| /external/u-boot/arch/x86/cpu/ivybridge/ |
| D | lpc.c | 131 u8 reg8; in pch_power_options() local
238 u8 reg8; in pch_rtc_init() local
386 u8 reg8; in pch_disable_smm_only_flashing() local
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| D | northbridge.c | 184 u8 reg8; in bd82x6x_northbridge_early_init() local
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| /external/u-boot/board/esd/vme8349/ |
| D | pci.c | 57 u8 reg8; in pci_init_board() local
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| /external/u-boot/board/freescale/mpc8349itx/ |
| D | pci.c | 69 u8 reg8; in pci_init_board() local
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| /external/u-boot/arch/x86/cpu/intel_common/ |
| D | lpc.c | 21 u8 reg8; in enable_spi_prefetch() local
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| /external/u-boot/drivers/video/ |
| D | ivybridge_igd.c | 657 u8 reg8; in sandybridge_setup_graphics() local
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| /external/libvpx/libvpx/vpx_dsp/mips/ |
| D | idct16x16_msa.c | 15 v8i16 reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14; in vpx_idct16_1d_rows_msa() local
109 v8i16 reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14; in vpx_idct16_1d_columns_addblk_msa() local
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| /external/u-boot/board/gdsys/common/ |
| D | osd.c | 203 u8 reg0, reg4, reg8, reg12, reg18, reg20; in ics8n3qv01_set() local
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| /external/libvpx/libvpx/third_party/libyuv/source/ |
| D | scale_msa.cc | 767 v8i16 reg6, reg7, reg8, reg9, reg10, reg11; in ScaleRowDown34_0_Box_MSA() local
861 v8i16 reg6, reg7, reg8, reg9, reg10, reg11; in ScaleRowDown34_1_Box_MSA() local
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| D | row_msa.cc | 826 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; in ARGBToUVRow_MSA() local
2678 v4i32 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; in I444ToARGBRow_MSA() local
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| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.cc | 5943 const CPURegister& reg8) { in AreAliased()
5982 const CPURegister& reg8) { in AreSameSizeAndType()
6002 const CPURegister& reg8) { in AreEven()
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| /external/libyuv/files/source/ |
| D | row_msa.cc | 826 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; in ARGBToUVRow_MSA() local
2666 v4i32 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; in I444ToARGBRow_MSA() local
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| /external/v8/src/arm64/ |
| D | assembler-arm64.cc | 221 const CPURegister& reg7, const CPURegister& reg8) { in AreAliased()
258 const CPURegister& reg7, const CPURegister& reg8) { in AreSameSizeAndType()
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