1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * pci.c -- esd VME8349 PCI board support.
4 * Copyright (c) 2006 Wind River Systems, Inc.
5 * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
6 * Copyright (c) 2009 esd gmbh.
7 *
8 * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
9 *
10 * Based on MPC8349 PCI support but w/o PIB related code.
11 */
12
13 #include <asm/mmu.h>
14 #include <asm/io.h>
15 #include <common.h>
16 #include <mpc83xx.h>
17 #include <pci.h>
18 #include <i2c.h>
19 #include <asm/fsl_i2c.h>
20 #include "vme8349pin.h"
21
22 static struct pci_region pci1_regions[] = {
23 {
24 bus_start: CONFIG_SYS_PCI1_MEM_BASE,
25 phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
26 size: CONFIG_SYS_PCI1_MEM_SIZE,
27 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
28 },
29 {
30 bus_start: CONFIG_SYS_PCI1_IO_BASE,
31 phys_start: CONFIG_SYS_PCI1_IO_PHYS,
32 size: CONFIG_SYS_PCI1_IO_SIZE,
33 flags: PCI_REGION_IO
34 },
35 {
36 bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
37 phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
38 size: CONFIG_SYS_PCI1_MMIO_SIZE,
39 flags: PCI_REGION_MEM
40 },
41 };
42
43 /*
44 * pci_init_board()
45 *
46 * NOTICE: PCI2 is not supported. There is only one
47 * physical PCI slot on the board.
48 *
49 */
50 void
pci_init_board(void)51 pci_init_board(void)
52 {
53 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
54 volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
55 volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
56 struct pci_region *reg[] = { pci1_regions };
57 u8 reg8;
58 int monarch = 0;
59
60 i2c_set_bus_num(1);
61 /* Read the PCI_M66EN jumper setting */
62 if ((i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, ®8, 1) == 0) ||
63 (i2c_read(0x38 , 0, 0, ®8, 1) == 0)) {
64 if (reg8 & 0x40) {
65 clk->occr = 0xff000000; /* 66 MHz PCI */
66 printf("PCI: 66MHz\n");
67 } else {
68 clk->occr = 0xffff0003; /* 33 MHz PCI */
69 printf("PCI: 33MHz\n");
70 }
71 if (((reg8 & 0x01) == 0) || ((reg8 & 0x02) == 0))
72 monarch = 1;
73 } else {
74 clk->occr = 0xffff0003; /* 33 MHz PCI */
75 printf("PCI: 33MHz (I2C read failed)\n");
76 }
77 udelay(2000);
78
79 /*
80 * Assert/deassert VME reset
81 */
82 clrsetbits_be32(&immr->gpio[1].dat,
83 GPIO2_TSI_POWERUP_RESET_N | GPIO2_TSI_PLL_RESET_N,
84 GPIO2_VME_RESET_N | GPIO2_L_RESET_EN_N);
85 setbits_be32(&immr->gpio[1].dir, GPIO2_TSI_PLL_RESET_N |
86 GPIO2_TSI_POWERUP_RESET_N |
87 GPIO2_VME_RESET_N |
88 GPIO2_L_RESET_EN_N);
89 clrbits_be32(&immr->gpio[1].dir, GPIO2_V_SCON);
90 udelay(200);
91 setbits_be32(&immr->gpio[1].dat, GPIO2_TSI_PLL_RESET_N);
92 udelay(200);
93 setbits_be32(&immr->gpio[1].dat, GPIO2_TSI_POWERUP_RESET_N);
94 udelay(600000);
95 clrbits_be32(&immr->gpio[1].dat, GPIO2_L_RESET_EN_N);
96
97 /* Configure PCI Local Access Windows */
98 pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
99 pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
100
101 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
102 pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
103
104 udelay(2000);
105
106 if (monarch == 0) {
107 mpc83xx_pci_init(1, reg);
108 } else {
109 /*
110 * Release PCI RST Output signal
111 */
112 out_be32(&immr->pci_ctrl[0].gcr, 0);
113 udelay(2000);
114 out_be32(&immr->pci_ctrl[0].gcr, 1);
115 }
116 }
117