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/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InferAddressSpaces/AMDGPU/
Dmem-intrinsics.ll1 ; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -infer-address-spaces %s | FileCheck %s
3 ; CHECK-LABEL: @memset_group_to_flat(
4 ; CHECK: call void @llvm.memset.p3i8.i64(i8 addrspace(3)* align 4 %group.ptr, i8 4, i64 32, i1 fals…
6 %cast = addrspacecast i8 addrspace(3)* %group.ptr to i8*
7 …call void @llvm.memset.p0i8.i64(i8* align 4 %cast, i8 4, i64 32, i1 false), !tbaa !0, !alias.scope…
11 ; CHECK-LABEL: @memset_global_to_flat(
12 ; CHECK: call void @llvm.memset.p1i8.i64(i8 addrspace(1)* align 4 %global.ptr, i8 4, i64 32, i1 fal…
14 %cast = addrspacecast i8 addrspace(1)* %global.ptr to i8*
15 …call void @llvm.memset.p0i8.i64(i8* align 4 %cast, i8 4, i64 32, i1 false), !tbaa !0, !alias.scope…
19 ; CHECK-LABEL: @memset_group_to_flat_no_md(
[all …]
Dbasic.ll1 ; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -infer-address-spaces %s | FileCheck %s
5 ; CHECK-LABEL: @load_global_from_flat(
6 ; CHECK-NEXT: %tmp0 = addrspacecast float* %generic_scalar to float addrspace(1)*
7 ; CHECK-NEXT: %tmp1 = load float, float addrspace(1)* %tmp0
8 ; CHECK-NEXT: ret float %tmp1
15 ; CHECK-LABEL: @load_constant_from_flat(
16 ; CHECK-NEXT: %tmp0 = addrspacecast float* %generic_scalar to float addrspace(2)*
17 ; CHECK-NEXT: %tmp1 = load float, float addrspace(2)* %tmp0
18 ; CHECK-NEXT: ret float %tmp1
25 ; CHECK-LABEL: @load_group_from_flat(
[all …]
Dvolatile.ll1 ; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -infer-address-spaces %s | FileCheck %s
5 ; CHECK-LABEL: @volatile_load_flat_from_global(
11 %val = load volatile i32, i32* %tmp0, align 4
12 store i32 %val, i32* %tmp1, align 4
16 ; CHECK-LABEL: @volatile_load_flat_from_constant(
22 %val = load volatile i32, i32* %tmp0, align 4
23 store i32 %val, i32* %tmp1, align 4
27 ; CHECK-LABEL: @volatile_load_flat_from_group(
33 %val = load volatile i32, i32* %tmp0, align 4
34 store i32 %val, i32* %tmp1, align 4
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/MemCpyOpt/
Dmemcpy-to-memset-with-lifetimes.ll1 ; RUN: opt -basicaa -memcpyopt -instcombine -S < %s | FileCheck %s
3 target datalayout = "e-i64:64-f80:128-n8:16:32:64-S128"
4 target triple = "x86_64-unknown-linux-gnu"
7 entry-block:
8 %a = alloca [8 x i64], align 8
9 %a.cast = bitcast [8 x i64]* %a to i8*
10 call void @llvm.lifetime.start.p0i8(i64 64, i8* %a.cast)
11 call void @llvm.memset.p0i8.i64(i8* align 8 %a.cast, i8 0, i64 64, i1 false)
12 %sret.cast = bitcast [8 x i64]* %sret to i8*
13 …call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 %sret.cast, i8* align 8 %a.cast, i64 64, i1 false)
[all …]
Dalign.ll1 ; RUN: opt < %s -S -basicaa -memcpyopt | FileCheck %s
2 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v…
7 ; The resulting memset is only 4-byte aligned, despite containing
8 ; a 16-byte aligned store in the middle.
11 ; CHECK-LABEL: @foo(
12 ; CHECK: call void @llvm.memset.p0i8.i64(i8* align 4 {{.*}}, i8 0, i64 16, i1 false)
14 store i32 0, i32* %a0, align 4
16 store i32 0, i32* %a1, align 16
18 store i32 0, i32* %a2, align 4
20 store i32 0, i32* %a3, align 4
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Daddrspacecast-captured.ll1 ; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -mcpu=kaveri -amdgpu-promote-alloca < %s | FileCheck %s
7 ; CHECK-LABEL: @addrspacecast_captured(
8 ; CHECK: %data = alloca i32, align 4
9 ; CHECK: %cast = addrspacecast i32* %data to i32 addrspace(4)*
10 ; CHECK: %ptr2int = ptrtoint i32 addrspace(4)* %cast to i32
14 %data = alloca i32, align 4
15 %cast = addrspacecast i32* %data to i32 addrspace(4)*
16 %ptr2int = ptrtoint i32 addrspace(4)* %cast to i32
21 ; CHECK-LABEL: @addrspacecast_captured_store(
22 ; CHECK: %data = alloca i32, align 4
[all …]
Duint_to_fp.f64.ll1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
5 ; SI-LABEL: {{^}}v_uint_to_fp_i64_to_f64
6 ; SI: buffer_load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}
7 ; SI-DAG: v_cvt_f64_u32_e32 [[HI_CONV:v\[[0-9]+:[0-9]+\]]], v[[HI]]
8 ; SI-DAG: v_cvt_f64_u32_e32 [[LO_CONV:v\[[0-9]+:[0-9]+\]]], v[[LO]]
9 ; SI-DAG: v_ldexp_f64 [[LDEXP:v\[[0-9]+:[0-9]+\]]], [[HI_CONV]], 32
10 ; SI: v_add_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[LDEXP]], [[LO_CONV]]
15 %val = load i64, i64 addrspace(1)* %gep, align 8
21 ; SI-LABEL: {{^}}s_uint_to_fp_i64_to_f64
23 %cast = uitofp i64 %in to double
[all …]
Dfp_to_uint.f64.ll1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
2 ; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=CI -che…
7 ; SI-LABEL: {{^}}fp_to_uint_i32_f64:
10 %cast = fptoui double %in to i32
11 store i32 %cast, i32 addrspace(1)* %out, align 4
15 ; SI-LABEL: @fp_to_uint_v2i32_v2f64
19 %cast = fptoui <2 x double> %in to <2 x i32>
20 store <2 x i32> %cast, <2 x i32> addrspace(1)* %out, align 8
24 ; SI-LABEL: @fp_to_uint_v4i32_v4f64
30 %cast = fptoui <4 x double> %in to <4 x i32>
[all …]
Drewrite-out-arguments.ll1 ; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -amdgpu-rewrite-out-arguments < %s | FileCheck %s
43 ; CHECK-LABEL: define void @no_ret_blocks() #0 {
44 ; CHECK-NEXT: unreachable
49 ; CHECK-LABEL: @void_one_out_arg_i32_no_use(
50 ; CHECK-NEXT: ret void
55 ; CHECK-NOT: define
56 ; CHECK-LABEL: define void @skip_byval_arg(
57 ; CHECK-NEXT: store i32 0, i32* %val
58 ; CHECK-NEXT: ret void
64 ; CHECK-NOT: define
[all …]
/external/llvm/test/CodeGen/AMDGPU/
Duint_to_fp.f64.ll1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
5 ; SI-LABEL: {{^}}v_uint_to_fp_i64_to_f64
6 ; SI: buffer_load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}
7 ; SI-DAG: v_cvt_f64_u32_e32 [[HI_CONV:v\[[0-9]+:[0-9]+\]]], v[[HI]]
8 ; SI-DAG: v_cvt_f64_u32_e32 [[LO_CONV:v\[[0-9]+:[0-9]+\]]], v[[LO]]
9 ; SI-DAG: v_ldexp_f64 [[LDEXP:v\[[0-9]+:[0-9]+\]]], [[HI_CONV]], 32
10 ; SI: v_add_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[LDEXP]], [[LO_CONV]]
15 %val = load i64, i64 addrspace(1)* %gep, align 8
21 ; SI-LABEL: {{^}}s_uint_to_fp_i64_to_f64
23 %cast = uitofp i64 %in to double
[all …]
Dfp_to_uint.f64.ll1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
2 ; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=CI -che…
6 ; SI-LABEL: {{^}}fp_to_uint_i32_f64:
9 %cast = fptoui double %in to i32
10 store i32 %cast, i32 addrspace(1)* %out, align 4
14 ; SI-LABEL: @fp_to_uint_v2i32_v2f64
18 %cast = fptoui <2 x double> %in to <2 x i32>
19 store <2 x i32> %cast, <2 x i32> addrspace(1)* %out, align 8
23 ; SI-LABEL: @fp_to_uint_v4i32_v4f64
29 %cast = fptoui <4 x double> %in to <4 x i32>
[all …]
/external/llvm/test/CodeGen/NVPTX/
Daccess-non-generic.ll1 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s --check-prefix PTX
2 ; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s --check-prefix PTX
3 ; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 -nvptx-use-infer-addrspace | FileCheck %s --check-prefi…
4 ; RUN: opt < %s -S -nvptx-favor-non-generic -dce | FileCheck %s --check-prefix IR
5 ; RUN: opt < %s -S -nvptx-infer-addrspace | FileCheck %s --check-prefix IR --check-prefix IR-WITH-L…
7 @array = internal addrspace(3) global [10 x float] zeroinitializer, align 4
8 @scalar = internal addrspace(3) global float 0.000000e+00, align 4
9 @generic_scalar = internal global float 0.000000e+00, align 4
17 ; Verifies nvptx-favor-non-generic correctly optimizes generic address space
18 ; usage to non-generic address space usage for the patterns we claim to handle:
[all …]
Dmisaligned-vector-ldst.ll1 ; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s
3 …t datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:1…
4 target triple = "nvptx64-nvidia-cuda"
6 ; CHECK-LABEL: t1
8 ; CHECK-NOT: ld.v4
9 ; CHECK-NOT: ld.v2
10 ; CHECK-NOT: ld.f32
12 %cast = bitcast i8* %p1 to <4 x float>*
13 %r = load <4 x float>, <4 x float>* %cast, align 1
17 ; CHECK-LABEL: t2
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/NVPTX/
Daccess-non-generic.ll1 ; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s --check-prefix PTX
2 ; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s --check-prefix PTX
3 ; RUN: opt -mtriple=nvptx-- < %s -S -infer-address-spaces | FileCheck %s --check-prefix IR
4 ; RUN: opt -mtriple=nvptx64-- < %s -S -infer-address-spaces | FileCheck %s --check-prefix IR
6 @array = internal addrspace(3) global [10 x float] zeroinitializer, align 4
7 @scalar = internal addrspace(3) global float 0.000000e+00, align 4
9 ; Verifies nvptx-favor-non-generic correctly optimizes generic address space
10 ; usage to non-generic address space usage for the patterns we claim to handle:
11 ; 1. load cast
12 ; 2. store cast
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/SROA/
Daddress-spaces.ll1 ; RUN: opt < %s -sroa -S | FileCheck %s
2 …t datalayout = "e-p:64:64:64-p1:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64…
12 ; CHECK-LABEL: @test_address_space_1_1(
13 ; CHECK: load <2 x i64>, <2 x i64> addrspace(1)* %a, align 2
14 ; CHECK: store <2 x i64> {{.*}}, <2 x i64> addrspace(1)* {{.*}}, align 2
16 %aa = alloca <2 x i64>, align 16
19 …call void @llvm.memcpy.p0i8.p1i8.i32(i8* align 2 %aaptr, i8 addrspace(1)* align 2 %aptr, i32 16, i…
21 …call void @llvm.memcpy.p1i8.p0i8.i32(i8 addrspace(1)* align 2 %bptr, i8* align 2 %aaptr, i32 16, i…
26 ; CHECK-LABEL: @test_address_space_1_0(
27 ; CHECK: load <2 x i64>, <2 x i64> addrspace(1)* %a, align 2
[all …]
Dpreserve-nonnull.ll1 ; RUN: opt < %s -sroa -S | FileCheck %s
10 ; CHECK-LABEL: define i8* @propagate_nonnull(
11 ; CHECK-NEXT: entry:
12 ; CHECK-NEXT: %[[A:.*]] = alloca i8*
13 ; CHECK-NEXT: %[[V_CAST:.*]] = bitcast i32* %v to i8*
14 ; CHECK-NEXT: store i8* %[[V_CAST]], i8** %[[A]]
15 ; CHECK-NEXT: %[[LOAD:.*]] = load volatile i8*, i8** %[[A]], !nonnull !0
16 ; CHECK-NEXT: ret i8* %[[LOAD]]
21 %a.gep0.cast = bitcast i8** %a.gep0 to i32**
22 %a.gep1.cast = bitcast i8** %a.gep1 to i32**
[all …]
/external/llvm/test/Transforms/InstCombine/
Dbitcast-alias-function.ll1 ; RUN: opt -S -instcombine -o - %s | FileCheck %s
2 target datalayout = "e-p:32:32:32-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:3…
8 ; Test cast between scalars with same bit sizes
11 ; Test cast between vectors with same number of elements and bit sizes
14 ; Test cast from vector to scalar with same number of bits
17 ; Test cast from scalar to vector with same number of bits
20 ; Test cast between vectors of pointers
26 ; Test cast between scalars with different bit sizes
29 ; Test cast between vectors with different bit sizes but the
33 ; Test cast between vectors with same number of bits and different
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/
Dbitcast-alias-function.ll1 ; RUN: opt -S -instcombine -o - %s | FileCheck %s
2 target datalayout = "e-p:32:32:32-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:3…
8 ; Test cast between scalars with same bit sizes
11 ; Test cast between vectors with same number of elements and bit sizes
14 ; Test cast from vector to scalar with same number of bits
17 ; Test cast from scalar to vector with same number of bits
20 ; Test cast between vectors of pointers
26 ; Test cast between scalars with different bit sizes
29 ; Test cast between vectors with different bit sizes but the
33 ; Test cast between vectors with same number of bits and different
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/GVN/PRE/
Dpre-after-rle.ll1 ; RUN: opt -gvn -S < %s | FileCheck %s
8 ; CHECK-LABEL: @fn1
11 %call.cast = bitcast i8* %call to i32*
12 store i32* %call.cast, i32** %start, align 8
19 ; CHECK-LABEL: preheader.body_crit_edge:
20 ; CHECK: load i32, i32* %width, align 8
22 ; CHECK-LABEL: body:
23 ; CHECK-NOT: load i32*, i32** %start, align 8
24 ; CHECK-NOT: load i32, i32* %width, align 8
27 %s = load i32*, i32** %start, align 8
[all …]
/external/llvm/test/Transforms/GVN/
Dassume-equal.ll1 ; RUN: opt < %s -gvn -S | FileCheck %s
4 …2 (%struct.A*)* @_ZN1A3fooEv to i8*), i8* bitcast (i32 (%struct.A*)* @_ZN1A3barEv to i8*)], align 8
10 ; CHECK-LABEL: define void @_Z1gb(
18 %vtable = load i8**, i8*** %1, align 8
24 %vtable1.cast = bitcast i8** %vtable to i32 (%struct.A*)**
25 %2 = load i32 (%struct.A*)*, i32 (%struct.A*)** %vtable1.cast, align 8
37 %3 = load i32 (%struct.A*)*, i32 (%struct.A*)** %vfn4, align 8
47 ; CHECK-LABEL: define void @invariantGroupHandling(i1 zeroext %p) {
54 %vtable = load i8**, i8*** %1, align 8, !invariant.group !0
60 %vtable1.cast = bitcast i8** %vtable to i32 (%struct.A*)**
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/GVN/
Dassume-equal.ll1 ; RUN: opt < %s -gvn -S | FileCheck %s
4 …2 (%struct.A*)* @_ZN1A3fooEv to i8*), i8* bitcast (i32 (%struct.A*)* @_ZN1A3barEv to i8*)], align 8
10 ; CHECK-LABEL: define void @_Z1gb(
18 %vtable = load i8**, i8*** %1, align 8
24 %vtable1.cast = bitcast i8** %vtable to i32 (%struct.A*)**
25 %2 = load i32 (%struct.A*)*, i32 (%struct.A*)** %vtable1.cast, align 8
37 %3 = load i32 (%struct.A*)*, i32 (%struct.A*)** %vfn4, align 8
47 ; CHECK-LABEL: define void @invariantGroupHandling(i1 zeroext %p) {
54 %vtable = load i8**, i8*** %1, align 8, !invariant.group !0
60 %vtable1.cast = bitcast i8** %vtable to i32 (%struct.A*)**
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/NewGVN/
Dassume-equal.ll2 ; RUN: opt < %s -newgvn -S | FileCheck %s
5 …2 (%struct.A*)* @_ZN1A3fooEv to i8*), i8* bitcast (i32 (%struct.A*)* @_ZN1A3barEv to i8*)], align 8
11 ; CHECK-LABEL: define void @_Z1gb(
19 %vtable = load i8**, i8*** %1, align 8
25 %vtable1.cast = bitcast i8** %vtable to i32 (%struct.A*)**
26 %2 = load i32 (%struct.A*)*, i32 (%struct.A*)** %vtable1.cast, align 8
38 %3 = load i32 (%struct.A*)*, i32 (%struct.A*)** %vfn4, align 8
48 ; CHECK-LABEL: define void @invariantGroupHandling(i1 zeroext %p) {
55 %vtable = load i8**, i8*** %1, align 8, !invariant.group !0
61 %vtable1.cast = bitcast i8** %vtable to i32 (%struct.A*)**
[all …]
/external/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/
Dpointer-elements.ll1 ; RUN: opt -mtriple=amdgcn-amd-amdhsa -basicaa -load-store-vectorizer -S -o - %s | FileCheck %s
3 …-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64-i64:64-v16:16-v24:32-v32:32-v48:64…
7 ; CHECK-LABEL: @merge_v2p1i8(
9 ; CHECK: inttoptr i64 %{{[0-9]+}} to i8 addrspace(1)*
10 ; CHECK: inttoptr i64 %{{[0-9]+}} to i8 addrspace(1)*
17 %ld.c = load i8 addrspace(1)*, i8 addrspace(1)* addrspace(1)* %b, align 4
18 %ld.c.idx.1 = load i8 addrspace(1)*, i8 addrspace(1)* addrspace(1)* %b.1, align 4
20 store i8 addrspace(1)* null, i8 addrspace(1)* addrspace(1)* %a, align 4
21 store i8 addrspace(1)* null, i8 addrspace(1)* addrspace(1)* %a.1, align 4
26 ; CHECK-LABEL: @merge_v2p3i8(
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/
Dpointer-elements.ll1 ; RUN: opt -mtriple=amdgcn-amd-amdhsa -basicaa -load-store-vectorizer -S -o - %s | FileCheck %s
3 …-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64-i64:64-v16:16-v24:32-v32:32-v48:64…
7 ; CHECK-LABEL: @merge_v2p1i8(
17 %ld.c = load i8 addrspace(1)*, i8 addrspace(1)* addrspace(1)* %b, align 4
18 %ld.c.idx.1 = load i8 addrspace(1)*, i8 addrspace(1)* addrspace(1)* %b.1, align 4
20 store i8 addrspace(1)* null, i8 addrspace(1)* addrspace(1)* %a, align 4
21 store i8 addrspace(1)* null, i8 addrspace(1)* addrspace(1)* %a.1, align 4
26 ; CHECK-LABEL: @merge_v2p3i8(
36 %ld.c = load i8 addrspace(3)*, i8 addrspace(3)* addrspace(3)* %b, align 4
37 %ld.c.idx.1 = load i8 addrspace(3)*, i8 addrspace(3)* addrspace(3)* %b.1, align 4
[all …]
/external/llvm/test/Transforms/MemCpyOpt/
Dalign.ll1 ; RUN: opt < %s -S -basicaa -memcpyopt | FileCheck %s
2 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v…
7 ; The resulting memset is only 4-byte aligned, despite containing
8 ; a 16-byte aligned store in the middle.
11 ; CHECK-LABEL: @foo(
14 store i32 0, i32* %a0, align 4
16 store i32 0, i32* %a1, align 16
18 store i32 0, i32* %a2, align 4
20 store i32 0, i32* %a3, align 4
27 ; CHECK-LABEL: @bar(
[all …]

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