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/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/
DX86GenEVEX2VEXTables.inc3 |* X86 EVEX2VEX tables *|
9 // X86 EVEX encoded instructions that have a VEX 128 encoding
13 { X86::VADDPDZ128rm, X86::VADDPDrm },
14 { X86::VADDPDZ128rr, X86::VADDPDrr },
15 { X86::VADDPSZ128rm, X86::VADDPSrm },
16 { X86::VADDPSZ128rr, X86::VADDPSrr },
17 { X86::VADDSDZrm, X86::VADDSDrm },
18 { X86::VADDSDZrm_Int, X86::VADDSDrm_Int },
19 { X86::VADDSDZrr, X86::VADDSDrr },
20 { X86::VADDSDZrr_Int, X86::VADDSDrr_Int },
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DX86GenRegisterInfo.inc18 namespace X86 {
299 } // end namespace X86
303 namespace X86 {
393 } // end namespace X86
398 namespace X86 {
411 } // end namespace X86
1085 { X86::AH },
1086 { X86::AL },
1087 { X86::BH },
1088 { X86::BL },
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86InstrFoldTables.cpp1 //===-- X86InstrFoldTables.cpp - X86 Instruction Folding Tables -----------===//
10 // This file contains the X86 memory folding tables.
32 // because as new instruction are added into holes in the X86 opcode map they
37 { X86::ADC16ri, X86::ADC16mi, 0 },
38 { X86::ADC16ri8, X86::ADC16mi8, 0 },
39 { X86::ADC16rr, X86::ADC16mr, 0 },
40 { X86::ADC32ri, X86::ADC32mi, 0 },
41 { X86::ADC32ri8, X86::ADC32mi8, 0 },
42 { X86::ADC32rr, X86::ADC32mr, 0 },
43 { X86::ADC64ri32, X86::ADC64mi32, 0 },
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DX86InstrInfo.cpp1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
15 #include "X86.h"
46 #define DEBUG_TYPE "x86-instr-info"
58 " fuse, but the X86 backend currently can't"),
81 : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64 in X86InstrInfo()
82 : X86::ADJCALLSTACKDOWN32), in X86InstrInfo()
83 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64 in X86InstrInfo()
84 : X86::ADJCALLSTACKUP32), in X86InstrInfo()
85 X86::CATCHRET, in X86InstrInfo()
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DX86MacroFusion.cpp1 //===- X86MacroFusion.cpp - X86 Macro Fusion ------------------------------===//
10 /// \file This file contains the X86 implementation of the DAG scheduling
42 : static_cast<unsigned>(X86::INSTRUCTION_LIST_END); in shouldScheduleAdjacent()
48 case X86::JE_1: in shouldScheduleAdjacent()
49 case X86::JNE_1: in shouldScheduleAdjacent()
50 case X86::JL_1: in shouldScheduleAdjacent()
51 case X86::JLE_1: in shouldScheduleAdjacent()
52 case X86::JG_1: in shouldScheduleAdjacent()
53 case X86::JGE_1: in shouldScheduleAdjacent()
56 case X86::JB_1: in shouldScheduleAdjacent()
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/external/llvm/lib/Target/X86/
DX86InstrInfo.cpp1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
15 #include "X86.h"
44 #define DEBUG_TYPE "x86-instr-info"
55 " fuse, but the X86 backend currently can't"),
116 : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64 in X86InstrInfo()
117 : X86::ADJCALLSTACKDOWN32), in X86InstrInfo()
118 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64 in X86InstrInfo()
119 : X86::ADJCALLSTACKUP32), in X86InstrInfo()
120 X86::CATCHRET, in X86InstrInfo()
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/external/llvm/lib/Target/X86/MCTargetDesc/
DX86MCTargetDesc.cpp1 //===-- X86MCTargetDesc.cpp - X86 Target Descriptions ---------------------===//
10 // This file provides X86 specific target descriptions.
70 for (unsigned Reg = X86::NoRegister + 1; Reg < X86::NUM_TARGET_REGS; ++Reg) { in initLLVMToSEHAndCVRegMapping()
77 X86::AL, X86::CL, X86::DL, X86::BL, X86::AH, X86::CH, in initLLVMToSEHAndCVRegMapping()
78 X86::DH, X86::BH, X86::AX, X86::CX, X86::DX, X86::BX, in initLLVMToSEHAndCVRegMapping()
79 X86::SP, X86::BP, X86::SI, X86::DI, X86::EAX, X86::ECX, in initLLVMToSEHAndCVRegMapping()
80 X86::EDX, X86::EBX, X86::ESP, X86::EBP, X86::ESI, X86::EDI, in initLLVMToSEHAndCVRegMapping()
86 MRI->mapLLVMRegToCVReg(X86::EFLAGS, 34); in initLLVMToSEHAndCVRegMapping()
91 MRI->mapLLVMRegToCVReg(X86::FP0 + I, FP0Start + I); in initLLVMToSEHAndCVRegMapping()
96 MRI->mapLLVMRegToCVReg(X86::XMM0 + I, CVXMM0Start + I); in initLLVMToSEHAndCVRegMapping()
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/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrInfo.cpp1 //===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
10 // This file contains the X86 implementation of the TargetInstrInfo class.
15 #include "X86.h"
49 " fuse, but the X86 backend currently can't"),
88 ? X86::ADJCALLSTACKDOWN64 in X86InstrInfo()
89 : X86::ADJCALLSTACKDOWN32), in X86InstrInfo()
91 ? X86::ADJCALLSTACKUP64 in X86InstrInfo()
92 : X86::ADJCALLSTACKUP32)), in X86InstrInfo()
96 { X86::ADC32ri, X86::ADC32mi, 0 }, in X86InstrInfo()
97 { X86::ADC32ri8, X86::ADC32mi8, 0 }, in X86InstrInfo()
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DX86RegisterInfo.cpp1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
12 // on X86.
16 #include "X86.h"
56 ? X86::RIP : X86::EIP, in X86RegisterInfo()
69 StackPtr = X86::RSP; in X86RegisterInfo()
70 FramePtr = X86::RBP; in X86RegisterInfo()
73 StackPtr = X86::ESP; in X86RegisterInfo()
74 FramePtr = X86::EBP; in X86RegisterInfo()
82 case X86::EBX: case X86::RBX: return 1; in getCompactUnwindRegNum()
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DX86GenRegisterInfo.inc17 namespace X86 {
184 namespace X86 {
249 const unsigned AH_Overlaps[] = { X86::AH, X86::AX, X86::EAX, X86::RAX, 0 };
250 const unsigned AL_Overlaps[] = { X86::AL, X86::AX, X86::EAX, X86::RAX, 0 };
251 const unsigned AX_Overlaps[] = { X86::AX, X86::AH, X86::AL, X86::EAX, X86::RAX, 0 };
252 const unsigned BH_Overlaps[] = { X86::BH, X86::BX, X86::EBX, X86::RBX, 0 };
253 const unsigned BL_Overlaps[] = { X86::BL, X86::BX, X86::EBX, X86::RBX, 0 };
254 const unsigned BP_Overlaps[] = { X86::BP, X86::BPL, X86::EBP, X86::RBP, 0 };
255 const unsigned BPL_Overlaps[] = { X86::BPL, X86::BP, X86::EBP, X86::RBP, 0 };
256 const unsigned BX_Overlaps[] = { X86::BX, X86::BH, X86::BL, X86::EBX, X86::RBX, 0 };
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DX86GenSubtargetInfo.inc13 namespace X86 {
55 { "3dnow", "Enable 3DNow! instructions", X86::Feature3DNow, X86::FeatureMMX },
56 { "3dnowa", "Enable 3DNow! Athlon instructions", X86::Feature3DNowA, X86::Feature3DNow },
57 { "64bit", "Support 64-bit instructions", X86::Feature64Bit, X86::FeatureCMOV },
58 { "64bit-mode", "64-bit mode (x86_64)", X86::Mode64Bit, 0ULL },
59 { "aes", "Enable AES instructions", X86::FeatureAES, 0ULL },
60 { "avx", "Enable AVX instructions", X86::FeatureAVX, 0ULL },
61 { "bmi", "Support BMI instructions", X86::FeatureBMI, 0ULL },
62 { "clmul", "Enable carry-less multiplication instructions", X86::FeatureCLMUL, 0ULL },
63 { "cmov", "Enable conditional move instructions", X86::FeatureCMOV, 0ULL },
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DX86GenAsmMatcher.inc1792 Inst.addOperand(MCOperand::CreateReg(X86::ST0));
1795 Inst.addOperand(MCOperand::CreateReg(X86::ST1));
2623 case X86::AL: OpKind = MCK_AL; break;
2624 case X86::DL: OpKind = MCK_GR8_ABCD_L; break;
2625 case X86::CL: OpKind = MCK_CL; break;
2626 case X86::BL: OpKind = MCK_GR8_ABCD_L; break;
2627 case X86::SIL: OpKind = MCK_GR8; break;
2628 case X86::DIL: OpKind = MCK_GR8; break;
2629 case X86::BPL: OpKind = MCK_GR8; break;
2630 case X86::SPL: OpKind = MCK_GR8; break;
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/MCTargetDesc/
DX86MCTargetDesc.cpp1 //===-- X86MCTargetDesc.cpp - X86 Target Descriptions ---------------------===//
10 // This file provides X86 specific target descriptions.
74 for (unsigned Reg = X86::NoRegister + 1; Reg < X86::NUM_TARGET_REGS; ++Reg) { in initLLVMToSEHAndCVRegMapping()
84 { codeview::RegisterId::CVRegAL, X86::AL}, in initLLVMToSEHAndCVRegMapping()
85 { codeview::RegisterId::CVRegCL, X86::CL}, in initLLVMToSEHAndCVRegMapping()
86 { codeview::RegisterId::CVRegDL, X86::DL}, in initLLVMToSEHAndCVRegMapping()
87 { codeview::RegisterId::CVRegBL, X86::BL}, in initLLVMToSEHAndCVRegMapping()
88 { codeview::RegisterId::CVRegAH, X86::AH}, in initLLVMToSEHAndCVRegMapping()
89 { codeview::RegisterId::CVRegCH, X86::CH}, in initLLVMToSEHAndCVRegMapping()
90 { codeview::RegisterId::CVRegDH, X86::DH}, in initLLVMToSEHAndCVRegMapping()
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/external/clang/test/CodeGen/
Dcomplex-math.c1 … %clang_cc1 %s -O1 -emit-llvm -triple x86_64-unknown-unknown -o - | FileCheck %s --check-prefix=X86
2 // RUN: %clang_cc1 %s -O1 -emit-llvm -triple x86_64-pc-win64 -o - | FileCheck %s --check-prefix=X86
3 …N: %clang_cc1 %s -O1 -emit-llvm -triple i686-unknown-unknown -o - | FileCheck %s --check-prefix=X86
9 // X86-LABEL: @add_float_rr( in add_float_rr()
10 // X86: fadd in add_float_rr()
11 // X86-NOT: fadd in add_float_rr()
12 // X86: ret in add_float_rr()
16 // X86-LABEL: @add_float_cr( in add_float_cr()
17 // X86: fadd in add_float_cr()
18 // X86-NOT: fadd in add_float_cr()
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Dmmx-fold-load.ll2 ; RUN: llc < %s -mtriple=i686-unknown -mattr=+mmx,+sse2 | FileCheck %s --check-prefix=X86
6 ; X86-LABEL: t0:
7 ; X86: # %bb.0: # %entry
8 ; X86-NEXT: pushl %ebp
9 ; X86-NEXT: movl %esp, %ebp
10 ; X86-NEXT: andl $-8, %esp
11 ; X86-NEXT: subl $8, %esp
12 ; X86-NEXT: movl 12(%ebp), %eax
13 ; X86-NEXT: movl 8(%ebp), %ecx
14 ; X86-NEXT: movq (%ecx), %mm0
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Dbtc_bts_btr.ll3 ; RUN: llc < %s -mtriple=i386-pc-linux | FileCheck %s --check-prefix=X86
16 ; X86-LABEL: btr_16:
17 ; X86: # %bb.0:
18 ; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
19 ; X86-NEXT: movb {{[0-9]+}}(%esp), %cl
20 ; X86-NEXT: btrw %cx, %ax
21 ; X86-NEXT: retl
35 ; X86-LABEL: bts_16:
36 ; X86: # %bb.0:
37 ; X86-NEXT: movb {{[0-9]+}}(%esp), %cl
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Dgpr-to-mask.ll2 …86_64-unknown-unknown -mattr=+avx512f,+avx512bw,+avx512dq < %s | FileCheck %s --check-prefix=X86-64
3 …=i386-unknown-unknown -mattr=+avx512f,+avx512bw,+avx512dq < %s | FileCheck %s --check-prefix=X86-32
6 ; X86-64-LABEL: test_fcmp_storefloat:
7 ; X86-64: # %bb.0: # %entry
8 ; X86-64-NEXT: testb $1, %dil
9 ; X86-64-NEXT: je .LBB0_2
10 ; X86-64-NEXT: # %bb.1: # %if
11 ; X86-64-NEXT: vcmpeqss %xmm3, %xmm2, %k1
12 ; X86-64-NEXT: jmp .LBB0_3
13 ; X86-64-NEXT: .LBB0_2: # %else
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Di128-mul.ll2 ; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s --check-prefixes=X86,X86-NOBMI
3 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+bmi2 | FileCheck %s --check-prefixes=X86,X86-…
10 ; X86-NOBMI-LABEL: foo:
11 ; X86-NOBMI: # %bb.0:
12 ; X86-NOBMI-NEXT: pushl %ebp
13 ; X86-NOBMI-NEXT: pushl %ebx
14 ; X86-NOBMI-NEXT: pushl %edi
15 ; X86-NOBMI-NEXT: pushl %esi
16 ; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %ecx
17 ; X86-NOBMI-NEXT: movl {{[0-9]+}}(%esp), %esi
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Dextract-lowbits.ll2 …own-linux-gnu -mattr=-bmi,-tbm,-bmi2 < %s | FileCheck %s --check-prefixes=CHECK,X86,NOBMI,X86-NOBMI
3 …known-linux-gnu -mattr=+bmi,-tbm,-bmi2 < %s | FileCheck %s --check-prefixes=CHECK,X86,BMI1,X86-BMI1
4 …tr=+bmi,+tbm,-bmi2 < %s | FileCheck %s --check-prefixes=CHECK,X86,BMI1,X86-BMI1,BMI1TBM,X86-BMI1TBM
5 … | FileCheck %s --check-prefixes=CHECK,X86,BMI1,X86-BMI1,BMI1BMI2,X86-BMI1BMI2,BMI1TBM,X86-BMI1TBM…
6 …bmi2 < %s | FileCheck %s --check-prefixes=CHECK,X86,BMI1,X86-BMI1,BMI1BMI2,X86-BMI1BMI2,BMI1NOTBMB…
31 ; X86-NOBMI-LABEL: bzhi32_a0:
32 ; X86-NOBMI: # %bb.0:
33 ; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %cl
34 ; X86-NOBMI-NEXT: movl $1, %eax
35 ; X86-NOBMI-NEXT: shll %cl, %eax
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Dmul-constant-result.ll2 ; RUN: llc < %s -mtriple=i686-unknown | FileCheck %s --check-prefix=X86
10 ; X86-LABEL: mult:
11 ; X86: # %bb.0:
12 ; X86-NEXT: pushl %esi
13 ; X86-NEXT: .cfi_def_cfa_offset 8
14 ; X86-NEXT: .cfi_offset %esi, -8
15 ; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
16 ; X86-NEXT: cmpl $1, %edx
17 ; X86-NEXT: movl $1, %eax
18 ; X86-NEXT: movl $1, %esi
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Drotate4.ll2 ; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s --check-prefixes=X86
9 ; X86-LABEL: rotate_left_32:
10 ; X86: # %bb.0:
11 ; X86-NEXT: movb {{[0-9]+}}(%esp), %cl
12 ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
13 ; X86-NEXT: roll %cl, %eax
14 ; X86-NEXT: retl
32 ; X86-LABEL: rotate_right_32:
33 ; X86: # %bb.0:
34 ; X86-NEXT: movb {{[0-9]+}}(%esp), %cl
[all …]
D3dnow-intrinsics.ll2 …RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+3dnow | FileCheck %s --check-prefixes=CHECK,X86
6 ; X86-LABEL: test_pavgusb:
7 ; X86: # %bb.0: # %entry
8 ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
9 ; X86-NEXT: pavgusb %mm1, %mm0
10 ; X86-NEXT: movq %mm0, (%eax)
11 ; X86-NEXT: retl $4
25 %4 = call x86_mmx @llvm.x86.3dnow.pavgusb(x86_mmx %2, x86_mmx %3)
30 declare x86_mmx @llvm.x86.3dnow.pavgusb(x86_mmx, x86_mmx) nounwind readnone
33 ; X86-LABEL: test_pf2id:
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Datomic32.ll3 …i686-unknown-unknown -mcpu=corei7 -verify-machineinstrs | FileCheck %s -check-prefixes=X86,X86-CMOV
4 …nown -mcpu=corei7 -mattr=-cmov -verify-machineinstrs | FileCheck %s --check-prefixes=X86,X86-NOCMOV
18 ; X86-LABEL: atomic_fetch_add32:
19 ; X86: # %bb.0: # %entry
20 ; X86-NEXT: lock incl sc32
21 ; X86-NEXT: lock addl $3, sc32
22 ; X86-NEXT: movl $5, %eax
23 ; X86-NEXT: lock xaddl %eax, sc32
24 ; X86-NEXT: lock addl %eax, sc32
25 ; X86-NEXT: retl
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/
DX86MCTargetDesc.cpp1 //===-- X86MCTargetDesc.cpp - X86 Target Descriptions -----------*- C++ -*-===//
10 // This file provides X86 specific target descriptions.
141 /// getX86RegNum - This function maps LLVM register identifiers to their X86
145 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX; in getX86RegNum()
146 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX; in getX86RegNum()
147 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX; in getX86RegNum()
148 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX; in getX86RegNum()
149 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH: in getX86RegNum()
151 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH: in getX86RegNum()
153 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH: in getX86RegNum()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/Disassembler/
DX86Disassembler.cpp1 //===-- X86Disassembler.cpp - Disassembler for x86 and x86_64 -------------===//
10 // This file is part of the X86 Disassembler.
15 // The X86 disassembler is a table-driven disassembler for the 16-, 32-, and
16 // 64-bit X86 instruction sets. The main decode sequence for an assembly
93 #define DEBUG_TYPE "x86-disassembler"
113 namespace X86 { namespace
132 /// Generic disassembler for all X86 platforms. All each platform class should
158 if (FB[X86::Mode16Bit]) { in X86GenericDisassembler()
161 } else if (FB[X86::Mode32Bit]) { in X86GenericDisassembler()
164 } else if (FB[X86::Mode64Bit]) { in X86GenericDisassembler()
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