1 //===-- X86MCTargetDesc.cpp - X86 Target Descriptions ---------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file provides X86 specific target descriptions.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "X86MCTargetDesc.h"
15 #include "InstPrinter/X86ATTInstPrinter.h"
16 #include "InstPrinter/X86IntelInstPrinter.h"
17 #include "X86BaseInfo.h"
18 #include "X86MCAsmInfo.h"
19 #include "llvm/ADT/APInt.h"
20 #include "llvm/ADT/Triple.h"
21 #include "llvm/DebugInfo/CodeView/CodeView.h"
22 #include "llvm/MC/MCInstrAnalysis.h"
23 #include "llvm/MC/MCInstrInfo.h"
24 #include "llvm/MC/MCRegisterInfo.h"
25 #include "llvm/MC/MCStreamer.h"
26 #include "llvm/MC/MCSubtargetInfo.h"
27 #include "llvm/MC/MachineLocation.h"
28 #include "llvm/Support/ErrorHandling.h"
29 #include "llvm/Support/Host.h"
30 #include "llvm/Support/TargetRegistry.h"
31
32 #if _MSC_VER
33 #include <intrin.h>
34 #endif
35
36 using namespace llvm;
37
38 #define GET_REGINFO_MC_DESC
39 #include "X86GenRegisterInfo.inc"
40
41 #define GET_INSTRINFO_MC_DESC
42 #define GET_GENINSTRINFO_MC_HELPERS
43 #include "X86GenInstrInfo.inc"
44
45 #define GET_SUBTARGETINFO_MC_DESC
46 #include "X86GenSubtargetInfo.inc"
47
ParseX86Triple(const Triple & TT)48 std::string X86_MC::ParseX86Triple(const Triple &TT) {
49 std::string FS;
50 if (TT.getArch() == Triple::x86_64)
51 FS = "+64bit-mode,-32bit-mode,-16bit-mode";
52 else if (TT.getEnvironment() != Triple::CODE16)
53 FS = "-64bit-mode,+32bit-mode,-16bit-mode";
54 else
55 FS = "-64bit-mode,-32bit-mode,+16bit-mode";
56
57 return FS;
58 }
59
getDwarfRegFlavour(const Triple & TT,bool isEH)60 unsigned X86_MC::getDwarfRegFlavour(const Triple &TT, bool isEH) {
61 if (TT.getArch() == Triple::x86_64)
62 return DWARFFlavour::X86_64;
63
64 if (TT.isOSDarwin())
65 return isEH ? DWARFFlavour::X86_32_DarwinEH : DWARFFlavour::X86_32_Generic;
66 if (TT.isOSCygMing())
67 // Unsupported by now, just quick fallback
68 return DWARFFlavour::X86_32_Generic;
69 return DWARFFlavour::X86_32_Generic;
70 }
71
initLLVMToSEHAndCVRegMapping(MCRegisterInfo * MRI)72 void X86_MC::initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI) {
73 // FIXME: TableGen these.
74 for (unsigned Reg = X86::NoRegister + 1; Reg < X86::NUM_TARGET_REGS; ++Reg) {
75 unsigned SEH = MRI->getEncodingValue(Reg);
76 MRI->mapLLVMRegToSEHReg(Reg, SEH);
77 }
78
79 // Mapping from CodeView to MC register id.
80 static const struct {
81 codeview::RegisterId CVReg;
82 MCPhysReg Reg;
83 } RegMap[] = {
84 { codeview::RegisterId::CVRegAL, X86::AL},
85 { codeview::RegisterId::CVRegCL, X86::CL},
86 { codeview::RegisterId::CVRegDL, X86::DL},
87 { codeview::RegisterId::CVRegBL, X86::BL},
88 { codeview::RegisterId::CVRegAH, X86::AH},
89 { codeview::RegisterId::CVRegCH, X86::CH},
90 { codeview::RegisterId::CVRegDH, X86::DH},
91 { codeview::RegisterId::CVRegBH, X86::BH},
92 { codeview::RegisterId::CVRegAX, X86::AX},
93 { codeview::RegisterId::CVRegCX, X86::CX},
94 { codeview::RegisterId::CVRegDX, X86::DX},
95 { codeview::RegisterId::CVRegBX, X86::BX},
96 { codeview::RegisterId::CVRegSP, X86::SP},
97 { codeview::RegisterId::CVRegBP, X86::BP},
98 { codeview::RegisterId::CVRegSI, X86::SI},
99 { codeview::RegisterId::CVRegDI, X86::DI},
100 { codeview::RegisterId::CVRegEAX, X86::EAX},
101 { codeview::RegisterId::CVRegECX, X86::ECX},
102 { codeview::RegisterId::CVRegEDX, X86::EDX},
103 { codeview::RegisterId::CVRegEBX, X86::EBX},
104 { codeview::RegisterId::CVRegESP, X86::ESP},
105 { codeview::RegisterId::CVRegEBP, X86::EBP},
106 { codeview::RegisterId::CVRegESI, X86::ESI},
107 { codeview::RegisterId::CVRegEDI, X86::EDI},
108
109 { codeview::RegisterId::CVRegEFLAGS, X86::EFLAGS},
110
111 { codeview::RegisterId::CVRegST0, X86::FP0},
112 { codeview::RegisterId::CVRegST1, X86::FP1},
113 { codeview::RegisterId::CVRegST2, X86::FP2},
114 { codeview::RegisterId::CVRegST3, X86::FP3},
115 { codeview::RegisterId::CVRegST4, X86::FP4},
116 { codeview::RegisterId::CVRegST5, X86::FP5},
117 { codeview::RegisterId::CVRegST6, X86::FP6},
118 { codeview::RegisterId::CVRegST7, X86::FP7},
119
120 { codeview::RegisterId::CVRegXMM0, X86::XMM0},
121 { codeview::RegisterId::CVRegXMM1, X86::XMM1},
122 { codeview::RegisterId::CVRegXMM2, X86::XMM2},
123 { codeview::RegisterId::CVRegXMM3, X86::XMM3},
124 { codeview::RegisterId::CVRegXMM4, X86::XMM4},
125 { codeview::RegisterId::CVRegXMM5, X86::XMM5},
126 { codeview::RegisterId::CVRegXMM6, X86::XMM6},
127 { codeview::RegisterId::CVRegXMM7, X86::XMM7},
128
129 { codeview::RegisterId::CVRegXMM8, X86::XMM8},
130 { codeview::RegisterId::CVRegXMM9, X86::XMM9},
131 { codeview::RegisterId::CVRegXMM10, X86::XMM10},
132 { codeview::RegisterId::CVRegXMM11, X86::XMM11},
133 { codeview::RegisterId::CVRegXMM12, X86::XMM12},
134 { codeview::RegisterId::CVRegXMM13, X86::XMM13},
135 { codeview::RegisterId::CVRegXMM14, X86::XMM14},
136 { codeview::RegisterId::CVRegXMM15, X86::XMM15},
137
138 { codeview::RegisterId::CVRegSIL, X86::SIL},
139 { codeview::RegisterId::CVRegDIL, X86::DIL},
140 { codeview::RegisterId::CVRegBPL, X86::BPL},
141 { codeview::RegisterId::CVRegSPL, X86::SPL},
142 { codeview::RegisterId::CVRegRAX, X86::RAX},
143 { codeview::RegisterId::CVRegRBX, X86::RBX},
144 { codeview::RegisterId::CVRegRCX, X86::RCX},
145 { codeview::RegisterId::CVRegRDX, X86::RDX},
146 { codeview::RegisterId::CVRegRSI, X86::RSI},
147 { codeview::RegisterId::CVRegRDI, X86::RDI},
148 { codeview::RegisterId::CVRegRBP, X86::RBP},
149 { codeview::RegisterId::CVRegRSP, X86::RSP},
150 { codeview::RegisterId::CVRegR8, X86::R8},
151 { codeview::RegisterId::CVRegR9, X86::R9},
152 { codeview::RegisterId::CVRegR10, X86::R10},
153 { codeview::RegisterId::CVRegR11, X86::R11},
154 { codeview::RegisterId::CVRegR12, X86::R12},
155 { codeview::RegisterId::CVRegR13, X86::R13},
156 { codeview::RegisterId::CVRegR14, X86::R14},
157 { codeview::RegisterId::CVRegR15, X86::R15},
158 { codeview::RegisterId::CVRegR8B, X86::R8B},
159 { codeview::RegisterId::CVRegR9B, X86::R9B},
160 { codeview::RegisterId::CVRegR10B, X86::R10B},
161 { codeview::RegisterId::CVRegR11B, X86::R11B},
162 { codeview::RegisterId::CVRegR12B, X86::R12B},
163 { codeview::RegisterId::CVRegR13B, X86::R13B},
164 { codeview::RegisterId::CVRegR14B, X86::R14B},
165 { codeview::RegisterId::CVRegR15B, X86::R15B},
166 { codeview::RegisterId::CVRegR8W, X86::R8W},
167 { codeview::RegisterId::CVRegR9W, X86::R9W},
168 { codeview::RegisterId::CVRegR10W, X86::R10W},
169 { codeview::RegisterId::CVRegR11W, X86::R11W},
170 { codeview::RegisterId::CVRegR12W, X86::R12W},
171 { codeview::RegisterId::CVRegR13W, X86::R13W},
172 { codeview::RegisterId::CVRegR14W, X86::R14W},
173 { codeview::RegisterId::CVRegR15W, X86::R15W},
174 { codeview::RegisterId::CVRegR8D, X86::R8D},
175 { codeview::RegisterId::CVRegR9D, X86::R9D},
176 { codeview::RegisterId::CVRegR10D, X86::R10D},
177 { codeview::RegisterId::CVRegR11D, X86::R11D},
178 { codeview::RegisterId::CVRegR12D, X86::R12D},
179 { codeview::RegisterId::CVRegR13D, X86::R13D},
180 { codeview::RegisterId::CVRegR14D, X86::R14D},
181 { codeview::RegisterId::CVRegR15D, X86::R15D},
182 { codeview::RegisterId::CVRegAMD64_YMM0, X86::YMM0},
183 { codeview::RegisterId::CVRegAMD64_YMM1, X86::YMM1},
184 { codeview::RegisterId::CVRegAMD64_YMM2, X86::YMM2},
185 { codeview::RegisterId::CVRegAMD64_YMM3, X86::YMM3},
186 { codeview::RegisterId::CVRegAMD64_YMM4, X86::YMM4},
187 { codeview::RegisterId::CVRegAMD64_YMM5, X86::YMM5},
188 { codeview::RegisterId::CVRegAMD64_YMM6, X86::YMM6},
189 { codeview::RegisterId::CVRegAMD64_YMM7, X86::YMM7},
190 { codeview::RegisterId::CVRegAMD64_YMM8, X86::YMM8},
191 { codeview::RegisterId::CVRegAMD64_YMM9, X86::YMM9},
192 { codeview::RegisterId::CVRegAMD64_YMM10, X86::YMM10},
193 { codeview::RegisterId::CVRegAMD64_YMM11, X86::YMM11},
194 { codeview::RegisterId::CVRegAMD64_YMM12, X86::YMM12},
195 { codeview::RegisterId::CVRegAMD64_YMM13, X86::YMM13},
196 { codeview::RegisterId::CVRegAMD64_YMM14, X86::YMM14},
197 { codeview::RegisterId::CVRegAMD64_YMM15, X86::YMM15},
198 };
199 for (unsigned I = 0; I < array_lengthof(RegMap); ++I)
200 MRI->mapLLVMRegToCVReg(RegMap[I].Reg, static_cast<int>(RegMap[I].CVReg));
201 }
202
createX86MCSubtargetInfo(const Triple & TT,StringRef CPU,StringRef FS)203 MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(const Triple &TT,
204 StringRef CPU, StringRef FS) {
205 std::string ArchFS = X86_MC::ParseX86Triple(TT);
206 if (!FS.empty()) {
207 if (!ArchFS.empty())
208 ArchFS = (Twine(ArchFS) + "," + FS).str();
209 else
210 ArchFS = FS;
211 }
212
213 std::string CPUName = CPU;
214 if (CPUName.empty())
215 CPUName = "generic";
216
217 return createX86MCSubtargetInfoImpl(TT, CPUName, ArchFS);
218 }
219
createX86MCInstrInfo()220 static MCInstrInfo *createX86MCInstrInfo() {
221 MCInstrInfo *X = new MCInstrInfo();
222 InitX86MCInstrInfo(X);
223 return X;
224 }
225
createX86MCRegisterInfo(const Triple & TT)226 static MCRegisterInfo *createX86MCRegisterInfo(const Triple &TT) {
227 unsigned RA = (TT.getArch() == Triple::x86_64)
228 ? X86::RIP // Should have dwarf #16.
229 : X86::EIP; // Should have dwarf #8.
230
231 MCRegisterInfo *X = new MCRegisterInfo();
232 InitX86MCRegisterInfo(X, RA, X86_MC::getDwarfRegFlavour(TT, false),
233 X86_MC::getDwarfRegFlavour(TT, true), RA);
234 X86_MC::initLLVMToSEHAndCVRegMapping(X);
235 return X;
236 }
237
createX86MCAsmInfo(const MCRegisterInfo & MRI,const Triple & TheTriple)238 static MCAsmInfo *createX86MCAsmInfo(const MCRegisterInfo &MRI,
239 const Triple &TheTriple) {
240 bool is64Bit = TheTriple.getArch() == Triple::x86_64;
241
242 MCAsmInfo *MAI;
243 if (TheTriple.isOSBinFormatMachO()) {
244 if (is64Bit)
245 MAI = new X86_64MCAsmInfoDarwin(TheTriple);
246 else
247 MAI = new X86MCAsmInfoDarwin(TheTriple);
248 } else if (TheTriple.isOSBinFormatELF()) {
249 // Force the use of an ELF container.
250 MAI = new X86ELFMCAsmInfo(TheTriple);
251 } else if (TheTriple.isWindowsMSVCEnvironment() ||
252 TheTriple.isWindowsCoreCLREnvironment()) {
253 MAI = new X86MCAsmInfoMicrosoft(TheTriple);
254 } else if (TheTriple.isOSCygMing() ||
255 TheTriple.isWindowsItaniumEnvironment()) {
256 MAI = new X86MCAsmInfoGNUCOFF(TheTriple);
257 } else {
258 // The default is ELF.
259 MAI = new X86ELFMCAsmInfo(TheTriple);
260 }
261
262 // Initialize initial frame state.
263 // Calculate amount of bytes used for return address storing
264 int stackGrowth = is64Bit ? -8 : -4;
265
266 // Initial state of the frame pointer is esp+stackGrowth.
267 unsigned StackPtr = is64Bit ? X86::RSP : X86::ESP;
268 MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(
269 nullptr, MRI.getDwarfRegNum(StackPtr, true), -stackGrowth);
270 MAI->addInitialFrameState(Inst);
271
272 // Add return address to move list
273 unsigned InstPtr = is64Bit ? X86::RIP : X86::EIP;
274 MCCFIInstruction Inst2 = MCCFIInstruction::createOffset(
275 nullptr, MRI.getDwarfRegNum(InstPtr, true), stackGrowth);
276 MAI->addInitialFrameState(Inst2);
277
278 return MAI;
279 }
280
createX86MCInstPrinter(const Triple & T,unsigned SyntaxVariant,const MCAsmInfo & MAI,const MCInstrInfo & MII,const MCRegisterInfo & MRI)281 static MCInstPrinter *createX86MCInstPrinter(const Triple &T,
282 unsigned SyntaxVariant,
283 const MCAsmInfo &MAI,
284 const MCInstrInfo &MII,
285 const MCRegisterInfo &MRI) {
286 if (SyntaxVariant == 0)
287 return new X86ATTInstPrinter(MAI, MII, MRI);
288 if (SyntaxVariant == 1)
289 return new X86IntelInstPrinter(MAI, MII, MRI);
290 return nullptr;
291 }
292
createX86MCRelocationInfo(const Triple & TheTriple,MCContext & Ctx)293 static MCRelocationInfo *createX86MCRelocationInfo(const Triple &TheTriple,
294 MCContext &Ctx) {
295 // Default to the stock relocation info.
296 return llvm::createMCRelocationInfo(TheTriple, Ctx);
297 }
298
299 namespace llvm {
300 namespace X86_MC {
301
302 class X86MCInstrAnalysis : public MCInstrAnalysis {
303 X86MCInstrAnalysis(const X86MCInstrAnalysis &) = delete;
304 X86MCInstrAnalysis &operator=(const X86MCInstrAnalysis &) = delete;
305 virtual ~X86MCInstrAnalysis() = default;
306
307 public:
X86MCInstrAnalysis(const MCInstrInfo * MCII)308 X86MCInstrAnalysis(const MCInstrInfo *MCII) : MCInstrAnalysis(MCII) {}
309
310 bool isDependencyBreaking(const MCSubtargetInfo &STI,
311 const MCInst &Inst) const override;
312 bool clearsSuperRegisters(const MCRegisterInfo &MRI, const MCInst &Inst,
313 APInt &Mask) const override;
314 };
315
isDependencyBreaking(const MCSubtargetInfo & STI,const MCInst & Inst) const316 bool X86MCInstrAnalysis::isDependencyBreaking(const MCSubtargetInfo &STI,
317 const MCInst &Inst) const {
318 if (STI.getCPU() == "btver2") {
319 // Reference: Agner Fog's microarchitecture.pdf - Section 20 "AMD Bobcat and
320 // Jaguar pipeline", subsection 8 "Dependency-breaking instructions".
321 switch (Inst.getOpcode()) {
322 default:
323 return false;
324 case X86::SUB32rr:
325 case X86::SUB64rr:
326 case X86::SBB32rr:
327 case X86::SBB64rr:
328 case X86::XOR32rr:
329 case X86::XOR64rr:
330 case X86::XORPSrr:
331 case X86::XORPDrr:
332 case X86::VXORPSrr:
333 case X86::VXORPDrr:
334 case X86::ANDNPSrr:
335 case X86::VANDNPSrr:
336 case X86::ANDNPDrr:
337 case X86::VANDNPDrr:
338 case X86::PXORrr:
339 case X86::VPXORrr:
340 case X86::PANDNrr:
341 case X86::VPANDNrr:
342 case X86::PSUBBrr:
343 case X86::PSUBWrr:
344 case X86::PSUBDrr:
345 case X86::PSUBQrr:
346 case X86::VPSUBBrr:
347 case X86::VPSUBWrr:
348 case X86::VPSUBDrr:
349 case X86::VPSUBQrr:
350 case X86::PCMPEQBrr:
351 case X86::PCMPEQWrr:
352 case X86::PCMPEQDrr:
353 case X86::PCMPEQQrr:
354 case X86::VPCMPEQBrr:
355 case X86::VPCMPEQWrr:
356 case X86::VPCMPEQDrr:
357 case X86::VPCMPEQQrr:
358 case X86::PCMPGTBrr:
359 case X86::PCMPGTWrr:
360 case X86::PCMPGTDrr:
361 case X86::PCMPGTQrr:
362 case X86::VPCMPGTBrr:
363 case X86::VPCMPGTWrr:
364 case X86::VPCMPGTDrr:
365 case X86::VPCMPGTQrr:
366 case X86::MMX_PXORirr:
367 case X86::MMX_PANDNirr:
368 case X86::MMX_PSUBBirr:
369 case X86::MMX_PSUBDirr:
370 case X86::MMX_PSUBQirr:
371 case X86::MMX_PSUBWirr:
372 case X86::MMX_PCMPGTBirr:
373 case X86::MMX_PCMPGTDirr:
374 case X86::MMX_PCMPGTWirr:
375 case X86::MMX_PCMPEQBirr:
376 case X86::MMX_PCMPEQDirr:
377 case X86::MMX_PCMPEQWirr:
378 return Inst.getOperand(1).getReg() == Inst.getOperand(2).getReg();
379 case X86::CMP32rr:
380 case X86::CMP64rr:
381 return Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg();
382 }
383 }
384
385 return false;
386 }
387
clearsSuperRegisters(const MCRegisterInfo & MRI,const MCInst & Inst,APInt & Mask) const388 bool X86MCInstrAnalysis::clearsSuperRegisters(const MCRegisterInfo &MRI,
389 const MCInst &Inst,
390 APInt &Mask) const {
391 const MCInstrDesc &Desc = Info->get(Inst.getOpcode());
392 unsigned NumDefs = Desc.getNumDefs();
393 unsigned NumImplicitDefs = Desc.getNumImplicitDefs();
394 assert(Mask.getBitWidth() == NumDefs + NumImplicitDefs &&
395 "Unexpected number of bits in the mask!");
396
397 bool HasVEX = (Desc.TSFlags & X86II::EncodingMask) == X86II::VEX;
398 bool HasEVEX = (Desc.TSFlags & X86II::EncodingMask) == X86II::EVEX;
399 bool HasXOP = (Desc.TSFlags & X86II::EncodingMask) == X86II::XOP;
400
401 const MCRegisterClass &GR32RC = MRI.getRegClass(X86::GR32RegClassID);
402 const MCRegisterClass &VR128XRC = MRI.getRegClass(X86::VR128XRegClassID);
403 const MCRegisterClass &VR256XRC = MRI.getRegClass(X86::VR256XRegClassID);
404
405 auto ClearsSuperReg = [=](unsigned RegID) {
406 // On X86-64, a general purpose integer register is viewed as a 64-bit
407 // register internal to the processor.
408 // An update to the lower 32 bits of a 64 bit integer register is
409 // architecturally defined to zero extend the upper 32 bits.
410 if (GR32RC.contains(RegID))
411 return true;
412
413 // Early exit if this instruction has no vex/evex/xop prefix.
414 if (!HasEVEX && !HasVEX && !HasXOP)
415 return false;
416
417 // All VEX and EVEX encoded instructions are defined to zero the high bits
418 // of the destination register up to VLMAX (i.e. the maximum vector register
419 // width pertaining to the instruction).
420 // We assume the same behavior for XOP instructions too.
421 return VR128XRC.contains(RegID) || VR256XRC.contains(RegID);
422 };
423
424 Mask.clearAllBits();
425 for (unsigned I = 0, E = NumDefs; I < E; ++I) {
426 const MCOperand &Op = Inst.getOperand(I);
427 if (ClearsSuperReg(Op.getReg()))
428 Mask.setBit(I);
429 }
430
431 for (unsigned I = 0, E = NumImplicitDefs; I < E; ++I) {
432 const MCPhysReg Reg = Desc.getImplicitDefs()[I];
433 if (ClearsSuperReg(Reg))
434 Mask.setBit(NumDefs + I);
435 }
436
437 return Mask.getBoolValue();
438 }
439
440 } // end of namespace X86_MC
441
442 } // end of namespace llvm
443
createX86MCInstrAnalysis(const MCInstrInfo * Info)444 static MCInstrAnalysis *createX86MCInstrAnalysis(const MCInstrInfo *Info) {
445 return new X86_MC::X86MCInstrAnalysis(Info);
446 }
447
448 // Force static initialization.
LLVMInitializeX86TargetMC()449 extern "C" void LLVMInitializeX86TargetMC() {
450 for (Target *T : {&getTheX86_32Target(), &getTheX86_64Target()}) {
451 // Register the MC asm info.
452 RegisterMCAsmInfoFn X(*T, createX86MCAsmInfo);
453
454 // Register the MC instruction info.
455 TargetRegistry::RegisterMCInstrInfo(*T, createX86MCInstrInfo);
456
457 // Register the MC register info.
458 TargetRegistry::RegisterMCRegInfo(*T, createX86MCRegisterInfo);
459
460 // Register the MC subtarget info.
461 TargetRegistry::RegisterMCSubtargetInfo(*T,
462 X86_MC::createX86MCSubtargetInfo);
463
464 // Register the MC instruction analyzer.
465 TargetRegistry::RegisterMCInstrAnalysis(*T, createX86MCInstrAnalysis);
466
467 // Register the code emitter.
468 TargetRegistry::RegisterMCCodeEmitter(*T, createX86MCCodeEmitter);
469
470 // Register the obj target streamer.
471 TargetRegistry::RegisterObjectTargetStreamer(*T,
472 createX86ObjectTargetStreamer);
473
474 // Register the asm target streamer.
475 TargetRegistry::RegisterAsmTargetStreamer(*T, createX86AsmTargetStreamer);
476
477 TargetRegistry::RegisterCOFFStreamer(*T, createX86WinCOFFStreamer);
478
479 // Register the MCInstPrinter.
480 TargetRegistry::RegisterMCInstPrinter(*T, createX86MCInstPrinter);
481
482 // Register the MC relocation info.
483 TargetRegistry::RegisterMCRelocationInfo(*T, createX86MCRelocationInfo);
484 }
485
486 // Register the asm backend.
487 TargetRegistry::RegisterMCAsmBackend(getTheX86_32Target(),
488 createX86_32AsmBackend);
489 TargetRegistry::RegisterMCAsmBackend(getTheX86_64Target(),
490 createX86_64AsmBackend);
491 }
492
getX86SubSuperRegisterOrZero(unsigned Reg,unsigned Size,bool High)493 unsigned llvm::getX86SubSuperRegisterOrZero(unsigned Reg, unsigned Size,
494 bool High) {
495 switch (Size) {
496 default: return 0;
497 case 8:
498 if (High) {
499 switch (Reg) {
500 default: return getX86SubSuperRegisterOrZero(Reg, 64);
501 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
502 return X86::SI;
503 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
504 return X86::DI;
505 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
506 return X86::BP;
507 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
508 return X86::SP;
509 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
510 return X86::AH;
511 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
512 return X86::DH;
513 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
514 return X86::CH;
515 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
516 return X86::BH;
517 }
518 } else {
519 switch (Reg) {
520 default: return 0;
521 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
522 return X86::AL;
523 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
524 return X86::DL;
525 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
526 return X86::CL;
527 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
528 return X86::BL;
529 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
530 return X86::SIL;
531 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
532 return X86::DIL;
533 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
534 return X86::BPL;
535 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
536 return X86::SPL;
537 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
538 return X86::R8B;
539 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
540 return X86::R9B;
541 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
542 return X86::R10B;
543 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
544 return X86::R11B;
545 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
546 return X86::R12B;
547 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
548 return X86::R13B;
549 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
550 return X86::R14B;
551 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
552 return X86::R15B;
553 }
554 }
555 case 16:
556 switch (Reg) {
557 default: return 0;
558 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
559 return X86::AX;
560 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
561 return X86::DX;
562 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
563 return X86::CX;
564 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
565 return X86::BX;
566 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
567 return X86::SI;
568 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
569 return X86::DI;
570 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
571 return X86::BP;
572 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
573 return X86::SP;
574 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
575 return X86::R8W;
576 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
577 return X86::R9W;
578 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
579 return X86::R10W;
580 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
581 return X86::R11W;
582 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
583 return X86::R12W;
584 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
585 return X86::R13W;
586 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
587 return X86::R14W;
588 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
589 return X86::R15W;
590 }
591 case 32:
592 switch (Reg) {
593 default: return 0;
594 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
595 return X86::EAX;
596 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
597 return X86::EDX;
598 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
599 return X86::ECX;
600 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
601 return X86::EBX;
602 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
603 return X86::ESI;
604 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
605 return X86::EDI;
606 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
607 return X86::EBP;
608 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
609 return X86::ESP;
610 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
611 return X86::R8D;
612 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
613 return X86::R9D;
614 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
615 return X86::R10D;
616 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
617 return X86::R11D;
618 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
619 return X86::R12D;
620 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
621 return X86::R13D;
622 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
623 return X86::R14D;
624 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
625 return X86::R15D;
626 }
627 case 64:
628 switch (Reg) {
629 default: return 0;
630 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
631 return X86::RAX;
632 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
633 return X86::RDX;
634 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
635 return X86::RCX;
636 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
637 return X86::RBX;
638 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
639 return X86::RSI;
640 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
641 return X86::RDI;
642 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
643 return X86::RBP;
644 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
645 return X86::RSP;
646 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
647 return X86::R8;
648 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
649 return X86::R9;
650 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
651 return X86::R10;
652 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
653 return X86::R11;
654 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
655 return X86::R12;
656 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
657 return X86::R13;
658 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
659 return X86::R14;
660 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
661 return X86::R15;
662 }
663 }
664 }
665
getX86SubSuperRegister(unsigned Reg,unsigned Size,bool High)666 unsigned llvm::getX86SubSuperRegister(unsigned Reg, unsigned Size, bool High) {
667 unsigned Res = getX86SubSuperRegisterOrZero(Reg, Size, High);
668 assert(Res != 0 && "Unexpected register or VT");
669 return Res;
670 }
671
672
673