1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2|* *| 3|* Machine Code Emitter *| 4|* *| 5|* Automatically generated file, do not edit! *| 6|* *| 7\*===----------------------------------------------------------------------===*/ 8 9uint64_t ARMMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI, 10 SmallVectorImpl<MCFixup> &Fixups, 11 const MCSubtargetInfo &STI) const { 12 static const uint64_t InstBits[] = { 13 UINT64_C(0), 14 UINT64_C(0), 15 UINT64_C(0), 16 UINT64_C(0), 17 UINT64_C(0), 18 UINT64_C(0), 19 UINT64_C(0), 20 UINT64_C(0), 21 UINT64_C(0), 22 UINT64_C(0), 23 UINT64_C(0), 24 UINT64_C(0), 25 UINT64_C(0), 26 UINT64_C(0), 27 UINT64_C(0), 28 UINT64_C(0), 29 UINT64_C(0), 30 UINT64_C(0), 31 UINT64_C(0), 32 UINT64_C(0), 33 UINT64_C(0), 34 UINT64_C(0), 35 UINT64_C(0), 36 UINT64_C(0), 37 UINT64_C(0), 38 UINT64_C(0), 39 UINT64_C(0), 40 UINT64_C(0), 41 UINT64_C(0), 42 UINT64_C(0), 43 UINT64_C(0), 44 UINT64_C(0), 45 UINT64_C(0), 46 UINT64_C(0), 47 UINT64_C(0), 48 UINT64_C(0), 49 UINT64_C(0), 50 UINT64_C(0), 51 UINT64_C(0), 52 UINT64_C(0), 53 UINT64_C(0), 54 UINT64_C(0), 55 UINT64_C(0), 56 UINT64_C(0), 57 UINT64_C(0), 58 UINT64_C(0), 59 UINT64_C(0), 60 UINT64_C(0), 61 UINT64_C(0), 62 UINT64_C(0), 63 UINT64_C(0), 64 UINT64_C(0), 65 UINT64_C(0), 66 UINT64_C(0), 67 UINT64_C(0), 68 UINT64_C(0), 69 UINT64_C(0), 70 UINT64_C(0), 71 UINT64_C(0), 72 UINT64_C(0), 73 UINT64_C(0), 74 UINT64_C(0), 75 UINT64_C(0), 76 UINT64_C(0), 77 UINT64_C(0), 78 UINT64_C(0), 79 UINT64_C(0), 80 UINT64_C(0), 81 UINT64_C(0), 82 UINT64_C(0), 83 UINT64_C(0), 84 UINT64_C(0), 85 UINT64_C(0), 86 UINT64_C(0), 87 UINT64_C(0), 88 UINT64_C(0), 89 UINT64_C(0), 90 UINT64_C(0), 91 UINT64_C(0), 92 UINT64_C(0), 93 UINT64_C(0), 94 UINT64_C(0), 95 UINT64_C(0), 96 UINT64_C(0), 97 UINT64_C(0), 98 UINT64_C(0), 99 UINT64_C(0), 100 UINT64_C(0), 101 UINT64_C(0), 102 UINT64_C(0), 103 UINT64_C(0), 104 UINT64_C(0), 105 UINT64_C(0), 106 UINT64_C(0), 107 UINT64_C(0), 108 UINT64_C(0), 109 UINT64_C(0), 110 UINT64_C(0), 111 UINT64_C(0), 112 UINT64_C(0), 113 UINT64_C(0), 114 UINT64_C(0), 115 UINT64_C(0), 116 UINT64_C(0), 117 UINT64_C(0), 118 UINT64_C(0), 119 UINT64_C(0), 120 UINT64_C(0), 121 UINT64_C(0), 122 UINT64_C(0), 123 UINT64_C(0), 124 UINT64_C(0), 125 UINT64_C(0), 126 UINT64_C(0), 127 UINT64_C(0), 128 UINT64_C(0), 129 UINT64_C(0), 130 UINT64_C(0), 131 UINT64_C(0), 132 UINT64_C(0), 133 UINT64_C(0), 134 UINT64_C(0), 135 UINT64_C(0), 136 UINT64_C(0), 137 UINT64_C(0), 138 UINT64_C(0), 139 UINT64_C(0), 140 UINT64_C(0), 141 UINT64_C(0), 142 UINT64_C(0), 143 UINT64_C(0), 144 UINT64_C(0), 145 UINT64_C(0), 146 UINT64_C(0), 147 UINT64_C(0), 148 UINT64_C(0), 149 UINT64_C(0), 150 UINT64_C(0), 151 UINT64_C(0), 152 UINT64_C(0), 153 UINT64_C(0), 154 UINT64_C(0), 155 UINT64_C(0), 156 UINT64_C(0), 157 UINT64_C(0), 158 UINT64_C(0), 159 UINT64_C(0), 160 UINT64_C(0), 161 UINT64_C(0), 162 UINT64_C(0), 163 UINT64_C(0), 164 UINT64_C(0), 165 UINT64_C(0), 166 UINT64_C(0), 167 UINT64_C(0), 168 UINT64_C(0), 169 UINT64_C(0), 170 UINT64_C(0), 171 UINT64_C(0), 172 UINT64_C(0), 173 UINT64_C(0), 174 UINT64_C(0), 175 UINT64_C(0), 176 UINT64_C(0), 177 UINT64_C(0), 178 UINT64_C(0), 179 UINT64_C(0), 180 UINT64_C(0), 181 UINT64_C(0), 182 UINT64_C(0), 183 UINT64_C(0), 184 UINT64_C(0), 185 UINT64_C(0), 186 UINT64_C(0), 187 UINT64_C(0), 188 UINT64_C(0), 189 UINT64_C(0), 190 UINT64_C(0), 191 UINT64_C(0), 192 UINT64_C(0), 193 UINT64_C(0), 194 UINT64_C(0), 195 UINT64_C(0), 196 UINT64_C(0), 197 UINT64_C(0), 198 UINT64_C(0), 199 UINT64_C(0), 200 UINT64_C(0), 201 UINT64_C(0), 202 UINT64_C(0), 203 UINT64_C(0), 204 UINT64_C(0), 205 UINT64_C(0), 206 UINT64_C(0), 207 UINT64_C(0), 208 UINT64_C(0), 209 UINT64_C(0), 210 UINT64_C(0), 211 UINT64_C(0), 212 UINT64_C(0), 213 UINT64_C(0), 214 UINT64_C(0), 215 UINT64_C(0), 216 UINT64_C(0), 217 UINT64_C(0), 218 UINT64_C(0), 219 UINT64_C(0), 220 UINT64_C(0), 221 UINT64_C(0), 222 UINT64_C(0), 223 UINT64_C(0), 224 UINT64_C(0), 225 UINT64_C(0), 226 UINT64_C(0), 227 UINT64_C(0), 228 UINT64_C(0), 229 UINT64_C(0), 230 UINT64_C(0), 231 UINT64_C(0), 232 UINT64_C(0), 233 UINT64_C(0), 234 UINT64_C(0), 235 UINT64_C(0), 236 UINT64_C(0), 237 UINT64_C(0), 238 UINT64_C(0), 239 UINT64_C(0), 240 UINT64_C(0), 241 UINT64_C(0), 242 UINT64_C(0), 243 UINT64_C(0), 244 UINT64_C(0), 245 UINT64_C(0), 246 UINT64_C(0), 247 UINT64_C(0), 248 UINT64_C(0), 249 UINT64_C(0), 250 UINT64_C(0), 251 UINT64_C(0), 252 UINT64_C(0), 253 UINT64_C(0), 254 UINT64_C(0), 255 UINT64_C(0), 256 UINT64_C(0), 257 UINT64_C(0), 258 UINT64_C(0), 259 UINT64_C(0), 260 UINT64_C(0), 261 UINT64_C(0), 262 UINT64_C(0), 263 UINT64_C(0), 264 UINT64_C(0), 265 UINT64_C(0), 266 UINT64_C(0), 267 UINT64_C(0), 268 UINT64_C(0), 269 UINT64_C(0), 270 UINT64_C(0), 271 UINT64_C(0), 272 UINT64_C(0), 273 UINT64_C(0), 274 UINT64_C(0), 275 UINT64_C(0), 276 UINT64_C(0), 277 UINT64_C(0), 278 UINT64_C(0), 279 UINT64_C(0), 280 UINT64_C(0), 281 UINT64_C(0), 282 UINT64_C(0), 283 UINT64_C(0), 284 UINT64_C(0), 285 UINT64_C(0), 286 UINT64_C(0), 287 UINT64_C(0), 288 UINT64_C(0), 289 UINT64_C(0), 290 UINT64_C(0), 291 UINT64_C(0), 292 UINT64_C(0), 293 UINT64_C(0), 294 UINT64_C(0), 295 UINT64_C(0), 296 UINT64_C(0), 297 UINT64_C(0), 298 UINT64_C(0), 299 UINT64_C(0), 300 UINT64_C(0), 301 UINT64_C(0), 302 UINT64_C(0), 303 UINT64_C(0), 304 UINT64_C(0), 305 UINT64_C(0), 306 UINT64_C(0), 307 UINT64_C(0), 308 UINT64_C(0), 309 UINT64_C(0), 310 UINT64_C(0), 311 UINT64_C(0), 312 UINT64_C(0), 313 UINT64_C(0), 314 UINT64_C(0), 315 UINT64_C(0), 316 UINT64_C(0), 317 UINT64_C(0), 318 UINT64_C(0), 319 UINT64_C(0), 320 UINT64_C(0), 321 UINT64_C(0), 322 UINT64_C(0), 323 UINT64_C(0), 324 UINT64_C(0), 325 UINT64_C(0), 326 UINT64_C(0), 327 UINT64_C(0), 328 UINT64_C(0), 329 UINT64_C(0), 330 UINT64_C(0), 331 UINT64_C(0), 332 UINT64_C(0), 333 UINT64_C(0), 334 UINT64_C(0), 335 UINT64_C(0), 336 UINT64_C(0), 337 UINT64_C(0), 338 UINT64_C(0), 339 UINT64_C(0), 340 UINT64_C(0), 341 UINT64_C(0), 342 UINT64_C(0), 343 UINT64_C(0), 344 UINT64_C(0), 345 UINT64_C(0), 346 UINT64_C(0), 347 UINT64_C(0), 348 UINT64_C(0), 349 UINT64_C(0), 350 UINT64_C(0), 351 UINT64_C(0), 352 UINT64_C(0), 353 UINT64_C(0), 354 UINT64_C(0), 355 UINT64_C(0), 356 UINT64_C(0), 357 UINT64_C(0), 358 UINT64_C(0), 359 UINT64_C(0), 360 UINT64_C(0), 361 UINT64_C(0), 362 UINT64_C(0), 363 UINT64_C(0), 364 UINT64_C(0), 365 UINT64_C(0), 366 UINT64_C(0), 367 UINT64_C(0), 368 UINT64_C(0), 369 UINT64_C(0), 370 UINT64_C(0), 371 UINT64_C(0), 372 UINT64_C(0), 373 UINT64_C(0), 374 UINT64_C(0), 375 UINT64_C(0), 376 UINT64_C(0), 377 UINT64_C(0), 378 UINT64_C(0), 379 UINT64_C(0), 380 UINT64_C(0), 381 UINT64_C(0), 382 UINT64_C(0), 383 UINT64_C(0), 384 UINT64_C(0), 385 UINT64_C(0), 386 UINT64_C(0), 387 UINT64_C(0), 388 UINT64_C(0), 389 UINT64_C(0), 390 UINT64_C(0), 391 UINT64_C(0), 392 UINT64_C(0), 393 UINT64_C(0), 394 UINT64_C(0), 395 UINT64_C(0), 396 UINT64_C(0), 397 UINT64_C(0), 398 UINT64_C(0), 399 UINT64_C(0), 400 UINT64_C(0), 401 UINT64_C(0), 402 UINT64_C(0), 403 UINT64_C(0), 404 UINT64_C(0), 405 UINT64_C(0), 406 UINT64_C(0), 407 UINT64_C(0), 408 UINT64_C(0), 409 UINT64_C(0), 410 UINT64_C(0), 411 UINT64_C(0), 412 UINT64_C(0), 413 UINT64_C(0), 414 UINT64_C(0), 415 UINT64_C(0), 416 UINT64_C(0), 417 UINT64_C(0), 418 UINT64_C(0), 419 UINT64_C(0), 420 UINT64_C(0), 421 UINT64_C(0), 422 UINT64_C(0), 423 UINT64_C(0), 424 UINT64_C(0), 425 UINT64_C(0), 426 UINT64_C(0), 427 UINT64_C(0), 428 UINT64_C(0), 429 UINT64_C(0), 430 UINT64_C(0), 431 UINT64_C(0), 432 UINT64_C(0), 433 UINT64_C(0), 434 UINT64_C(0), 435 UINT64_C(0), 436 UINT64_C(0), 437 UINT64_C(0), 438 UINT64_C(0), 439 UINT64_C(0), 440 UINT64_C(0), 441 UINT64_C(0), 442 UINT64_C(0), 443 UINT64_C(0), 444 UINT64_C(0), 445 UINT64_C(0), 446 UINT64_C(0), 447 UINT64_C(0), 448 UINT64_C(0), 449 UINT64_C(0), 450 UINT64_C(0), 451 UINT64_C(0), 452 UINT64_C(0), 453 UINT64_C(0), 454 UINT64_C(0), 455 UINT64_C(0), 456 UINT64_C(0), 457 UINT64_C(0), 458 UINT64_C(0), 459 UINT64_C(0), 460 UINT64_C(0), 461 UINT64_C(0), 462 UINT64_C(0), 463 UINT64_C(0), 464 UINT64_C(0), 465 UINT64_C(0), 466 UINT64_C(0), 467 UINT64_C(0), 468 UINT64_C(0), 469 UINT64_C(0), 470 UINT64_C(0), 471 UINT64_C(0), 472 UINT64_C(0), 473 UINT64_C(0), 474 UINT64_C(0), 475 UINT64_C(0), 476 UINT64_C(0), 477 UINT64_C(0), 478 UINT64_C(0), 479 UINT64_C(0), 480 UINT64_C(0), 481 UINT64_C(0), 482 UINT64_C(0), 483 UINT64_C(0), 484 UINT64_C(0), 485 UINT64_C(0), 486 UINT64_C(0), 487 UINT64_C(0), 488 UINT64_C(0), 489 UINT64_C(0), 490 UINT64_C(0), 491 UINT64_C(0), 492 UINT64_C(0), 493 UINT64_C(0), 494 UINT64_C(0), 495 UINT64_C(0), 496 UINT64_C(0), 497 UINT64_C(0), 498 UINT64_C(0), 499 UINT64_C(0), 500 UINT64_C(0), 501 UINT64_C(0), 502 UINT64_C(0), 503 UINT64_C(0), 504 UINT64_C(0), 505 UINT64_C(0), 506 UINT64_C(0), 507 UINT64_C(0), 508 UINT64_C(0), 509 UINT64_C(0), 510 UINT64_C(0), 511 UINT64_C(0), 512 UINT64_C(0), 513 UINT64_C(0), 514 UINT64_C(0), 515 UINT64_C(0), 516 UINT64_C(0), 517 UINT64_C(0), 518 UINT64_C(0), 519 UINT64_C(0), 520 UINT64_C(0), 521 UINT64_C(0), 522 UINT64_C(0), 523 UINT64_C(0), 524 UINT64_C(0), 525 UINT64_C(0), 526 UINT64_C(0), 527 UINT64_C(0), 528 UINT64_C(0), 529 UINT64_C(0), 530 UINT64_C(0), 531 UINT64_C(0), 532 UINT64_C(0), 533 UINT64_C(0), 534 UINT64_C(0), 535 UINT64_C(0), 536 UINT64_C(0), 537 UINT64_C(0), 538 UINT64_C(0), 539 UINT64_C(0), 540 UINT64_C(0), 541 UINT64_C(0), 542 UINT64_C(44040192), // ADCri 543 UINT64_C(10485760), // ADCrr 544 UINT64_C(10485760), // ADCrsi 545 UINT64_C(10485776), // ADCrsr 546 UINT64_C(41943040), // ADDri 547 UINT64_C(8388608), // ADDrr 548 UINT64_C(8388608), // ADDrsi 549 UINT64_C(8388624), // ADDrsr 550 UINT64_C(34537472), // ADR 551 UINT64_C(4088398656), // AESD 552 UINT64_C(4088398592), // AESE 553 UINT64_C(4088398784), // AESIMC 554 UINT64_C(4088398720), // AESMC 555 UINT64_C(33554432), // ANDri 556 UINT64_C(0), // ANDrr 557 UINT64_C(0), // ANDrsi 558 UINT64_C(16), // ANDrsr 559 UINT64_C(130023455), // BFC 560 UINT64_C(130023440), // BFI 561 UINT64_C(62914560), // BICri 562 UINT64_C(29360128), // BICrr 563 UINT64_C(29360128), // BICrsi 564 UINT64_C(29360144), // BICrsr 565 UINT64_C(3776970864), // BKPT 566 UINT64_C(3942645760), // BL 567 UINT64_C(3778019120), // BLX 568 UINT64_C(19922736), // BLX_pred 569 UINT64_C(4194304000), // BLXi 570 UINT64_C(184549376), // BL_pred 571 UINT64_C(3778019088), // BX 572 UINT64_C(19922720), // BXJ 573 UINT64_C(19922718), // BX_RET 574 UINT64_C(19922704), // BX_pred 575 UINT64_C(167772160), // Bcc 576 UINT64_C(234881024), // CDP 577 UINT64_C(4261412864), // CDP2 578 UINT64_C(4118802463), // CLREX 579 UINT64_C(24055568), // CLZ 580 UINT64_C(57671680), // CMNri 581 UINT64_C(24117248), // CMNzrr 582 UINT64_C(24117248), // CMNzrsi 583 UINT64_C(24117264), // CMNzrsr 584 UINT64_C(55574528), // CMPri 585 UINT64_C(22020096), // CMPrr 586 UINT64_C(22020096), // CMPrsi 587 UINT64_C(22020112), // CMPrsr 588 UINT64_C(4043440128), // CPS1p 589 UINT64_C(4043309056), // CPS2p 590 UINT64_C(4043440128), // CPS3p 591 UINT64_C(3774873664), // CRC32B 592 UINT64_C(3774874176), // CRC32CB 593 UINT64_C(3776971328), // CRC32CH 594 UINT64_C(3779068480), // CRC32CW 595 UINT64_C(3776970816), // CRC32H 596 UINT64_C(3779067968), // CRC32W 597 UINT64_C(52490480), // DBG 598 UINT64_C(4118802512), // DMB 599 UINT64_C(4118802496), // DSB 600 UINT64_C(35651584), // EORri 601 UINT64_C(2097152), // EORrr 602 UINT64_C(2097152), // EORrsi 603 UINT64_C(2097168), // EORrsr 604 UINT64_C(23068782), // ERET 605 UINT64_C(246418176), // FCONSTD 606 UINT64_C(246417664), // FCONSTH 607 UINT64_C(246417920), // FCONSTS 608 UINT64_C(221252353), // FLDMXDB_UPD 609 UINT64_C(210766593), // FLDMXIA 610 UINT64_C(212863745), // FLDMXIA_UPD 611 UINT64_C(250739216), // FMSTAT 612 UINT64_C(220203777), // FSTMXDB_UPD 613 UINT64_C(209718017), // FSTMXIA 614 UINT64_C(211815169), // FSTMXIA_UPD 615 UINT64_C(52490240), // HINT 616 UINT64_C(3774873712), // HLT 617 UINT64_C(3779068016), // HVC 618 UINT64_C(4118802528), // ISB 619 UINT64_C(26217631), // LDA 620 UINT64_C(30411935), // LDAB 621 UINT64_C(26218143), // LDAEX 622 UINT64_C(30412447), // LDAEXB 623 UINT64_C(28315295), // LDAEXD 624 UINT64_C(32509599), // LDAEXH 625 UINT64_C(32509087), // LDAH 626 UINT64_C(4249878528), // LDC2L_OFFSET 627 UINT64_C(4241489920), // LDC2L_OPTION 628 UINT64_C(4235198464), // LDC2L_POST 629 UINT64_C(4251975680), // LDC2L_PRE 630 UINT64_C(4245684224), // LDC2_OFFSET 631 UINT64_C(4237295616), // LDC2_OPTION 632 UINT64_C(4231004160), // LDC2_POST 633 UINT64_C(4247781376), // LDC2_PRE 634 UINT64_C(223346688), // LDCL_OFFSET 635 UINT64_C(214958080), // LDCL_OPTION 636 UINT64_C(208666624), // LDCL_POST 637 UINT64_C(225443840), // LDCL_PRE 638 UINT64_C(219152384), // LDC_OFFSET 639 UINT64_C(210763776), // LDC_OPTION 640 UINT64_C(204472320), // LDC_POST 641 UINT64_C(221249536), // LDC_PRE 642 UINT64_C(135266304), // LDMDA 643 UINT64_C(137363456), // LDMDA_UPD 644 UINT64_C(152043520), // LDMDB 645 UINT64_C(154140672), // LDMDB_UPD 646 UINT64_C(143654912), // LDMIA 647 UINT64_C(145752064), // LDMIA_UPD 648 UINT64_C(160432128), // LDMIB 649 UINT64_C(162529280), // LDMIB_UPD 650 UINT64_C(74448896), // LDRBT_POST_IMM 651 UINT64_C(108003328), // LDRBT_POST_REG 652 UINT64_C(72351744), // LDRB_POST_IMM 653 UINT64_C(105906176), // LDRB_POST_REG 654 UINT64_C(91226112), // LDRB_PRE_IMM 655 UINT64_C(124780544), // LDRB_PRE_REG 656 UINT64_C(89128960), // LDRBi12 657 UINT64_C(122683392), // LDRBrs 658 UINT64_C(16777424), // LDRD 659 UINT64_C(208), // LDRD_POST 660 UINT64_C(18874576), // LDRD_PRE 661 UINT64_C(26218399), // LDREX 662 UINT64_C(30412703), // LDREXB 663 UINT64_C(28315551), // LDREXD 664 UINT64_C(32509855), // LDREXH 665 UINT64_C(17825968), // LDRH 666 UINT64_C(7340208), // LDRHTi 667 UINT64_C(3145904), // LDRHTr 668 UINT64_C(1048752), // LDRH_POST 669 UINT64_C(19923120), // LDRH_PRE 670 UINT64_C(17826000), // LDRSB 671 UINT64_C(7340240), // LDRSBTi 672 UINT64_C(3145936), // LDRSBTr 673 UINT64_C(1048784), // LDRSB_POST 674 UINT64_C(19923152), // LDRSB_PRE 675 UINT64_C(17826032), // LDRSH 676 UINT64_C(7340272), // LDRSHTi 677 UINT64_C(3145968), // LDRSHTr 678 UINT64_C(1048816), // LDRSH_POST 679 UINT64_C(19923184), // LDRSH_PRE 680 UINT64_C(70254592), // LDRT_POST_IMM 681 UINT64_C(103809024), // LDRT_POST_REG 682 UINT64_C(68157440), // LDR_POST_IMM 683 UINT64_C(101711872), // LDR_POST_REG 684 UINT64_C(87031808), // LDR_PRE_IMM 685 UINT64_C(120586240), // LDR_PRE_REG 686 UINT64_C(85917696), // LDRcp 687 UINT64_C(84934656), // LDRi12 688 UINT64_C(118489088), // LDRrs 689 UINT64_C(234881040), // MCR 690 UINT64_C(4261412880), // MCR2 691 UINT64_C(205520896), // MCRR 692 UINT64_C(4232052736), // MCRR2 693 UINT64_C(2097296), // MLA 694 UINT64_C(6291600), // MLS 695 UINT64_C(27324430), // MOVPCLR 696 UINT64_C(54525952), // MOVTi16 697 UINT64_C(60817408), // MOVi 698 UINT64_C(50331648), // MOVi16 699 UINT64_C(27262976), // MOVr 700 UINT64_C(27262976), // MOVr_TC 701 UINT64_C(27262976), // MOVsi 702 UINT64_C(27262992), // MOVsr 703 UINT64_C(235929616), // MRC 704 UINT64_C(4262461456), // MRC2 705 UINT64_C(206569472), // MRRC 706 UINT64_C(4233101312), // MRRC2 707 UINT64_C(17760256), // MRS 708 UINT64_C(16777728), // MRSbanked 709 UINT64_C(21954560), // MRSsys 710 UINT64_C(18935808), // MSR 711 UINT64_C(18936320), // MSRbanked 712 UINT64_C(52490240), // MSRi 713 UINT64_C(144), // MUL 714 UINT64_C(65011712), // MVNi 715 UINT64_C(31457280), // MVNr 716 UINT64_C(31457280), // MVNsi 717 UINT64_C(31457296), // MVNsr 718 UINT64_C(58720256), // ORRri 719 UINT64_C(25165824), // ORRrr 720 UINT64_C(25165824), // ORRrsi 721 UINT64_C(25165840), // ORRrsr 722 UINT64_C(109051920), // PKHBT 723 UINT64_C(109051984), // PKHTB 724 UINT64_C(4111527936), // PLDWi12 725 UINT64_C(4145082368), // PLDWrs 726 UINT64_C(4115722240), // PLDi12 727 UINT64_C(4149276672), // PLDrs 728 UINT64_C(4098945024), // PLIi12 729 UINT64_C(4132499456), // PLIrs 730 UINT64_C(16777296), // QADD 731 UINT64_C(102764304), // QADD16 732 UINT64_C(102764432), // QADD8 733 UINT64_C(102764336), // QASX 734 UINT64_C(20971600), // QDADD 735 UINT64_C(23068752), // QDSUB 736 UINT64_C(102764368), // QSAX 737 UINT64_C(18874448), // QSUB 738 UINT64_C(102764400), // QSUB16 739 UINT64_C(102764528), // QSUB8 740 UINT64_C(117378864), // RBIT 741 UINT64_C(113184560), // REV 742 UINT64_C(113184688), // REV16 743 UINT64_C(117378992), // REVSH 744 UINT64_C(4161800704), // RFEDA 745 UINT64_C(4163897856), // RFEDA_UPD 746 UINT64_C(4178577920), // RFEDB 747 UINT64_C(4180675072), // RFEDB_UPD 748 UINT64_C(4170189312), // RFEIA 749 UINT64_C(4172286464), // RFEIA_UPD 750 UINT64_C(4186966528), // RFEIB 751 UINT64_C(4189063680), // RFEIB_UPD 752 UINT64_C(39845888), // RSBri 753 UINT64_C(6291456), // RSBrr 754 UINT64_C(6291456), // RSBrsi 755 UINT64_C(6291472), // RSBrsr 756 UINT64_C(48234496), // RSCri 757 UINT64_C(14680064), // RSCrr 758 UINT64_C(14680064), // RSCrsi 759 UINT64_C(14680080), // RSCrsr 760 UINT64_C(101715728), // SADD16 761 UINT64_C(101715856), // SADD8 762 UINT64_C(101715760), // SASX 763 UINT64_C(46137344), // SBCri 764 UINT64_C(12582912), // SBCrr 765 UINT64_C(12582912), // SBCrsi 766 UINT64_C(12582928), // SBCrsr 767 UINT64_C(127926352), // SBFX 768 UINT64_C(118550544), // SDIV 769 UINT64_C(109055920), // SEL 770 UINT64_C(4043374592), // SETEND 771 UINT64_C(4044357632), // SETPAN 772 UINT64_C(4060089408), // SHA1C 773 UINT64_C(4088988352), // SHA1H 774 UINT64_C(4062186560), // SHA1M 775 UINT64_C(4061137984), // SHA1P 776 UINT64_C(4063235136), // SHA1SU0 777 UINT64_C(4089054080), // SHA1SU1 778 UINT64_C(4076866624), // SHA256H 779 UINT64_C(4077915200), // SHA256H2 780 UINT64_C(4089054144), // SHA256SU0 781 UINT64_C(4078963776), // SHA256SU1 782 UINT64_C(103812880), // SHADD16 783 UINT64_C(103813008), // SHADD8 784 UINT64_C(103812912), // SHASX 785 UINT64_C(103812944), // SHSAX 786 UINT64_C(103812976), // SHSUB16 787 UINT64_C(103813104), // SHSUB8 788 UINT64_C(23068784), // SMC 789 UINT64_C(16777344), // SMLABB 790 UINT64_C(16777408), // SMLABT 791 UINT64_C(117440528), // SMLAD 792 UINT64_C(117440560), // SMLADX 793 UINT64_C(14680208), // SMLAL 794 UINT64_C(20971648), // SMLALBB 795 UINT64_C(20971712), // SMLALBT 796 UINT64_C(121634832), // SMLALD 797 UINT64_C(121634864), // SMLALDX 798 UINT64_C(20971680), // SMLALTB 799 UINT64_C(20971744), // SMLALTT 800 UINT64_C(16777376), // SMLATB 801 UINT64_C(16777440), // SMLATT 802 UINT64_C(18874496), // SMLAWB 803 UINT64_C(18874560), // SMLAWT 804 UINT64_C(117440592), // SMLSD 805 UINT64_C(117440624), // SMLSDX 806 UINT64_C(121634896), // SMLSLD 807 UINT64_C(121634928), // SMLSLDX 808 UINT64_C(122683408), // SMMLA 809 UINT64_C(122683440), // SMMLAR 810 UINT64_C(122683600), // SMMLS 811 UINT64_C(122683632), // SMMLSR 812 UINT64_C(122744848), // SMMUL 813 UINT64_C(122744880), // SMMULR 814 UINT64_C(117501968), // SMUAD 815 UINT64_C(117502000), // SMUADX 816 UINT64_C(23068800), // SMULBB 817 UINT64_C(23068864), // SMULBT 818 UINT64_C(12583056), // SMULL 819 UINT64_C(23068832), // SMULTB 820 UINT64_C(23068896), // SMULTT 821 UINT64_C(18874528), // SMULWB 822 UINT64_C(18874592), // SMULWT 823 UINT64_C(117502032), // SMUSD 824 UINT64_C(117502064), // SMUSDX 825 UINT64_C(4165797120), // SRSDA 826 UINT64_C(4167894272), // SRSDA_UPD 827 UINT64_C(4182574336), // SRSDB 828 UINT64_C(4184671488), // SRSDB_UPD 829 UINT64_C(4174185728), // SRSIA 830 UINT64_C(4176282880), // SRSIA_UPD 831 UINT64_C(4190962944), // SRSIB 832 UINT64_C(4193060096), // SRSIB_UPD 833 UINT64_C(111149072), // SSAT 834 UINT64_C(111152944), // SSAT16 835 UINT64_C(101715792), // SSAX 836 UINT64_C(101715824), // SSUB16 837 UINT64_C(101715952), // SSUB8 838 UINT64_C(4248829952), // STC2L_OFFSET 839 UINT64_C(4240441344), // STC2L_OPTION 840 UINT64_C(4234149888), // STC2L_POST 841 UINT64_C(4250927104), // STC2L_PRE 842 UINT64_C(4244635648), // STC2_OFFSET 843 UINT64_C(4236247040), // STC2_OPTION 844 UINT64_C(4229955584), // STC2_POST 845 UINT64_C(4246732800), // STC2_PRE 846 UINT64_C(222298112), // STCL_OFFSET 847 UINT64_C(213909504), // STCL_OPTION 848 UINT64_C(207618048), // STCL_POST 849 UINT64_C(224395264), // STCL_PRE 850 UINT64_C(218103808), // STC_OFFSET 851 UINT64_C(209715200), // STC_OPTION 852 UINT64_C(203423744), // STC_POST 853 UINT64_C(220200960), // STC_PRE 854 UINT64_C(25230480), // STL 855 UINT64_C(29424784), // STLB 856 UINT64_C(25169552), // STLEX 857 UINT64_C(29363856), // STLEXB 858 UINT64_C(27266704), // STLEXD 859 UINT64_C(31461008), // STLEXH 860 UINT64_C(31521936), // STLH 861 UINT64_C(134217728), // STMDA 862 UINT64_C(136314880), // STMDA_UPD 863 UINT64_C(150994944), // STMDB 864 UINT64_C(153092096), // STMDB_UPD 865 UINT64_C(142606336), // STMIA 866 UINT64_C(144703488), // STMIA_UPD 867 UINT64_C(159383552), // STMIB 868 UINT64_C(161480704), // STMIB_UPD 869 UINT64_C(73400320), // STRBT_POST_IMM 870 UINT64_C(106954752), // STRBT_POST_REG 871 UINT64_C(71303168), // STRB_POST_IMM 872 UINT64_C(104857600), // STRB_POST_REG 873 UINT64_C(90177536), // STRB_PRE_IMM 874 UINT64_C(123731968), // STRB_PRE_REG 875 UINT64_C(88080384), // STRBi12 876 UINT64_C(121634816), // STRBrs 877 UINT64_C(16777456), // STRD 878 UINT64_C(240), // STRD_POST 879 UINT64_C(18874608), // STRD_PRE 880 UINT64_C(25169808), // STREX 881 UINT64_C(29364112), // STREXB 882 UINT64_C(27266960), // STREXD 883 UINT64_C(31461264), // STREXH 884 UINT64_C(16777392), // STRH 885 UINT64_C(6291632), // STRHTi 886 UINT64_C(2097328), // STRHTr 887 UINT64_C(176), // STRH_POST 888 UINT64_C(18874544), // STRH_PRE 889 UINT64_C(69206016), // STRT_POST_IMM 890 UINT64_C(102760448), // STRT_POST_REG 891 UINT64_C(67108864), // STR_POST_IMM 892 UINT64_C(100663296), // STR_POST_REG 893 UINT64_C(85983232), // STR_PRE_IMM 894 UINT64_C(119537664), // STR_PRE_REG 895 UINT64_C(83886080), // STRi12 896 UINT64_C(117440512), // STRrs 897 UINT64_C(37748736), // SUBri 898 UINT64_C(4194304), // SUBrr 899 UINT64_C(4194304), // SUBrsi 900 UINT64_C(4194320), // SUBrsr 901 UINT64_C(251658240), // SVC 902 UINT64_C(16777360), // SWP 903 UINT64_C(20971664), // SWPB 904 UINT64_C(111149168), // SXTAB 905 UINT64_C(109052016), // SXTAB16 906 UINT64_C(112197744), // SXTAH 907 UINT64_C(112132208), // SXTB 908 UINT64_C(110035056), // SXTB16 909 UINT64_C(113180784), // SXTH 910 UINT64_C(53477376), // TEQri 911 UINT64_C(19922944), // TEQrr 912 UINT64_C(19922944), // TEQrsi 913 UINT64_C(19922960), // TEQrsr 914 UINT64_C(3892305662), // TRAP 915 UINT64_C(3892240112), // TRAPNaCl 916 UINT64_C(3810586642), // TSB 917 UINT64_C(51380224), // TSTri 918 UINT64_C(17825792), // TSTrr 919 UINT64_C(17825792), // TSTrsi 920 UINT64_C(17825808), // TSTrsr 921 UINT64_C(105910032), // UADD16 922 UINT64_C(105910160), // UADD8 923 UINT64_C(105910064), // UASX 924 UINT64_C(132120656), // UBFX 925 UINT64_C(3891265776), // UDF 926 UINT64_C(120647696), // UDIV 927 UINT64_C(108007184), // UHADD16 928 UINT64_C(108007312), // UHADD8 929 UINT64_C(108007216), // UHASX 930 UINT64_C(108007248), // UHSAX 931 UINT64_C(108007280), // UHSUB16 932 UINT64_C(108007408), // UHSUB8 933 UINT64_C(4194448), // UMAAL 934 UINT64_C(10485904), // UMLAL 935 UINT64_C(8388752), // UMULL 936 UINT64_C(106958608), // UQADD16 937 UINT64_C(106958736), // UQADD8 938 UINT64_C(106958640), // UQASX 939 UINT64_C(106958672), // UQSAX 940 UINT64_C(106958704), // UQSUB16 941 UINT64_C(106958832), // UQSUB8 942 UINT64_C(125890576), // USAD8 943 UINT64_C(125829136), // USADA8 944 UINT64_C(115343376), // USAT 945 UINT64_C(115347248), // USAT16 946 UINT64_C(105910096), // USAX 947 UINT64_C(105910128), // USUB16 948 UINT64_C(105910256), // USUB8 949 UINT64_C(115343472), // UXTAB 950 UINT64_C(113246320), // UXTAB16 951 UINT64_C(116392048), // UXTAH 952 UINT64_C(116326512), // UXTB 953 UINT64_C(114229360), // UXTB16 954 UINT64_C(117375088), // UXTH 955 UINT64_C(4070573312), // VABALsv2i64 956 UINT64_C(4069524736), // VABALsv4i32 957 UINT64_C(4068476160), // VABALsv8i16 958 UINT64_C(4087350528), // VABALuv2i64 959 UINT64_C(4086301952), // VABALuv4i32 960 UINT64_C(4085253376), // VABALuv8i16 961 UINT64_C(4060088144), // VABAsv16i8 962 UINT64_C(4062185232), // VABAsv2i32 963 UINT64_C(4061136656), // VABAsv4i16 964 UINT64_C(4062185296), // VABAsv4i32 965 UINT64_C(4061136720), // VABAsv8i16 966 UINT64_C(4060088080), // VABAsv8i8 967 UINT64_C(4076865360), // VABAuv16i8 968 UINT64_C(4078962448), // VABAuv2i32 969 UINT64_C(4077913872), // VABAuv4i16 970 UINT64_C(4078962512), // VABAuv4i32 971 UINT64_C(4077913936), // VABAuv8i16 972 UINT64_C(4076865296), // VABAuv8i8 973 UINT64_C(4070573824), // VABDLsv2i64 974 UINT64_C(4069525248), // VABDLsv4i32 975 UINT64_C(4068476672), // VABDLsv8i16 976 UINT64_C(4087351040), // VABDLuv2i64 977 UINT64_C(4086302464), // VABDLuv4i32 978 UINT64_C(4085253888), // VABDLuv8i16 979 UINT64_C(4078963968), // VABDfd 980 UINT64_C(4078964032), // VABDfq 981 UINT64_C(4080012544), // VABDhd 982 UINT64_C(4080012608), // VABDhq 983 UINT64_C(4060088128), // VABDsv16i8 984 UINT64_C(4062185216), // VABDsv2i32 985 UINT64_C(4061136640), // VABDsv4i16 986 UINT64_C(4062185280), // VABDsv4i32 987 UINT64_C(4061136704), // VABDsv8i16 988 UINT64_C(4060088064), // VABDsv8i8 989 UINT64_C(4076865344), // VABDuv16i8 990 UINT64_C(4078962432), // VABDuv2i32 991 UINT64_C(4077913856), // VABDuv4i16 992 UINT64_C(4078962496), // VABDuv4i32 993 UINT64_C(4077913920), // VABDuv8i16 994 UINT64_C(4076865280), // VABDuv8i8 995 UINT64_C(246418368), // VABSD 996 UINT64_C(246417856), // VABSH 997 UINT64_C(246418112), // VABSS 998 UINT64_C(4088989440), // VABSfd 999 UINT64_C(4088989504), // VABSfq 1000 UINT64_C(4088727296), // VABShd 1001 UINT64_C(4088727360), // VABShq 1002 UINT64_C(4088464192), // VABSv16i8 1003 UINT64_C(4088988416), // VABSv2i32 1004 UINT64_C(4088726272), // VABSv4i16 1005 UINT64_C(4088988480), // VABSv4i32 1006 UINT64_C(4088726336), // VABSv8i16 1007 UINT64_C(4088464128), // VABSv8i8 1008 UINT64_C(4076867088), // VACGEfd 1009 UINT64_C(4076867152), // VACGEfq 1010 UINT64_C(4077915664), // VACGEhd 1011 UINT64_C(4077915728), // VACGEhq 1012 UINT64_C(4078964240), // VACGTfd 1013 UINT64_C(4078964304), // VACGTfq 1014 UINT64_C(4080012816), // VACGThd 1015 UINT64_C(4080012880), // VACGThq 1016 UINT64_C(238029568), // VADDD 1017 UINT64_C(238029056), // VADDH 1018 UINT64_C(4070573056), // VADDHNv2i32 1019 UINT64_C(4069524480), // VADDHNv4i16 1020 UINT64_C(4068475904), // VADDHNv8i8 1021 UINT64_C(4070572032), // VADDLsv2i64 1022 UINT64_C(4069523456), // VADDLsv4i32 1023 UINT64_C(4068474880), // VADDLsv8i16 1024 UINT64_C(4087349248), // VADDLuv2i64 1025 UINT64_C(4086300672), // VADDLuv4i32 1026 UINT64_C(4085252096), // VADDLuv8i16 1027 UINT64_C(238029312), // VADDS 1028 UINT64_C(4070572288), // VADDWsv2i64 1029 UINT64_C(4069523712), // VADDWsv4i32 1030 UINT64_C(4068475136), // VADDWsv8i16 1031 UINT64_C(4087349504), // VADDWuv2i64 1032 UINT64_C(4086300928), // VADDWuv4i32 1033 UINT64_C(4085252352), // VADDWuv8i16 1034 UINT64_C(4060089600), // VADDfd 1035 UINT64_C(4060089664), // VADDfq 1036 UINT64_C(4061138176), // VADDhd 1037 UINT64_C(4061138240), // VADDhq 1038 UINT64_C(4060088384), // VADDv16i8 1039 UINT64_C(4063234048), // VADDv1i64 1040 UINT64_C(4062185472), // VADDv2i32 1041 UINT64_C(4063234112), // VADDv2i64 1042 UINT64_C(4061136896), // VADDv4i16 1043 UINT64_C(4062185536), // VADDv4i32 1044 UINT64_C(4061136960), // VADDv8i16 1045 UINT64_C(4060088320), // VADDv8i8 1046 UINT64_C(4060086544), // VANDd 1047 UINT64_C(4060086608), // VANDq 1048 UINT64_C(4061135120), // VBICd 1049 UINT64_C(4068475184), // VBICiv2i32 1050 UINT64_C(4068477232), // VBICiv4i16 1051 UINT64_C(4068475248), // VBICiv4i32 1052 UINT64_C(4068477296), // VBICiv8i16 1053 UINT64_C(4061135184), // VBICq 1054 UINT64_C(4080009488), // VBIFd 1055 UINT64_C(4080009552), // VBIFq 1056 UINT64_C(4078960912), // VBITd 1057 UINT64_C(4078960976), // VBITq 1058 UINT64_C(4077912336), // VBSLd 1059 UINT64_C(4077912400), // VBSLq 1060 UINT64_C(4237297664), // VCADDv2f32 1061 UINT64_C(4236249088), // VCADDv4f16 1062 UINT64_C(4237297728), // VCADDv4f32 1063 UINT64_C(4236249152), // VCADDv8f16 1064 UINT64_C(4060089856), // VCEQfd 1065 UINT64_C(4060089920), // VCEQfq 1066 UINT64_C(4061138432), // VCEQhd 1067 UINT64_C(4061138496), // VCEQhq 1068 UINT64_C(4076865616), // VCEQv16i8 1069 UINT64_C(4078962704), // VCEQv2i32 1070 UINT64_C(4077914128), // VCEQv4i16 1071 UINT64_C(4078962768), // VCEQv4i32 1072 UINT64_C(4077914192), // VCEQv8i16 1073 UINT64_C(4076865552), // VCEQv8i8 1074 UINT64_C(4088463680), // VCEQzv16i8 1075 UINT64_C(4088988928), // VCEQzv2f32 1076 UINT64_C(4088987904), // VCEQzv2i32 1077 UINT64_C(4088726784), // VCEQzv4f16 1078 UINT64_C(4088988992), // VCEQzv4f32 1079 UINT64_C(4088725760), // VCEQzv4i16 1080 UINT64_C(4088987968), // VCEQzv4i32 1081 UINT64_C(4088726848), // VCEQzv8f16 1082 UINT64_C(4088725824), // VCEQzv8i16 1083 UINT64_C(4088463616), // VCEQzv8i8 1084 UINT64_C(4076867072), // VCGEfd 1085 UINT64_C(4076867136), // VCGEfq 1086 UINT64_C(4077915648), // VCGEhd 1087 UINT64_C(4077915712), // VCGEhq 1088 UINT64_C(4060087120), // VCGEsv16i8 1089 UINT64_C(4062184208), // VCGEsv2i32 1090 UINT64_C(4061135632), // VCGEsv4i16 1091 UINT64_C(4062184272), // VCGEsv4i32 1092 UINT64_C(4061135696), // VCGEsv8i16 1093 UINT64_C(4060087056), // VCGEsv8i8 1094 UINT64_C(4076864336), // VCGEuv16i8 1095 UINT64_C(4078961424), // VCGEuv2i32 1096 UINT64_C(4077912848), // VCGEuv4i16 1097 UINT64_C(4078961488), // VCGEuv4i32 1098 UINT64_C(4077912912), // VCGEuv8i16 1099 UINT64_C(4076864272), // VCGEuv8i8 1100 UINT64_C(4088463552), // VCGEzv16i8 1101 UINT64_C(4088988800), // VCGEzv2f32 1102 UINT64_C(4088987776), // VCGEzv2i32 1103 UINT64_C(4088726656), // VCGEzv4f16 1104 UINT64_C(4088988864), // VCGEzv4f32 1105 UINT64_C(4088725632), // VCGEzv4i16 1106 UINT64_C(4088987840), // VCGEzv4i32 1107 UINT64_C(4088726720), // VCGEzv8f16 1108 UINT64_C(4088725696), // VCGEzv8i16 1109 UINT64_C(4088463488), // VCGEzv8i8 1110 UINT64_C(4078964224), // VCGTfd 1111 UINT64_C(4078964288), // VCGTfq 1112 UINT64_C(4080012800), // VCGThd 1113 UINT64_C(4080012864), // VCGThq 1114 UINT64_C(4060087104), // VCGTsv16i8 1115 UINT64_C(4062184192), // VCGTsv2i32 1116 UINT64_C(4061135616), // VCGTsv4i16 1117 UINT64_C(4062184256), // VCGTsv4i32 1118 UINT64_C(4061135680), // VCGTsv8i16 1119 UINT64_C(4060087040), // VCGTsv8i8 1120 UINT64_C(4076864320), // VCGTuv16i8 1121 UINT64_C(4078961408), // VCGTuv2i32 1122 UINT64_C(4077912832), // VCGTuv4i16 1123 UINT64_C(4078961472), // VCGTuv4i32 1124 UINT64_C(4077912896), // VCGTuv8i16 1125 UINT64_C(4076864256), // VCGTuv8i8 1126 UINT64_C(4088463424), // VCGTzv16i8 1127 UINT64_C(4088988672), // VCGTzv2f32 1128 UINT64_C(4088987648), // VCGTzv2i32 1129 UINT64_C(4088726528), // VCGTzv4f16 1130 UINT64_C(4088988736), // VCGTzv4f32 1131 UINT64_C(4088725504), // VCGTzv4i16 1132 UINT64_C(4088987712), // VCGTzv4i32 1133 UINT64_C(4088726592), // VCGTzv8f16 1134 UINT64_C(4088725568), // VCGTzv8i16 1135 UINT64_C(4088463360), // VCGTzv8i8 1136 UINT64_C(4088463808), // VCLEzv16i8 1137 UINT64_C(4088989056), // VCLEzv2f32 1138 UINT64_C(4088988032), // VCLEzv2i32 1139 UINT64_C(4088726912), // VCLEzv4f16 1140 UINT64_C(4088989120), // VCLEzv4f32 1141 UINT64_C(4088725888), // VCLEzv4i16 1142 UINT64_C(4088988096), // VCLEzv4i32 1143 UINT64_C(4088726976), // VCLEzv8f16 1144 UINT64_C(4088725952), // VCLEzv8i16 1145 UINT64_C(4088463744), // VCLEzv8i8 1146 UINT64_C(4088398912), // VCLSv16i8 1147 UINT64_C(4088923136), // VCLSv2i32 1148 UINT64_C(4088660992), // VCLSv4i16 1149 UINT64_C(4088923200), // VCLSv4i32 1150 UINT64_C(4088661056), // VCLSv8i16 1151 UINT64_C(4088398848), // VCLSv8i8 1152 UINT64_C(4088463936), // VCLTzv16i8 1153 UINT64_C(4088989184), // VCLTzv2f32 1154 UINT64_C(4088988160), // VCLTzv2i32 1155 UINT64_C(4088727040), // VCLTzv4f16 1156 UINT64_C(4088989248), // VCLTzv4f32 1157 UINT64_C(4088726016), // VCLTzv4i16 1158 UINT64_C(4088988224), // VCLTzv4i32 1159 UINT64_C(4088727104), // VCLTzv8f16 1160 UINT64_C(4088726080), // VCLTzv8i16 1161 UINT64_C(4088463872), // VCLTzv8i8 1162 UINT64_C(4088399040), // VCLZv16i8 1163 UINT64_C(4088923264), // VCLZv2i32 1164 UINT64_C(4088661120), // VCLZv4i16 1165 UINT64_C(4088923328), // VCLZv4i32 1166 UINT64_C(4088661184), // VCLZv8i16 1167 UINT64_C(4088398976), // VCLZv8i8 1168 UINT64_C(4231006208), // VCMLAv2f32 1169 UINT64_C(4269803520), // VCMLAv2f32_indexed 1170 UINT64_C(4229957632), // VCMLAv4f16 1171 UINT64_C(4261414912), // VCMLAv4f16_indexed 1172 UINT64_C(4231006272), // VCMLAv4f32 1173 UINT64_C(4269803584), // VCMLAv4f32_indexed 1174 UINT64_C(4229957696), // VCMLAv8f16 1175 UINT64_C(4261414976), // VCMLAv8f16_indexed 1176 UINT64_C(246680384), // VCMPD 1177 UINT64_C(246680512), // VCMPED 1178 UINT64_C(246680000), // VCMPEH 1179 UINT64_C(246680256), // VCMPES 1180 UINT64_C(246746048), // VCMPEZD 1181 UINT64_C(246745536), // VCMPEZH 1182 UINT64_C(246745792), // VCMPEZS 1183 UINT64_C(246679872), // VCMPH 1184 UINT64_C(246680128), // VCMPS 1185 UINT64_C(246745920), // VCMPZD 1186 UINT64_C(246745408), // VCMPZH 1187 UINT64_C(246745664), // VCMPZS 1188 UINT64_C(4088399104), // VCNTd 1189 UINT64_C(4088399168), // VCNTq 1190 UINT64_C(4089118720), // VCVTANSDf 1191 UINT64_C(4088856576), // VCVTANSDh 1192 UINT64_C(4089118784), // VCVTANSQf 1193 UINT64_C(4088856640), // VCVTANSQh 1194 UINT64_C(4089118848), // VCVTANUDf 1195 UINT64_C(4088856704), // VCVTANUDh 1196 UINT64_C(4089118912), // VCVTANUQf 1197 UINT64_C(4088856768), // VCVTANUQh 1198 UINT64_C(4273736640), // VCVTASD 1199 UINT64_C(4273736128), // VCVTASH 1200 UINT64_C(4273736384), // VCVTASS 1201 UINT64_C(4273736512), // VCVTAUD 1202 UINT64_C(4273736000), // VCVTAUH 1203 UINT64_C(4273736256), // VCVTAUS 1204 UINT64_C(246614848), // VCVTBDH 1205 UINT64_C(246549312), // VCVTBHD 1206 UINT64_C(246549056), // VCVTBHS 1207 UINT64_C(246614592), // VCVTBSH 1208 UINT64_C(246876864), // VCVTDS 1209 UINT64_C(4089119488), // VCVTMNSDf 1210 UINT64_C(4088857344), // VCVTMNSDh 1211 UINT64_C(4089119552), // VCVTMNSQf 1212 UINT64_C(4088857408), // VCVTMNSQh 1213 UINT64_C(4089119616), // VCVTMNUDf 1214 UINT64_C(4088857472), // VCVTMNUDh 1215 UINT64_C(4089119680), // VCVTMNUQf 1216 UINT64_C(4088857536), // VCVTMNUQh 1217 UINT64_C(4273933248), // VCVTMSD 1218 UINT64_C(4273932736), // VCVTMSH 1219 UINT64_C(4273932992), // VCVTMSS 1220 UINT64_C(4273933120), // VCVTMUD 1221 UINT64_C(4273932608), // VCVTMUH 1222 UINT64_C(4273932864), // VCVTMUS 1223 UINT64_C(4089118976), // VCVTNNSDf 1224 UINT64_C(4088856832), // VCVTNNSDh 1225 UINT64_C(4089119040), // VCVTNNSQf 1226 UINT64_C(4088856896), // VCVTNNSQh 1227 UINT64_C(4089119104), // VCVTNNUDf 1228 UINT64_C(4088856960), // VCVTNNUDh 1229 UINT64_C(4089119168), // VCVTNNUQf 1230 UINT64_C(4088857024), // VCVTNNUQh 1231 UINT64_C(4273802176), // VCVTNSD 1232 UINT64_C(4273801664), // VCVTNSH 1233 UINT64_C(4273801920), // VCVTNSS 1234 UINT64_C(4273802048), // VCVTNUD 1235 UINT64_C(4273801536), // VCVTNUH 1236 UINT64_C(4273801792), // VCVTNUS 1237 UINT64_C(4089119232), // VCVTPNSDf 1238 UINT64_C(4088857088), // VCVTPNSDh 1239 UINT64_C(4089119296), // VCVTPNSQf 1240 UINT64_C(4088857152), // VCVTPNSQh 1241 UINT64_C(4089119360), // VCVTPNUDf 1242 UINT64_C(4088857216), // VCVTPNUDh 1243 UINT64_C(4089119424), // VCVTPNUQf 1244 UINT64_C(4088857280), // VCVTPNUQh 1245 UINT64_C(4273867712), // VCVTPSD 1246 UINT64_C(4273867200), // VCVTPSH 1247 UINT64_C(4273867456), // VCVTPSS 1248 UINT64_C(4273867584), // VCVTPUD 1249 UINT64_C(4273867072), // VCVTPUH 1250 UINT64_C(4273867328), // VCVTPUS 1251 UINT64_C(246877120), // VCVTSD 1252 UINT64_C(246614976), // VCVTTDH 1253 UINT64_C(246549440), // VCVTTHD 1254 UINT64_C(246549184), // VCVTTHS 1255 UINT64_C(246614720), // VCVTTSH 1256 UINT64_C(4088792576), // VCVTf2h 1257 UINT64_C(4089120512), // VCVTf2sd 1258 UINT64_C(4089120576), // VCVTf2sq 1259 UINT64_C(4089120640), // VCVTf2ud 1260 UINT64_C(4089120704), // VCVTf2uq 1261 UINT64_C(4068478736), // VCVTf2xsd 1262 UINT64_C(4068478800), // VCVTf2xsq 1263 UINT64_C(4085255952), // VCVTf2xud 1264 UINT64_C(4085256016), // VCVTf2xuq 1265 UINT64_C(4088792832), // VCVTh2f 1266 UINT64_C(4088858368), // VCVTh2sd 1267 UINT64_C(4088858432), // VCVTh2sq 1268 UINT64_C(4088858496), // VCVTh2ud 1269 UINT64_C(4088858560), // VCVTh2uq 1270 UINT64_C(4068478224), // VCVTh2xsd 1271 UINT64_C(4068478288), // VCVTh2xsq 1272 UINT64_C(4085255440), // VCVTh2xud 1273 UINT64_C(4085255504), // VCVTh2xuq 1274 UINT64_C(4089120256), // VCVTs2fd 1275 UINT64_C(4089120320), // VCVTs2fq 1276 UINT64_C(4088858112), // VCVTs2hd 1277 UINT64_C(4088858176), // VCVTs2hq 1278 UINT64_C(4089120384), // VCVTu2fd 1279 UINT64_C(4089120448), // VCVTu2fq 1280 UINT64_C(4088858240), // VCVTu2hd 1281 UINT64_C(4088858304), // VCVTu2hq 1282 UINT64_C(4068478480), // VCVTxs2fd 1283 UINT64_C(4068478544), // VCVTxs2fq 1284 UINT64_C(4068477968), // VCVTxs2hd 1285 UINT64_C(4068478032), // VCVTxs2hq 1286 UINT64_C(4085255696), // VCVTxu2fd 1287 UINT64_C(4085255760), // VCVTxu2fq 1288 UINT64_C(4085255184), // VCVTxu2hd 1289 UINT64_C(4085255248), // VCVTxu2hq 1290 UINT64_C(243272448), // VDIVD 1291 UINT64_C(243271936), // VDIVH 1292 UINT64_C(243272192), // VDIVS 1293 UINT64_C(243272496), // VDUP16d 1294 UINT64_C(245369648), // VDUP16q 1295 UINT64_C(243272464), // VDUP32d 1296 UINT64_C(245369616), // VDUP32q 1297 UINT64_C(247466768), // VDUP8d 1298 UINT64_C(249563920), // VDUP8q 1299 UINT64_C(4088531968), // VDUPLN16d 1300 UINT64_C(4088532032), // VDUPLN16q 1301 UINT64_C(4088663040), // VDUPLN32d 1302 UINT64_C(4088663104), // VDUPLN32q 1303 UINT64_C(4088466432), // VDUPLN8d 1304 UINT64_C(4088466496), // VDUPLN8q 1305 UINT64_C(4076863760), // VEORd 1306 UINT64_C(4076863824), // VEORq 1307 UINT64_C(4071620608), // VEXTd16 1308 UINT64_C(4071620608), // VEXTd32 1309 UINT64_C(4071620608), // VEXTd8 1310 UINT64_C(4071620672), // VEXTq16 1311 UINT64_C(4071620672), // VEXTq32 1312 UINT64_C(4071620672), // VEXTq64 1313 UINT64_C(4071620672), // VEXTq8 1314 UINT64_C(245369600), // VFMAD 1315 UINT64_C(245369088), // VFMAH 1316 UINT64_C(245369344), // VFMAS 1317 UINT64_C(4060089360), // VFMAfd 1318 UINT64_C(4060089424), // VFMAfq 1319 UINT64_C(4061137936), // VFMAhd 1320 UINT64_C(4061138000), // VFMAhq 1321 UINT64_C(245369664), // VFMSD 1322 UINT64_C(245369152), // VFMSH 1323 UINT64_C(245369408), // VFMSS 1324 UINT64_C(4062186512), // VFMSfd 1325 UINT64_C(4062186576), // VFMSfq 1326 UINT64_C(4063235088), // VFMShd 1327 UINT64_C(4063235152), // VFMShq 1328 UINT64_C(244321088), // VFNMAD 1329 UINT64_C(244320576), // VFNMAH 1330 UINT64_C(244320832), // VFNMAS 1331 UINT64_C(244321024), // VFNMSD 1332 UINT64_C(244320512), // VFNMSH 1333 UINT64_C(244320768), // VFNMSS 1334 UINT64_C(235932432), // VGETLNi32 1335 UINT64_C(235932464), // VGETLNs16 1336 UINT64_C(240126736), // VGETLNs8 1337 UINT64_C(244321072), // VGETLNu16 1338 UINT64_C(248515344), // VGETLNu8 1339 UINT64_C(4060086336), // VHADDsv16i8 1340 UINT64_C(4062183424), // VHADDsv2i32 1341 UINT64_C(4061134848), // VHADDsv4i16 1342 UINT64_C(4062183488), // VHADDsv4i32 1343 UINT64_C(4061134912), // VHADDsv8i16 1344 UINT64_C(4060086272), // VHADDsv8i8 1345 UINT64_C(4076863552), // VHADDuv16i8 1346 UINT64_C(4078960640), // VHADDuv2i32 1347 UINT64_C(4077912064), // VHADDuv4i16 1348 UINT64_C(4078960704), // VHADDuv4i32 1349 UINT64_C(4077912128), // VHADDuv8i16 1350 UINT64_C(4076863488), // VHADDuv8i8 1351 UINT64_C(4060086848), // VHSUBsv16i8 1352 UINT64_C(4062183936), // VHSUBsv2i32 1353 UINT64_C(4061135360), // VHSUBsv4i16 1354 UINT64_C(4062184000), // VHSUBsv4i32 1355 UINT64_C(4061135424), // VHSUBsv8i16 1356 UINT64_C(4060086784), // VHSUBsv8i8 1357 UINT64_C(4076864064), // VHSUBuv16i8 1358 UINT64_C(4078961152), // VHSUBuv2i32 1359 UINT64_C(4077912576), // VHSUBuv4i16 1360 UINT64_C(4078961216), // VHSUBuv4i32 1361 UINT64_C(4077912640), // VHSUBuv8i16 1362 UINT64_C(4076864000), // VHSUBuv8i8 1363 UINT64_C(4272949952), // VINSH 1364 UINT64_C(247008192), // VJCVT 1365 UINT64_C(4104129615), // VLD1DUPd16 1366 UINT64_C(4104129613), // VLD1DUPd16wb_fixed 1367 UINT64_C(4104129600), // VLD1DUPd16wb_register 1368 UINT64_C(4104129679), // VLD1DUPd32 1369 UINT64_C(4104129677), // VLD1DUPd32wb_fixed 1370 UINT64_C(4104129664), // VLD1DUPd32wb_register 1371 UINT64_C(4104129551), // VLD1DUPd8 1372 UINT64_C(4104129549), // VLD1DUPd8wb_fixed 1373 UINT64_C(4104129536), // VLD1DUPd8wb_register 1374 UINT64_C(4104129647), // VLD1DUPq16 1375 UINT64_C(4104129645), // VLD1DUPq16wb_fixed 1376 UINT64_C(4104129632), // VLD1DUPq16wb_register 1377 UINT64_C(4104129711), // VLD1DUPq32 1378 UINT64_C(4104129709), // VLD1DUPq32wb_fixed 1379 UINT64_C(4104129696), // VLD1DUPq32wb_register 1380 UINT64_C(4104129583), // VLD1DUPq8 1381 UINT64_C(4104129581), // VLD1DUPq8wb_fixed 1382 UINT64_C(4104129568), // VLD1DUPq8wb_register 1383 UINT64_C(4104127503), // VLD1LNd16 1384 UINT64_C(4104127488), // VLD1LNd16_UPD 1385 UINT64_C(4104128527), // VLD1LNd32 1386 UINT64_C(4104128512), // VLD1LNd32_UPD 1387 UINT64_C(4104126479), // VLD1LNd8 1388 UINT64_C(4104126464), // VLD1LNd8_UPD 1389 UINT64_C(0), // VLD1LNq16Pseudo 1390 UINT64_C(0), // VLD1LNq16Pseudo_UPD 1391 UINT64_C(0), // VLD1LNq32Pseudo 1392 UINT64_C(0), // VLD1LNq32Pseudo_UPD 1393 UINT64_C(0), // VLD1LNq8Pseudo 1394 UINT64_C(0), // VLD1LNq8Pseudo_UPD 1395 UINT64_C(4095739727), // VLD1d16 1396 UINT64_C(4095738447), // VLD1d16Q 1397 UINT64_C(0), // VLD1d16QPseudo 1398 UINT64_C(4095738445), // VLD1d16Qwb_fixed 1399 UINT64_C(4095738432), // VLD1d16Qwb_register 1400 UINT64_C(4095739471), // VLD1d16T 1401 UINT64_C(0), // VLD1d16TPseudo 1402 UINT64_C(4095739469), // VLD1d16Twb_fixed 1403 UINT64_C(4095739456), // VLD1d16Twb_register 1404 UINT64_C(4095739725), // VLD1d16wb_fixed 1405 UINT64_C(4095739712), // VLD1d16wb_register 1406 UINT64_C(4095739791), // VLD1d32 1407 UINT64_C(4095738511), // VLD1d32Q 1408 UINT64_C(0), // VLD1d32QPseudo 1409 UINT64_C(4095738509), // VLD1d32Qwb_fixed 1410 UINT64_C(4095738496), // VLD1d32Qwb_register 1411 UINT64_C(4095739535), // VLD1d32T 1412 UINT64_C(0), // VLD1d32TPseudo 1413 UINT64_C(4095739533), // VLD1d32Twb_fixed 1414 UINT64_C(4095739520), // VLD1d32Twb_register 1415 UINT64_C(4095739789), // VLD1d32wb_fixed 1416 UINT64_C(4095739776), // VLD1d32wb_register 1417 UINT64_C(4095739855), // VLD1d64 1418 UINT64_C(4095738575), // VLD1d64Q 1419 UINT64_C(0), // VLD1d64QPseudo 1420 UINT64_C(0), // VLD1d64QPseudoWB_fixed 1421 UINT64_C(0), // VLD1d64QPseudoWB_register 1422 UINT64_C(4095738573), // VLD1d64Qwb_fixed 1423 UINT64_C(4095738560), // VLD1d64Qwb_register 1424 UINT64_C(4095739599), // VLD1d64T 1425 UINT64_C(0), // VLD1d64TPseudo 1426 UINT64_C(0), // VLD1d64TPseudoWB_fixed 1427 UINT64_C(0), // VLD1d64TPseudoWB_register 1428 UINT64_C(4095739597), // VLD1d64Twb_fixed 1429 UINT64_C(4095739584), // VLD1d64Twb_register 1430 UINT64_C(4095739853), // VLD1d64wb_fixed 1431 UINT64_C(4095739840), // VLD1d64wb_register 1432 UINT64_C(4095739663), // VLD1d8 1433 UINT64_C(4095738383), // VLD1d8Q 1434 UINT64_C(0), // VLD1d8QPseudo 1435 UINT64_C(4095738381), // VLD1d8Qwb_fixed 1436 UINT64_C(4095738368), // VLD1d8Qwb_register 1437 UINT64_C(4095739407), // VLD1d8T 1438 UINT64_C(0), // VLD1d8TPseudo 1439 UINT64_C(4095739405), // VLD1d8Twb_fixed 1440 UINT64_C(4095739392), // VLD1d8Twb_register 1441 UINT64_C(4095739661), // VLD1d8wb_fixed 1442 UINT64_C(4095739648), // VLD1d8wb_register 1443 UINT64_C(4095740495), // VLD1q16 1444 UINT64_C(0), // VLD1q16HighQPseudo 1445 UINT64_C(0), // VLD1q16HighTPseudo 1446 UINT64_C(0), // VLD1q16LowQPseudo_UPD 1447 UINT64_C(0), // VLD1q16LowTPseudo_UPD 1448 UINT64_C(4095740493), // VLD1q16wb_fixed 1449 UINT64_C(4095740480), // VLD1q16wb_register 1450 UINT64_C(4095740559), // VLD1q32 1451 UINT64_C(0), // VLD1q32HighQPseudo 1452 UINT64_C(0), // VLD1q32HighTPseudo 1453 UINT64_C(0), // VLD1q32LowQPseudo_UPD 1454 UINT64_C(0), // VLD1q32LowTPseudo_UPD 1455 UINT64_C(4095740557), // VLD1q32wb_fixed 1456 UINT64_C(4095740544), // VLD1q32wb_register 1457 UINT64_C(4095740623), // VLD1q64 1458 UINT64_C(0), // VLD1q64HighQPseudo 1459 UINT64_C(0), // VLD1q64HighTPseudo 1460 UINT64_C(0), // VLD1q64LowQPseudo_UPD 1461 UINT64_C(0), // VLD1q64LowTPseudo_UPD 1462 UINT64_C(4095740621), // VLD1q64wb_fixed 1463 UINT64_C(4095740608), // VLD1q64wb_register 1464 UINT64_C(4095740431), // VLD1q8 1465 UINT64_C(0), // VLD1q8HighQPseudo 1466 UINT64_C(0), // VLD1q8HighTPseudo 1467 UINT64_C(0), // VLD1q8LowQPseudo_UPD 1468 UINT64_C(0), // VLD1q8LowTPseudo_UPD 1469 UINT64_C(4095740429), // VLD1q8wb_fixed 1470 UINT64_C(4095740416), // VLD1q8wb_register 1471 UINT64_C(4104129871), // VLD2DUPd16 1472 UINT64_C(4104129869), // VLD2DUPd16wb_fixed 1473 UINT64_C(4104129856), // VLD2DUPd16wb_register 1474 UINT64_C(4104129903), // VLD2DUPd16x2 1475 UINT64_C(4104129901), // VLD2DUPd16x2wb_fixed 1476 UINT64_C(4104129888), // VLD2DUPd16x2wb_register 1477 UINT64_C(4104129935), // VLD2DUPd32 1478 UINT64_C(4104129933), // VLD2DUPd32wb_fixed 1479 UINT64_C(4104129920), // VLD2DUPd32wb_register 1480 UINT64_C(4104129967), // VLD2DUPd32x2 1481 UINT64_C(4104129965), // VLD2DUPd32x2wb_fixed 1482 UINT64_C(4104129952), // VLD2DUPd32x2wb_register 1483 UINT64_C(4104129807), // VLD2DUPd8 1484 UINT64_C(4104129805), // VLD2DUPd8wb_fixed 1485 UINT64_C(4104129792), // VLD2DUPd8wb_register 1486 UINT64_C(4104129839), // VLD2DUPd8x2 1487 UINT64_C(4104129837), // VLD2DUPd8x2wb_fixed 1488 UINT64_C(4104129824), // VLD2DUPd8x2wb_register 1489 UINT64_C(0), // VLD2DUPq16EvenPseudo 1490 UINT64_C(0), // VLD2DUPq16OddPseudo 1491 UINT64_C(0), // VLD2DUPq32EvenPseudo 1492 UINT64_C(0), // VLD2DUPq32OddPseudo 1493 UINT64_C(0), // VLD2DUPq8EvenPseudo 1494 UINT64_C(0), // VLD2DUPq8OddPseudo 1495 UINT64_C(4104127759), // VLD2LNd16 1496 UINT64_C(0), // VLD2LNd16Pseudo 1497 UINT64_C(0), // VLD2LNd16Pseudo_UPD 1498 UINT64_C(4104127744), // VLD2LNd16_UPD 1499 UINT64_C(4104128783), // VLD2LNd32 1500 UINT64_C(0), // VLD2LNd32Pseudo 1501 UINT64_C(0), // VLD2LNd32Pseudo_UPD 1502 UINT64_C(4104128768), // VLD2LNd32_UPD 1503 UINT64_C(4104126735), // VLD2LNd8 1504 UINT64_C(0), // VLD2LNd8Pseudo 1505 UINT64_C(0), // VLD2LNd8Pseudo_UPD 1506 UINT64_C(4104126720), // VLD2LNd8_UPD 1507 UINT64_C(4104127791), // VLD2LNq16 1508 UINT64_C(0), // VLD2LNq16Pseudo 1509 UINT64_C(0), // VLD2LNq16Pseudo_UPD 1510 UINT64_C(4104127776), // VLD2LNq16_UPD 1511 UINT64_C(4104128847), // VLD2LNq32 1512 UINT64_C(0), // VLD2LNq32Pseudo 1513 UINT64_C(0), // VLD2LNq32Pseudo_UPD 1514 UINT64_C(4104128832), // VLD2LNq32_UPD 1515 UINT64_C(4095740239), // VLD2b16 1516 UINT64_C(4095740237), // VLD2b16wb_fixed 1517 UINT64_C(4095740224), // VLD2b16wb_register 1518 UINT64_C(4095740303), // VLD2b32 1519 UINT64_C(4095740301), // VLD2b32wb_fixed 1520 UINT64_C(4095740288), // VLD2b32wb_register 1521 UINT64_C(4095740175), // VLD2b8 1522 UINT64_C(4095740173), // VLD2b8wb_fixed 1523 UINT64_C(4095740160), // VLD2b8wb_register 1524 UINT64_C(4095739983), // VLD2d16 1525 UINT64_C(4095739981), // VLD2d16wb_fixed 1526 UINT64_C(4095739968), // VLD2d16wb_register 1527 UINT64_C(4095740047), // VLD2d32 1528 UINT64_C(4095740045), // VLD2d32wb_fixed 1529 UINT64_C(4095740032), // VLD2d32wb_register 1530 UINT64_C(4095739919), // VLD2d8 1531 UINT64_C(4095739917), // VLD2d8wb_fixed 1532 UINT64_C(4095739904), // VLD2d8wb_register 1533 UINT64_C(4095738703), // VLD2q16 1534 UINT64_C(0), // VLD2q16Pseudo 1535 UINT64_C(0), // VLD2q16PseudoWB_fixed 1536 UINT64_C(0), // VLD2q16PseudoWB_register 1537 UINT64_C(4095738701), // VLD2q16wb_fixed 1538 UINT64_C(4095738688), // VLD2q16wb_register 1539 UINT64_C(4095738767), // VLD2q32 1540 UINT64_C(0), // VLD2q32Pseudo 1541 UINT64_C(0), // VLD2q32PseudoWB_fixed 1542 UINT64_C(0), // VLD2q32PseudoWB_register 1543 UINT64_C(4095738765), // VLD2q32wb_fixed 1544 UINT64_C(4095738752), // VLD2q32wb_register 1545 UINT64_C(4095738639), // VLD2q8 1546 UINT64_C(0), // VLD2q8Pseudo 1547 UINT64_C(0), // VLD2q8PseudoWB_fixed 1548 UINT64_C(0), // VLD2q8PseudoWB_register 1549 UINT64_C(4095738637), // VLD2q8wb_fixed 1550 UINT64_C(4095738624), // VLD2q8wb_register 1551 UINT64_C(4104130127), // VLD3DUPd16 1552 UINT64_C(0), // VLD3DUPd16Pseudo 1553 UINT64_C(0), // VLD3DUPd16Pseudo_UPD 1554 UINT64_C(4104130112), // VLD3DUPd16_UPD 1555 UINT64_C(4104130191), // VLD3DUPd32 1556 UINT64_C(0), // VLD3DUPd32Pseudo 1557 UINT64_C(0), // VLD3DUPd32Pseudo_UPD 1558 UINT64_C(4104130176), // VLD3DUPd32_UPD 1559 UINT64_C(4104130063), // VLD3DUPd8 1560 UINT64_C(0), // VLD3DUPd8Pseudo 1561 UINT64_C(0), // VLD3DUPd8Pseudo_UPD 1562 UINT64_C(4104130048), // VLD3DUPd8_UPD 1563 UINT64_C(4104130159), // VLD3DUPq16 1564 UINT64_C(0), // VLD3DUPq16EvenPseudo 1565 UINT64_C(0), // VLD3DUPq16OddPseudo 1566 UINT64_C(4104130144), // VLD3DUPq16_UPD 1567 UINT64_C(4104130223), // VLD3DUPq32 1568 UINT64_C(0), // VLD3DUPq32EvenPseudo 1569 UINT64_C(0), // VLD3DUPq32OddPseudo 1570 UINT64_C(4104130208), // VLD3DUPq32_UPD 1571 UINT64_C(4104130095), // VLD3DUPq8 1572 UINT64_C(0), // VLD3DUPq8EvenPseudo 1573 UINT64_C(0), // VLD3DUPq8OddPseudo 1574 UINT64_C(4104130080), // VLD3DUPq8_UPD 1575 UINT64_C(4104128015), // VLD3LNd16 1576 UINT64_C(0), // VLD3LNd16Pseudo 1577 UINT64_C(0), // VLD3LNd16Pseudo_UPD 1578 UINT64_C(4104128000), // VLD3LNd16_UPD 1579 UINT64_C(4104129039), // VLD3LNd32 1580 UINT64_C(0), // VLD3LNd32Pseudo 1581 UINT64_C(0), // VLD3LNd32Pseudo_UPD 1582 UINT64_C(4104129024), // VLD3LNd32_UPD 1583 UINT64_C(4104126991), // VLD3LNd8 1584 UINT64_C(0), // VLD3LNd8Pseudo 1585 UINT64_C(0), // VLD3LNd8Pseudo_UPD 1586 UINT64_C(4104126976), // VLD3LNd8_UPD 1587 UINT64_C(4104128047), // VLD3LNq16 1588 UINT64_C(0), // VLD3LNq16Pseudo 1589 UINT64_C(0), // VLD3LNq16Pseudo_UPD 1590 UINT64_C(4104128032), // VLD3LNq16_UPD 1591 UINT64_C(4104129103), // VLD3LNq32 1592 UINT64_C(0), // VLD3LNq32Pseudo 1593 UINT64_C(0), // VLD3LNq32Pseudo_UPD 1594 UINT64_C(4104129088), // VLD3LNq32_UPD 1595 UINT64_C(4095738959), // VLD3d16 1596 UINT64_C(0), // VLD3d16Pseudo 1597 UINT64_C(0), // VLD3d16Pseudo_UPD 1598 UINT64_C(4095738944), // VLD3d16_UPD 1599 UINT64_C(4095739023), // VLD3d32 1600 UINT64_C(0), // VLD3d32Pseudo 1601 UINT64_C(0), // VLD3d32Pseudo_UPD 1602 UINT64_C(4095739008), // VLD3d32_UPD 1603 UINT64_C(4095738895), // VLD3d8 1604 UINT64_C(0), // VLD3d8Pseudo 1605 UINT64_C(0), // VLD3d8Pseudo_UPD 1606 UINT64_C(4095738880), // VLD3d8_UPD 1607 UINT64_C(4095739215), // VLD3q16 1608 UINT64_C(0), // VLD3q16Pseudo_UPD 1609 UINT64_C(4095739200), // VLD3q16_UPD 1610 UINT64_C(0), // VLD3q16oddPseudo 1611 UINT64_C(0), // VLD3q16oddPseudo_UPD 1612 UINT64_C(4095739279), // VLD3q32 1613 UINT64_C(0), // VLD3q32Pseudo_UPD 1614 UINT64_C(4095739264), // VLD3q32_UPD 1615 UINT64_C(0), // VLD3q32oddPseudo 1616 UINT64_C(0), // VLD3q32oddPseudo_UPD 1617 UINT64_C(4095739151), // VLD3q8 1618 UINT64_C(0), // VLD3q8Pseudo_UPD 1619 UINT64_C(4095739136), // VLD3q8_UPD 1620 UINT64_C(0), // VLD3q8oddPseudo 1621 UINT64_C(0), // VLD3q8oddPseudo_UPD 1622 UINT64_C(4104130383), // VLD4DUPd16 1623 UINT64_C(0), // VLD4DUPd16Pseudo 1624 UINT64_C(0), // VLD4DUPd16Pseudo_UPD 1625 UINT64_C(4104130368), // VLD4DUPd16_UPD 1626 UINT64_C(4104130447), // VLD4DUPd32 1627 UINT64_C(0), // VLD4DUPd32Pseudo 1628 UINT64_C(0), // VLD4DUPd32Pseudo_UPD 1629 UINT64_C(4104130432), // VLD4DUPd32_UPD 1630 UINT64_C(4104130319), // VLD4DUPd8 1631 UINT64_C(0), // VLD4DUPd8Pseudo 1632 UINT64_C(0), // VLD4DUPd8Pseudo_UPD 1633 UINT64_C(4104130304), // VLD4DUPd8_UPD 1634 UINT64_C(4104130415), // VLD4DUPq16 1635 UINT64_C(0), // VLD4DUPq16EvenPseudo 1636 UINT64_C(0), // VLD4DUPq16OddPseudo 1637 UINT64_C(4104130400), // VLD4DUPq16_UPD 1638 UINT64_C(4104130479), // VLD4DUPq32 1639 UINT64_C(0), // VLD4DUPq32EvenPseudo 1640 UINT64_C(0), // VLD4DUPq32OddPseudo 1641 UINT64_C(4104130464), // VLD4DUPq32_UPD 1642 UINT64_C(4104130351), // VLD4DUPq8 1643 UINT64_C(0), // VLD4DUPq8EvenPseudo 1644 UINT64_C(0), // VLD4DUPq8OddPseudo 1645 UINT64_C(4104130336), // VLD4DUPq8_UPD 1646 UINT64_C(4104128271), // VLD4LNd16 1647 UINT64_C(0), // VLD4LNd16Pseudo 1648 UINT64_C(0), // VLD4LNd16Pseudo_UPD 1649 UINT64_C(4104128256), // VLD4LNd16_UPD 1650 UINT64_C(4104129295), // VLD4LNd32 1651 UINT64_C(0), // VLD4LNd32Pseudo 1652 UINT64_C(0), // VLD4LNd32Pseudo_UPD 1653 UINT64_C(4104129280), // VLD4LNd32_UPD 1654 UINT64_C(4104127247), // VLD4LNd8 1655 UINT64_C(0), // VLD4LNd8Pseudo 1656 UINT64_C(0), // VLD4LNd8Pseudo_UPD 1657 UINT64_C(4104127232), // VLD4LNd8_UPD 1658 UINT64_C(4104128303), // VLD4LNq16 1659 UINT64_C(0), // VLD4LNq16Pseudo 1660 UINT64_C(0), // VLD4LNq16Pseudo_UPD 1661 UINT64_C(4104128288), // VLD4LNq16_UPD 1662 UINT64_C(4104129359), // VLD4LNq32 1663 UINT64_C(0), // VLD4LNq32Pseudo 1664 UINT64_C(0), // VLD4LNq32Pseudo_UPD 1665 UINT64_C(4104129344), // VLD4LNq32_UPD 1666 UINT64_C(4095737935), // VLD4d16 1667 UINT64_C(0), // VLD4d16Pseudo 1668 UINT64_C(0), // VLD4d16Pseudo_UPD 1669 UINT64_C(4095737920), // VLD4d16_UPD 1670 UINT64_C(4095737999), // VLD4d32 1671 UINT64_C(0), // VLD4d32Pseudo 1672 UINT64_C(0), // VLD4d32Pseudo_UPD 1673 UINT64_C(4095737984), // VLD4d32_UPD 1674 UINT64_C(4095737871), // VLD4d8 1675 UINT64_C(0), // VLD4d8Pseudo 1676 UINT64_C(0), // VLD4d8Pseudo_UPD 1677 UINT64_C(4095737856), // VLD4d8_UPD 1678 UINT64_C(4095738191), // VLD4q16 1679 UINT64_C(0), // VLD4q16Pseudo_UPD 1680 UINT64_C(4095738176), // VLD4q16_UPD 1681 UINT64_C(0), // VLD4q16oddPseudo 1682 UINT64_C(0), // VLD4q16oddPseudo_UPD 1683 UINT64_C(4095738255), // VLD4q32 1684 UINT64_C(0), // VLD4q32Pseudo_UPD 1685 UINT64_C(4095738240), // VLD4q32_UPD 1686 UINT64_C(0), // VLD4q32oddPseudo 1687 UINT64_C(0), // VLD4q32oddPseudo_UPD 1688 UINT64_C(4095738127), // VLD4q8 1689 UINT64_C(0), // VLD4q8Pseudo_UPD 1690 UINT64_C(4095738112), // VLD4q8_UPD 1691 UINT64_C(0), // VLD4q8oddPseudo 1692 UINT64_C(0), // VLD4q8oddPseudo_UPD 1693 UINT64_C(221252352), // VLDMDDB_UPD 1694 UINT64_C(210766592), // VLDMDIA 1695 UINT64_C(212863744), // VLDMDIA_UPD 1696 UINT64_C(0), // VLDMQIA 1697 UINT64_C(221252096), // VLDMSDB_UPD 1698 UINT64_C(210766336), // VLDMSIA 1699 UINT64_C(212863488), // VLDMSIA_UPD 1700 UINT64_C(219155200), // VLDRD 1701 UINT64_C(219154688), // VLDRH 1702 UINT64_C(219154944), // VLDRS 1703 UINT64_C(204474880), // VLLDM 1704 UINT64_C(203426304), // VLSTM 1705 UINT64_C(4269804288), // VMAXNMD 1706 UINT64_C(4269803776), // VMAXNMH 1707 UINT64_C(4076867344), // VMAXNMNDf 1708 UINT64_C(4077915920), // VMAXNMNDh 1709 UINT64_C(4076867408), // VMAXNMNQf 1710 UINT64_C(4077915984), // VMAXNMNQh 1711 UINT64_C(4269804032), // VMAXNMS 1712 UINT64_C(4060090112), // VMAXfd 1713 UINT64_C(4060090176), // VMAXfq 1714 UINT64_C(4061138688), // VMAXhd 1715 UINT64_C(4061138752), // VMAXhq 1716 UINT64_C(4060087872), // VMAXsv16i8 1717 UINT64_C(4062184960), // VMAXsv2i32 1718 UINT64_C(4061136384), // VMAXsv4i16 1719 UINT64_C(4062185024), // VMAXsv4i32 1720 UINT64_C(4061136448), // VMAXsv8i16 1721 UINT64_C(4060087808), // VMAXsv8i8 1722 UINT64_C(4076865088), // VMAXuv16i8 1723 UINT64_C(4078962176), // VMAXuv2i32 1724 UINT64_C(4077913600), // VMAXuv4i16 1725 UINT64_C(4078962240), // VMAXuv4i32 1726 UINT64_C(4077913664), // VMAXuv8i16 1727 UINT64_C(4076865024), // VMAXuv8i8 1728 UINT64_C(4269804352), // VMINNMD 1729 UINT64_C(4269803840), // VMINNMH 1730 UINT64_C(4078964496), // VMINNMNDf 1731 UINT64_C(4080013072), // VMINNMNDh 1732 UINT64_C(4078964560), // VMINNMNQf 1733 UINT64_C(4080013136), // VMINNMNQh 1734 UINT64_C(4269804096), // VMINNMS 1735 UINT64_C(4062187264), // VMINfd 1736 UINT64_C(4062187328), // VMINfq 1737 UINT64_C(4063235840), // VMINhd 1738 UINT64_C(4063235904), // VMINhq 1739 UINT64_C(4060087888), // VMINsv16i8 1740 UINT64_C(4062184976), // VMINsv2i32 1741 UINT64_C(4061136400), // VMINsv4i16 1742 UINT64_C(4062185040), // VMINsv4i32 1743 UINT64_C(4061136464), // VMINsv8i16 1744 UINT64_C(4060087824), // VMINsv8i8 1745 UINT64_C(4076865104), // VMINuv16i8 1746 UINT64_C(4078962192), // VMINuv2i32 1747 UINT64_C(4077913616), // VMINuv4i16 1748 UINT64_C(4078962256), // VMINuv4i32 1749 UINT64_C(4077913680), // VMINuv8i16 1750 UINT64_C(4076865040), // VMINuv8i8 1751 UINT64_C(234883840), // VMLAD 1752 UINT64_C(234883328), // VMLAH 1753 UINT64_C(4070572608), // VMLALslsv2i32 1754 UINT64_C(4069524032), // VMLALslsv4i16 1755 UINT64_C(4087349824), // VMLALsluv2i32 1756 UINT64_C(4086301248), // VMLALsluv4i16 1757 UINT64_C(4070574080), // VMLALsv2i64 1758 UINT64_C(4069525504), // VMLALsv4i32 1759 UINT64_C(4068476928), // VMLALsv8i16 1760 UINT64_C(4087351296), // VMLALuv2i64 1761 UINT64_C(4086302720), // VMLALuv4i32 1762 UINT64_C(4085254144), // VMLALuv8i16 1763 UINT64_C(234883584), // VMLAS 1764 UINT64_C(4060089616), // VMLAfd 1765 UINT64_C(4060089680), // VMLAfq 1766 UINT64_C(4061138192), // VMLAhd 1767 UINT64_C(4061138256), // VMLAhq 1768 UINT64_C(4070572352), // VMLAslfd 1769 UINT64_C(4087349568), // VMLAslfq 1770 UINT64_C(4069523776), // VMLAslhd 1771 UINT64_C(4086300992), // VMLAslhq 1772 UINT64_C(4070572096), // VMLAslv2i32 1773 UINT64_C(4069523520), // VMLAslv4i16 1774 UINT64_C(4087349312), // VMLAslv4i32 1775 UINT64_C(4086300736), // VMLAslv8i16 1776 UINT64_C(4060088640), // VMLAv16i8 1777 UINT64_C(4062185728), // VMLAv2i32 1778 UINT64_C(4061137152), // VMLAv4i16 1779 UINT64_C(4062185792), // VMLAv4i32 1780 UINT64_C(4061137216), // VMLAv8i16 1781 UINT64_C(4060088576), // VMLAv8i8 1782 UINT64_C(234883904), // VMLSD 1783 UINT64_C(234883392), // VMLSH 1784 UINT64_C(4070573632), // VMLSLslsv2i32 1785 UINT64_C(4069525056), // VMLSLslsv4i16 1786 UINT64_C(4087350848), // VMLSLsluv2i32 1787 UINT64_C(4086302272), // VMLSLsluv4i16 1788 UINT64_C(4070574592), // VMLSLsv2i64 1789 UINT64_C(4069526016), // VMLSLsv4i32 1790 UINT64_C(4068477440), // VMLSLsv8i16 1791 UINT64_C(4087351808), // VMLSLuv2i64 1792 UINT64_C(4086303232), // VMLSLuv4i32 1793 UINT64_C(4085254656), // VMLSLuv8i16 1794 UINT64_C(234883648), // VMLSS 1795 UINT64_C(4062186768), // VMLSfd 1796 UINT64_C(4062186832), // VMLSfq 1797 UINT64_C(4063235344), // VMLShd 1798 UINT64_C(4063235408), // VMLShq 1799 UINT64_C(4070573376), // VMLSslfd 1800 UINT64_C(4087350592), // VMLSslfq 1801 UINT64_C(4069524800), // VMLSslhd 1802 UINT64_C(4086302016), // VMLSslhq 1803 UINT64_C(4070573120), // VMLSslv2i32 1804 UINT64_C(4069524544), // VMLSslv4i16 1805 UINT64_C(4087350336), // VMLSslv4i32 1806 UINT64_C(4086301760), // VMLSslv8i16 1807 UINT64_C(4076865856), // VMLSv16i8 1808 UINT64_C(4078962944), // VMLSv2i32 1809 UINT64_C(4077914368), // VMLSv4i16 1810 UINT64_C(4078963008), // VMLSv4i32 1811 UINT64_C(4077914432), // VMLSv8i16 1812 UINT64_C(4076865792), // VMLSv8i8 1813 UINT64_C(246418240), // VMOVD 1814 UINT64_C(205523728), // VMOVDRR 1815 UINT64_C(4272949824), // VMOVH 1816 UINT64_C(234883344), // VMOVHR 1817 UINT64_C(4070574608), // VMOVLsv2i64 1818 UINT64_C(4069526032), // VMOVLsv4i32 1819 UINT64_C(4069001744), // VMOVLsv8i16 1820 UINT64_C(4087351824), // VMOVLuv2i64 1821 UINT64_C(4086303248), // VMOVLuv4i32 1822 UINT64_C(4085778960), // VMOVLuv8i16 1823 UINT64_C(4089053696), // VMOVNv2i32 1824 UINT64_C(4088791552), // VMOVNv4i16 1825 UINT64_C(4088529408), // VMOVNv8i8 1826 UINT64_C(235931920), // VMOVRH 1827 UINT64_C(206572304), // VMOVRRD 1828 UINT64_C(206572048), // VMOVRRS 1829 UINT64_C(235932176), // VMOVRS 1830 UINT64_C(246417984), // VMOVS 1831 UINT64_C(234883600), // VMOVSR 1832 UINT64_C(205523472), // VMOVSRR 1833 UINT64_C(4068478544), // VMOVv16i8 1834 UINT64_C(4068478512), // VMOVv1i64 1835 UINT64_C(4068478736), // VMOVv2f32 1836 UINT64_C(4068474896), // VMOVv2i32 1837 UINT64_C(4068478576), // VMOVv2i64 1838 UINT64_C(4068478800), // VMOVv4f32 1839 UINT64_C(4068476944), // VMOVv4i16 1840 UINT64_C(4068474960), // VMOVv4i32 1841 UINT64_C(4068477008), // VMOVv8i16 1842 UINT64_C(4068478480), // VMOVv8i8 1843 UINT64_C(250677776), // VMRS 1844 UINT64_C(251136528), // VMRS_FPEXC 1845 UINT64_C(251202064), // VMRS_FPINST 1846 UINT64_C(251267600), // VMRS_FPINST2 1847 UINT64_C(250612240), // VMRS_FPSID 1848 UINT64_C(251070992), // VMRS_MVFR0 1849 UINT64_C(251005456), // VMRS_MVFR1 1850 UINT64_C(250939920), // VMRS_MVFR2 1851 UINT64_C(249629200), // VMSR 1852 UINT64_C(250087952), // VMSR_FPEXC 1853 UINT64_C(250153488), // VMSR_FPINST 1854 UINT64_C(250219024), // VMSR_FPINST2 1855 UINT64_C(249563664), // VMSR_FPSID 1856 UINT64_C(236980992), // VMULD 1857 UINT64_C(236980480), // VMULH 1858 UINT64_C(4070575616), // VMULLp64 1859 UINT64_C(4068478464), // VMULLp8 1860 UINT64_C(4070574656), // VMULLslsv2i32 1861 UINT64_C(4069526080), // VMULLslsv4i16 1862 UINT64_C(4087351872), // VMULLsluv2i32 1863 UINT64_C(4086303296), // VMULLsluv4i16 1864 UINT64_C(4070575104), // VMULLsv2i64 1865 UINT64_C(4069526528), // VMULLsv4i32 1866 UINT64_C(4068477952), // VMULLsv8i16 1867 UINT64_C(4087352320), // VMULLuv2i64 1868 UINT64_C(4086303744), // VMULLuv4i32 1869 UINT64_C(4085255168), // VMULLuv8i16 1870 UINT64_C(236980736), // VMULS 1871 UINT64_C(4076866832), // VMULfd 1872 UINT64_C(4076866896), // VMULfq 1873 UINT64_C(4077915408), // VMULhd 1874 UINT64_C(4077915472), // VMULhq 1875 UINT64_C(4076865808), // VMULpd 1876 UINT64_C(4076865872), // VMULpq 1877 UINT64_C(4070574400), // VMULslfd 1878 UINT64_C(4087351616), // VMULslfq 1879 UINT64_C(4069525824), // VMULslhd 1880 UINT64_C(4086303040), // VMULslhq 1881 UINT64_C(4070574144), // VMULslv2i32 1882 UINT64_C(4069525568), // VMULslv4i16 1883 UINT64_C(4087351360), // VMULslv4i32 1884 UINT64_C(4086302784), // VMULslv8i16 1885 UINT64_C(4060088656), // VMULv16i8 1886 UINT64_C(4062185744), // VMULv2i32 1887 UINT64_C(4061137168), // VMULv4i16 1888 UINT64_C(4062185808), // VMULv4i32 1889 UINT64_C(4061137232), // VMULv8i16 1890 UINT64_C(4060088592), // VMULv8i8 1891 UINT64_C(4088399232), // VMVNd 1892 UINT64_C(4088399296), // VMVNq 1893 UINT64_C(4068474928), // VMVNv2i32 1894 UINT64_C(4068476976), // VMVNv4i16 1895 UINT64_C(4068474992), // VMVNv4i32 1896 UINT64_C(4068477040), // VMVNv8i16 1897 UINT64_C(246483776), // VNEGD 1898 UINT64_C(246483264), // VNEGH 1899 UINT64_C(246483520), // VNEGS 1900 UINT64_C(4088989632), // VNEGf32q 1901 UINT64_C(4088989568), // VNEGfd 1902 UINT64_C(4088727424), // VNEGhd 1903 UINT64_C(4088727488), // VNEGhq 1904 UINT64_C(4088726400), // VNEGs16d 1905 UINT64_C(4088726464), // VNEGs16q 1906 UINT64_C(4088988544), // VNEGs32d 1907 UINT64_C(4088988608), // VNEGs32q 1908 UINT64_C(4088464256), // VNEGs8d 1909 UINT64_C(4088464320), // VNEGs8q 1910 UINT64_C(235932480), // VNMLAD 1911 UINT64_C(235931968), // VNMLAH 1912 UINT64_C(235932224), // VNMLAS 1913 UINT64_C(235932416), // VNMLSD 1914 UINT64_C(235931904), // VNMLSH 1915 UINT64_C(235932160), // VNMLSS 1916 UINT64_C(236981056), // VNMULD 1917 UINT64_C(236980544), // VNMULH 1918 UINT64_C(236980800), // VNMULS 1919 UINT64_C(4063232272), // VORNd 1920 UINT64_C(4063232336), // VORNq 1921 UINT64_C(4062183696), // VORRd 1922 UINT64_C(4068475152), // VORRiv2i32 1923 UINT64_C(4068477200), // VORRiv4i16 1924 UINT64_C(4068475216), // VORRiv4i32 1925 UINT64_C(4068477264), // VORRiv8i16 1926 UINT64_C(4062183760), // VORRq 1927 UINT64_C(4088399424), // VPADALsv16i8 1928 UINT64_C(4088923648), // VPADALsv2i32 1929 UINT64_C(4088661504), // VPADALsv4i16 1930 UINT64_C(4088923712), // VPADALsv4i32 1931 UINT64_C(4088661568), // VPADALsv8i16 1932 UINT64_C(4088399360), // VPADALsv8i8 1933 UINT64_C(4088399552), // VPADALuv16i8 1934 UINT64_C(4088923776), // VPADALuv2i32 1935 UINT64_C(4088661632), // VPADALuv4i16 1936 UINT64_C(4088923840), // VPADALuv4i32 1937 UINT64_C(4088661696), // VPADALuv8i16 1938 UINT64_C(4088399488), // VPADALuv8i8 1939 UINT64_C(4088398400), // VPADDLsv16i8 1940 UINT64_C(4088922624), // VPADDLsv2i32 1941 UINT64_C(4088660480), // VPADDLsv4i16 1942 UINT64_C(4088922688), // VPADDLsv4i32 1943 UINT64_C(4088660544), // VPADDLsv8i16 1944 UINT64_C(4088398336), // VPADDLsv8i8 1945 UINT64_C(4088398528), // VPADDLuv16i8 1946 UINT64_C(4088922752), // VPADDLuv2i32 1947 UINT64_C(4088660608), // VPADDLuv4i16 1948 UINT64_C(4088922816), // VPADDLuv4i32 1949 UINT64_C(4088660672), // VPADDLuv8i16 1950 UINT64_C(4088398464), // VPADDLuv8i8 1951 UINT64_C(4076866816), // VPADDf 1952 UINT64_C(4077915392), // VPADDh 1953 UINT64_C(4061137680), // VPADDi16 1954 UINT64_C(4062186256), // VPADDi32 1955 UINT64_C(4060089104), // VPADDi8 1956 UINT64_C(4076867328), // VPMAXf 1957 UINT64_C(4077915904), // VPMAXh 1958 UINT64_C(4061137408), // VPMAXs16 1959 UINT64_C(4062185984), // VPMAXs32 1960 UINT64_C(4060088832), // VPMAXs8 1961 UINT64_C(4077914624), // VPMAXu16 1962 UINT64_C(4078963200), // VPMAXu32 1963 UINT64_C(4076866048), // VPMAXu8 1964 UINT64_C(4078964480), // VPMINf 1965 UINT64_C(4080013056), // VPMINh 1966 UINT64_C(4061137424), // VPMINs16 1967 UINT64_C(4062186000), // VPMINs32 1968 UINT64_C(4060088848), // VPMINs8 1969 UINT64_C(4077914640), // VPMINu16 1970 UINT64_C(4078963216), // VPMINu32 1971 UINT64_C(4076866064), // VPMINu8 1972 UINT64_C(4088399680), // VQABSv16i8 1973 UINT64_C(4088923904), // VQABSv2i32 1974 UINT64_C(4088661760), // VQABSv4i16 1975 UINT64_C(4088923968), // VQABSv4i32 1976 UINT64_C(4088661824), // VQABSv8i16 1977 UINT64_C(4088399616), // VQABSv8i8 1978 UINT64_C(4060086352), // VQADDsv16i8 1979 UINT64_C(4063232016), // VQADDsv1i64 1980 UINT64_C(4062183440), // VQADDsv2i32 1981 UINT64_C(4063232080), // VQADDsv2i64 1982 UINT64_C(4061134864), // VQADDsv4i16 1983 UINT64_C(4062183504), // VQADDsv4i32 1984 UINT64_C(4061134928), // VQADDsv8i16 1985 UINT64_C(4060086288), // VQADDsv8i8 1986 UINT64_C(4076863568), // VQADDuv16i8 1987 UINT64_C(4080009232), // VQADDuv1i64 1988 UINT64_C(4078960656), // VQADDuv2i32 1989 UINT64_C(4080009296), // VQADDuv2i64 1990 UINT64_C(4077912080), // VQADDuv4i16 1991 UINT64_C(4078960720), // VQADDuv4i32 1992 UINT64_C(4077912144), // VQADDuv8i16 1993 UINT64_C(4076863504), // VQADDuv8i8 1994 UINT64_C(4070572864), // VQDMLALslv2i32 1995 UINT64_C(4069524288), // VQDMLALslv4i16 1996 UINT64_C(4070574336), // VQDMLALv2i64 1997 UINT64_C(4069525760), // VQDMLALv4i32 1998 UINT64_C(4070573888), // VQDMLSLslv2i32 1999 UINT64_C(4069525312), // VQDMLSLslv4i16 2000 UINT64_C(4070574848), // VQDMLSLv2i64 2001 UINT64_C(4069526272), // VQDMLSLv4i32 2002 UINT64_C(4070575168), // VQDMULHslv2i32 2003 UINT64_C(4069526592), // VQDMULHslv4i16 2004 UINT64_C(4087352384), // VQDMULHslv4i32 2005 UINT64_C(4086303808), // VQDMULHslv8i16 2006 UINT64_C(4062186240), // VQDMULHv2i32 2007 UINT64_C(4061137664), // VQDMULHv4i16 2008 UINT64_C(4062186304), // VQDMULHv4i32 2009 UINT64_C(4061137728), // VQDMULHv8i16 2010 UINT64_C(4070574912), // VQDMULLslv2i32 2011 UINT64_C(4069526336), // VQDMULLslv4i16 2012 UINT64_C(4070575360), // VQDMULLv2i64 2013 UINT64_C(4069526784), // VQDMULLv4i32 2014 UINT64_C(4089053760), // VQMOVNsuv2i32 2015 UINT64_C(4088791616), // VQMOVNsuv4i16 2016 UINT64_C(4088529472), // VQMOVNsuv8i8 2017 UINT64_C(4089053824), // VQMOVNsv2i32 2018 UINT64_C(4088791680), // VQMOVNsv4i16 2019 UINT64_C(4088529536), // VQMOVNsv8i8 2020 UINT64_C(4089053888), // VQMOVNuv2i32 2021 UINT64_C(4088791744), // VQMOVNuv4i16 2022 UINT64_C(4088529600), // VQMOVNuv8i8 2023 UINT64_C(4088399808), // VQNEGv16i8 2024 UINT64_C(4088924032), // VQNEGv2i32 2025 UINT64_C(4088661888), // VQNEGv4i16 2026 UINT64_C(4088924096), // VQNEGv4i32 2027 UINT64_C(4088661952), // VQNEGv8i16 2028 UINT64_C(4088399744), // VQNEGv8i8 2029 UINT64_C(4070575680), // VQRDMLAHslv2i32 2030 UINT64_C(4069527104), // VQRDMLAHslv4i16 2031 UINT64_C(4087352896), // VQRDMLAHslv4i32 2032 UINT64_C(4086304320), // VQRDMLAHslv8i16 2033 UINT64_C(4078963472), // VQRDMLAHv2i32 2034 UINT64_C(4077914896), // VQRDMLAHv4i16 2035 UINT64_C(4078963536), // VQRDMLAHv4i32 2036 UINT64_C(4077914960), // VQRDMLAHv8i16 2037 UINT64_C(4070575936), // VQRDMLSHslv2i32 2038 UINT64_C(4069527360), // VQRDMLSHslv4i16 2039 UINT64_C(4087353152), // VQRDMLSHslv4i32 2040 UINT64_C(4086304576), // VQRDMLSHslv8i16 2041 UINT64_C(4078963728), // VQRDMLSHv2i32 2042 UINT64_C(4077915152), // VQRDMLSHv4i16 2043 UINT64_C(4078963792), // VQRDMLSHv4i32 2044 UINT64_C(4077915216), // VQRDMLSHv8i16 2045 UINT64_C(4070575424), // VQRDMULHslv2i32 2046 UINT64_C(4069526848), // VQRDMULHslv4i16 2047 UINT64_C(4087352640), // VQRDMULHslv4i32 2048 UINT64_C(4086304064), // VQRDMULHslv8i16 2049 UINT64_C(4078963456), // VQRDMULHv2i32 2050 UINT64_C(4077914880), // VQRDMULHv4i16 2051 UINT64_C(4078963520), // VQRDMULHv4i32 2052 UINT64_C(4077914944), // VQRDMULHv8i16 2053 UINT64_C(4060087632), // VQRSHLsv16i8 2054 UINT64_C(4063233296), // VQRSHLsv1i64 2055 UINT64_C(4062184720), // VQRSHLsv2i32 2056 UINT64_C(4063233360), // VQRSHLsv2i64 2057 UINT64_C(4061136144), // VQRSHLsv4i16 2058 UINT64_C(4062184784), // VQRSHLsv4i32 2059 UINT64_C(4061136208), // VQRSHLsv8i16 2060 UINT64_C(4060087568), // VQRSHLsv8i8 2061 UINT64_C(4076864848), // VQRSHLuv16i8 2062 UINT64_C(4080010512), // VQRSHLuv1i64 2063 UINT64_C(4078961936), // VQRSHLuv2i32 2064 UINT64_C(4080010576), // VQRSHLuv2i64 2065 UINT64_C(4077913360), // VQRSHLuv4i16 2066 UINT64_C(4078962000), // VQRSHLuv4i32 2067 UINT64_C(4077913424), // VQRSHLuv8i16 2068 UINT64_C(4076864784), // VQRSHLuv8i8 2069 UINT64_C(4070574416), // VQRSHRNsv2i32 2070 UINT64_C(4069525840), // VQRSHRNsv4i16 2071 UINT64_C(4069001552), // VQRSHRNsv8i8 2072 UINT64_C(4087351632), // VQRSHRNuv2i32 2073 UINT64_C(4086303056), // VQRSHRNuv4i16 2074 UINT64_C(4085778768), // VQRSHRNuv8i8 2075 UINT64_C(4087351376), // VQRSHRUNv2i32 2076 UINT64_C(4086302800), // VQRSHRUNv4i16 2077 UINT64_C(4085778512), // VQRSHRUNv8i8 2078 UINT64_C(4069001040), // VQSHLsiv16i8 2079 UINT64_C(4068476816), // VQSHLsiv1i64 2080 UINT64_C(4070573840), // VQSHLsiv2i32 2081 UINT64_C(4068476880), // VQSHLsiv2i64 2082 UINT64_C(4069525264), // VQSHLsiv4i16 2083 UINT64_C(4070573904), // VQSHLsiv4i32 2084 UINT64_C(4069525328), // VQSHLsiv8i16 2085 UINT64_C(4069000976), // VQSHLsiv8i8 2086 UINT64_C(4085778000), // VQSHLsuv16i8 2087 UINT64_C(4085253776), // VQSHLsuv1i64 2088 UINT64_C(4087350800), // VQSHLsuv2i32 2089 UINT64_C(4085253840), // VQSHLsuv2i64 2090 UINT64_C(4086302224), // VQSHLsuv4i16 2091 UINT64_C(4087350864), // VQSHLsuv4i32 2092 UINT64_C(4086302288), // VQSHLsuv8i16 2093 UINT64_C(4085777936), // VQSHLsuv8i8 2094 UINT64_C(4060087376), // VQSHLsv16i8 2095 UINT64_C(4063233040), // VQSHLsv1i64 2096 UINT64_C(4062184464), // VQSHLsv2i32 2097 UINT64_C(4063233104), // VQSHLsv2i64 2098 UINT64_C(4061135888), // VQSHLsv4i16 2099 UINT64_C(4062184528), // VQSHLsv4i32 2100 UINT64_C(4061135952), // VQSHLsv8i16 2101 UINT64_C(4060087312), // VQSHLsv8i8 2102 UINT64_C(4085778256), // VQSHLuiv16i8 2103 UINT64_C(4085254032), // VQSHLuiv1i64 2104 UINT64_C(4087351056), // VQSHLuiv2i32 2105 UINT64_C(4085254096), // VQSHLuiv2i64 2106 UINT64_C(4086302480), // VQSHLuiv4i16 2107 UINT64_C(4087351120), // VQSHLuiv4i32 2108 UINT64_C(4086302544), // VQSHLuiv8i16 2109 UINT64_C(4085778192), // VQSHLuiv8i8 2110 UINT64_C(4076864592), // VQSHLuv16i8 2111 UINT64_C(4080010256), // VQSHLuv1i64 2112 UINT64_C(4078961680), // VQSHLuv2i32 2113 UINT64_C(4080010320), // VQSHLuv2i64 2114 UINT64_C(4077913104), // VQSHLuv4i16 2115 UINT64_C(4078961744), // VQSHLuv4i32 2116 UINT64_C(4077913168), // VQSHLuv8i16 2117 UINT64_C(4076864528), // VQSHLuv8i8 2118 UINT64_C(4070574352), // VQSHRNsv2i32 2119 UINT64_C(4069525776), // VQSHRNsv4i16 2120 UINT64_C(4069001488), // VQSHRNsv8i8 2121 UINT64_C(4087351568), // VQSHRNuv2i32 2122 UINT64_C(4086302992), // VQSHRNuv4i16 2123 UINT64_C(4085778704), // VQSHRNuv8i8 2124 UINT64_C(4087351312), // VQSHRUNv2i32 2125 UINT64_C(4086302736), // VQSHRUNv4i16 2126 UINT64_C(4085778448), // VQSHRUNv8i8 2127 UINT64_C(4060086864), // VQSUBsv16i8 2128 UINT64_C(4063232528), // VQSUBsv1i64 2129 UINT64_C(4062183952), // VQSUBsv2i32 2130 UINT64_C(4063232592), // VQSUBsv2i64 2131 UINT64_C(4061135376), // VQSUBsv4i16 2132 UINT64_C(4062184016), // VQSUBsv4i32 2133 UINT64_C(4061135440), // VQSUBsv8i16 2134 UINT64_C(4060086800), // VQSUBsv8i8 2135 UINT64_C(4076864080), // VQSUBuv16i8 2136 UINT64_C(4080009744), // VQSUBuv1i64 2137 UINT64_C(4078961168), // VQSUBuv2i32 2138 UINT64_C(4080009808), // VQSUBuv2i64 2139 UINT64_C(4077912592), // VQSUBuv4i16 2140 UINT64_C(4078961232), // VQSUBuv4i32 2141 UINT64_C(4077912656), // VQSUBuv8i16 2142 UINT64_C(4076864016), // VQSUBuv8i8 2143 UINT64_C(4087350272), // VRADDHNv2i32 2144 UINT64_C(4086301696), // VRADDHNv4i16 2145 UINT64_C(4085253120), // VRADDHNv8i8 2146 UINT64_C(4089119744), // VRECPEd 2147 UINT64_C(4089120000), // VRECPEfd 2148 UINT64_C(4089120064), // VRECPEfq 2149 UINT64_C(4088857856), // VRECPEhd 2150 UINT64_C(4088857920), // VRECPEhq 2151 UINT64_C(4089119808), // VRECPEq 2152 UINT64_C(4060090128), // VRECPSfd 2153 UINT64_C(4060090192), // VRECPSfq 2154 UINT64_C(4061138704), // VRECPShd 2155 UINT64_C(4061138768), // VRECPShq 2156 UINT64_C(4088398080), // VREV16d8 2157 UINT64_C(4088398144), // VREV16q8 2158 UINT64_C(4088660096), // VREV32d16 2159 UINT64_C(4088397952), // VREV32d8 2160 UINT64_C(4088660160), // VREV32q16 2161 UINT64_C(4088398016), // VREV32q8 2162 UINT64_C(4088659968), // VREV64d16 2163 UINT64_C(4088922112), // VREV64d32 2164 UINT64_C(4088397824), // VREV64d8 2165 UINT64_C(4088660032), // VREV64q16 2166 UINT64_C(4088922176), // VREV64q32 2167 UINT64_C(4088397888), // VREV64q8 2168 UINT64_C(4060086592), // VRHADDsv16i8 2169 UINT64_C(4062183680), // VRHADDsv2i32 2170 UINT64_C(4061135104), // VRHADDsv4i16 2171 UINT64_C(4062183744), // VRHADDsv4i32 2172 UINT64_C(4061135168), // VRHADDsv8i16 2173 UINT64_C(4060086528), // VRHADDsv8i8 2174 UINT64_C(4076863808), // VRHADDuv16i8 2175 UINT64_C(4078960896), // VRHADDuv2i32 2176 UINT64_C(4077912320), // VRHADDuv4i16 2177 UINT64_C(4078960960), // VRHADDuv4i32 2178 UINT64_C(4077912384), // VRHADDuv8i16 2179 UINT64_C(4076863744), // VRHADDuv8i8 2180 UINT64_C(4273474368), // VRINTAD 2181 UINT64_C(4273473856), // VRINTAH 2182 UINT64_C(4089054464), // VRINTANDf 2183 UINT64_C(4088792320), // VRINTANDh 2184 UINT64_C(4089054528), // VRINTANQf 2185 UINT64_C(4088792384), // VRINTANQh 2186 UINT64_C(4273474112), // VRINTAS 2187 UINT64_C(4273670976), // VRINTMD 2188 UINT64_C(4273670464), // VRINTMH 2189 UINT64_C(4089054848), // VRINTMNDf 2190 UINT64_C(4088792704), // VRINTMNDh 2191 UINT64_C(4089054912), // VRINTMNQf 2192 UINT64_C(4088792768), // VRINTMNQh 2193 UINT64_C(4273670720), // VRINTMS 2194 UINT64_C(4273539904), // VRINTND 2195 UINT64_C(4273539392), // VRINTNH 2196 UINT64_C(4089054208), // VRINTNNDf 2197 UINT64_C(4088792064), // VRINTNNDh 2198 UINT64_C(4089054272), // VRINTNNQf 2199 UINT64_C(4088792128), // VRINTNNQh 2200 UINT64_C(4273539648), // VRINTNS 2201 UINT64_C(4273605440), // VRINTPD 2202 UINT64_C(4273604928), // VRINTPH 2203 UINT64_C(4089055104), // VRINTPNDf 2204 UINT64_C(4088792960), // VRINTPNDh 2205 UINT64_C(4089055168), // VRINTPNQf 2206 UINT64_C(4088793024), // VRINTPNQh 2207 UINT64_C(4273605184), // VRINTPS 2208 UINT64_C(246811456), // VRINTRD 2209 UINT64_C(246810944), // VRINTRH 2210 UINT64_C(246811200), // VRINTRS 2211 UINT64_C(246876992), // VRINTXD 2212 UINT64_C(246876480), // VRINTXH 2213 UINT64_C(4089054336), // VRINTXNDf 2214 UINT64_C(4088792192), // VRINTXNDh 2215 UINT64_C(4089054400), // VRINTXNQf 2216 UINT64_C(4088792256), // VRINTXNQh 2217 UINT64_C(246876736), // VRINTXS 2218 UINT64_C(246811584), // VRINTZD 2219 UINT64_C(246811072), // VRINTZH 2220 UINT64_C(4089054592), // VRINTZNDf 2221 UINT64_C(4088792448), // VRINTZNDh 2222 UINT64_C(4089054656), // VRINTZNQf 2223 UINT64_C(4088792512), // VRINTZNQh 2224 UINT64_C(246811328), // VRINTZS 2225 UINT64_C(4060087616), // VRSHLsv16i8 2226 UINT64_C(4063233280), // VRSHLsv1i64 2227 UINT64_C(4062184704), // VRSHLsv2i32 2228 UINT64_C(4063233344), // VRSHLsv2i64 2229 UINT64_C(4061136128), // VRSHLsv4i16 2230 UINT64_C(4062184768), // VRSHLsv4i32 2231 UINT64_C(4061136192), // VRSHLsv8i16 2232 UINT64_C(4060087552), // VRSHLsv8i8 2233 UINT64_C(4076864832), // VRSHLuv16i8 2234 UINT64_C(4080010496), // VRSHLuv1i64 2235 UINT64_C(4078961920), // VRSHLuv2i32 2236 UINT64_C(4080010560), // VRSHLuv2i64 2237 UINT64_C(4077913344), // VRSHLuv4i16 2238 UINT64_C(4078961984), // VRSHLuv4i32 2239 UINT64_C(4077913408), // VRSHLuv8i16 2240 UINT64_C(4076864768), // VRSHLuv8i8 2241 UINT64_C(4070574160), // VRSHRNv2i32 2242 UINT64_C(4069525584), // VRSHRNv4i16 2243 UINT64_C(4069001296), // VRSHRNv8i8 2244 UINT64_C(4068999760), // VRSHRsv16i8 2245 UINT64_C(4068475536), // VRSHRsv1i64 2246 UINT64_C(4070572560), // VRSHRsv2i32 2247 UINT64_C(4068475600), // VRSHRsv2i64 2248 UINT64_C(4069523984), // VRSHRsv4i16 2249 UINT64_C(4070572624), // VRSHRsv4i32 2250 UINT64_C(4069524048), // VRSHRsv8i16 2251 UINT64_C(4068999696), // VRSHRsv8i8 2252 UINT64_C(4085776976), // VRSHRuv16i8 2253 UINT64_C(4085252752), // VRSHRuv1i64 2254 UINT64_C(4087349776), // VRSHRuv2i32 2255 UINT64_C(4085252816), // VRSHRuv2i64 2256 UINT64_C(4086301200), // VRSHRuv4i16 2257 UINT64_C(4087349840), // VRSHRuv4i32 2258 UINT64_C(4086301264), // VRSHRuv8i16 2259 UINT64_C(4085776912), // VRSHRuv8i8 2260 UINT64_C(4089119872), // VRSQRTEd 2261 UINT64_C(4089120128), // VRSQRTEfd 2262 UINT64_C(4089120192), // VRSQRTEfq 2263 UINT64_C(4088857984), // VRSQRTEhd 2264 UINT64_C(4088858048), // VRSQRTEhq 2265 UINT64_C(4089119936), // VRSQRTEq 2266 UINT64_C(4062187280), // VRSQRTSfd 2267 UINT64_C(4062187344), // VRSQRTSfq 2268 UINT64_C(4063235856), // VRSQRTShd 2269 UINT64_C(4063235920), // VRSQRTShq 2270 UINT64_C(4069000016), // VRSRAsv16i8 2271 UINT64_C(4068475792), // VRSRAsv1i64 2272 UINT64_C(4070572816), // VRSRAsv2i32 2273 UINT64_C(4068475856), // VRSRAsv2i64 2274 UINT64_C(4069524240), // VRSRAsv4i16 2275 UINT64_C(4070572880), // VRSRAsv4i32 2276 UINT64_C(4069524304), // VRSRAsv8i16 2277 UINT64_C(4068999952), // VRSRAsv8i8 2278 UINT64_C(4085777232), // VRSRAuv16i8 2279 UINT64_C(4085253008), // VRSRAuv1i64 2280 UINT64_C(4087350032), // VRSRAuv2i32 2281 UINT64_C(4085253072), // VRSRAuv2i64 2282 UINT64_C(4086301456), // VRSRAuv4i16 2283 UINT64_C(4087350096), // VRSRAuv4i32 2284 UINT64_C(4086301520), // VRSRAuv8i16 2285 UINT64_C(4085777168), // VRSRAuv8i8 2286 UINT64_C(4087350784), // VRSUBHNv2i32 2287 UINT64_C(4086302208), // VRSUBHNv4i16 2288 UINT64_C(4085253632), // VRSUBHNv8i8 2289 UINT64_C(4229958912), // VSDOTD 2290 UINT64_C(4263513344), // VSDOTDI 2291 UINT64_C(4229958976), // VSDOTQ 2292 UINT64_C(4263513408), // VSDOTQI 2293 UINT64_C(4261415680), // VSELEQD 2294 UINT64_C(4261415168), // VSELEQH 2295 UINT64_C(4261415424), // VSELEQS 2296 UINT64_C(4263512832), // VSELGED 2297 UINT64_C(4263512320), // VSELGEH 2298 UINT64_C(4263512576), // VSELGES 2299 UINT64_C(4264561408), // VSELGTD 2300 UINT64_C(4264560896), // VSELGTH 2301 UINT64_C(4264561152), // VSELGTS 2302 UINT64_C(4262464256), // VSELVSD 2303 UINT64_C(4262463744), // VSELVSH 2304 UINT64_C(4262464000), // VSELVSS 2305 UINT64_C(234883888), // VSETLNi16 2306 UINT64_C(234883856), // VSETLNi32 2307 UINT64_C(239078160), // VSETLNi8 2308 UINT64_C(4088791808), // VSHLLi16 2309 UINT64_C(4089053952), // VSHLLi32 2310 UINT64_C(4088529664), // VSHLLi8 2311 UINT64_C(4070574608), // VSHLLsv2i64 2312 UINT64_C(4069526032), // VSHLLsv4i32 2313 UINT64_C(4069001744), // VSHLLsv8i16 2314 UINT64_C(4087351824), // VSHLLuv2i64 2315 UINT64_C(4086303248), // VSHLLuv4i32 2316 UINT64_C(4085778960), // VSHLLuv8i16 2317 UINT64_C(4069000528), // VSHLiv16i8 2318 UINT64_C(4068476304), // VSHLiv1i64 2319 UINT64_C(4070573328), // VSHLiv2i32 2320 UINT64_C(4068476368), // VSHLiv2i64 2321 UINT64_C(4069524752), // VSHLiv4i16 2322 UINT64_C(4070573392), // VSHLiv4i32 2323 UINT64_C(4069524816), // VSHLiv8i16 2324 UINT64_C(4069000464), // VSHLiv8i8 2325 UINT64_C(4060087360), // VSHLsv16i8 2326 UINT64_C(4063233024), // VSHLsv1i64 2327 UINT64_C(4062184448), // VSHLsv2i32 2328 UINT64_C(4063233088), // VSHLsv2i64 2329 UINT64_C(4061135872), // VSHLsv4i16 2330 UINT64_C(4062184512), // VSHLsv4i32 2331 UINT64_C(4061135936), // VSHLsv8i16 2332 UINT64_C(4060087296), // VSHLsv8i8 2333 UINT64_C(4076864576), // VSHLuv16i8 2334 UINT64_C(4080010240), // VSHLuv1i64 2335 UINT64_C(4078961664), // VSHLuv2i32 2336 UINT64_C(4080010304), // VSHLuv2i64 2337 UINT64_C(4077913088), // VSHLuv4i16 2338 UINT64_C(4078961728), // VSHLuv4i32 2339 UINT64_C(4077913152), // VSHLuv8i16 2340 UINT64_C(4076864512), // VSHLuv8i8 2341 UINT64_C(4070574096), // VSHRNv2i32 2342 UINT64_C(4069525520), // VSHRNv4i16 2343 UINT64_C(4069001232), // VSHRNv8i8 2344 UINT64_C(4068999248), // VSHRsv16i8 2345 UINT64_C(4068475024), // VSHRsv1i64 2346 UINT64_C(4070572048), // VSHRsv2i32 2347 UINT64_C(4068475088), // VSHRsv2i64 2348 UINT64_C(4069523472), // VSHRsv4i16 2349 UINT64_C(4070572112), // VSHRsv4i32 2350 UINT64_C(4069523536), // VSHRsv8i16 2351 UINT64_C(4068999184), // VSHRsv8i8 2352 UINT64_C(4085776464), // VSHRuv16i8 2353 UINT64_C(4085252240), // VSHRuv1i64 2354 UINT64_C(4087349264), // VSHRuv2i32 2355 UINT64_C(4085252304), // VSHRuv2i64 2356 UINT64_C(4086300688), // VSHRuv4i16 2357 UINT64_C(4087349328), // VSHRuv4i32 2358 UINT64_C(4086300752), // VSHRuv8i16 2359 UINT64_C(4085776400), // VSHRuv8i8 2360 UINT64_C(247073600), // VSHTOD 2361 UINT64_C(247073088), // VSHTOH 2362 UINT64_C(247073344), // VSHTOS 2363 UINT64_C(246942656), // VSITOD 2364 UINT64_C(246942144), // VSITOH 2365 UINT64_C(246942400), // VSITOS 2366 UINT64_C(4085777744), // VSLIv16i8 2367 UINT64_C(4085253520), // VSLIv1i64 2368 UINT64_C(4087350544), // VSLIv2i32 2369 UINT64_C(4085253584), // VSLIv2i64 2370 UINT64_C(4086301968), // VSLIv4i16 2371 UINT64_C(4087350608), // VSLIv4i32 2372 UINT64_C(4086302032), // VSLIv8i16 2373 UINT64_C(4085777680), // VSLIv8i8 2374 UINT64_C(247073728), // VSLTOD 2375 UINT64_C(247073216), // VSLTOH 2376 UINT64_C(247073472), // VSLTOS 2377 UINT64_C(246483904), // VSQRTD 2378 UINT64_C(246483392), // VSQRTH 2379 UINT64_C(246483648), // VSQRTS 2380 UINT64_C(4068999504), // VSRAsv16i8 2381 UINT64_C(4068475280), // VSRAsv1i64 2382 UINT64_C(4070572304), // VSRAsv2i32 2383 UINT64_C(4068475344), // VSRAsv2i64 2384 UINT64_C(4069523728), // VSRAsv4i16 2385 UINT64_C(4070572368), // VSRAsv4i32 2386 UINT64_C(4069523792), // VSRAsv8i16 2387 UINT64_C(4068999440), // VSRAsv8i8 2388 UINT64_C(4085776720), // VSRAuv16i8 2389 UINT64_C(4085252496), // VSRAuv1i64 2390 UINT64_C(4087349520), // VSRAuv2i32 2391 UINT64_C(4085252560), // VSRAuv2i64 2392 UINT64_C(4086300944), // VSRAuv4i16 2393 UINT64_C(4087349584), // VSRAuv4i32 2394 UINT64_C(4086301008), // VSRAuv8i16 2395 UINT64_C(4085776656), // VSRAuv8i8 2396 UINT64_C(4085777488), // VSRIv16i8 2397 UINT64_C(4085253264), // VSRIv1i64 2398 UINT64_C(4087350288), // VSRIv2i32 2399 UINT64_C(4085253328), // VSRIv2i64 2400 UINT64_C(4086301712), // VSRIv4i16 2401 UINT64_C(4087350352), // VSRIv4i32 2402 UINT64_C(4086301776), // VSRIv8i16 2403 UINT64_C(4085777424), // VSRIv8i8 2404 UINT64_C(4102030351), // VST1LNd16 2405 UINT64_C(4102030336), // VST1LNd16_UPD 2406 UINT64_C(4102031375), // VST1LNd32 2407 UINT64_C(4102031360), // VST1LNd32_UPD 2408 UINT64_C(4102029327), // VST1LNd8 2409 UINT64_C(4102029312), // VST1LNd8_UPD 2410 UINT64_C(0), // VST1LNq16Pseudo 2411 UINT64_C(0), // VST1LNq16Pseudo_UPD 2412 UINT64_C(0), // VST1LNq32Pseudo 2413 UINT64_C(0), // VST1LNq32Pseudo_UPD 2414 UINT64_C(0), // VST1LNq8Pseudo 2415 UINT64_C(0), // VST1LNq8Pseudo_UPD 2416 UINT64_C(4093642575), // VST1d16 2417 UINT64_C(4093641295), // VST1d16Q 2418 UINT64_C(0), // VST1d16QPseudo 2419 UINT64_C(4093641293), // VST1d16Qwb_fixed 2420 UINT64_C(4093641280), // VST1d16Qwb_register 2421 UINT64_C(4093642319), // VST1d16T 2422 UINT64_C(0), // VST1d16TPseudo 2423 UINT64_C(4093642317), // VST1d16Twb_fixed 2424 UINT64_C(4093642304), // VST1d16Twb_register 2425 UINT64_C(4093642573), // VST1d16wb_fixed 2426 UINT64_C(4093642560), // VST1d16wb_register 2427 UINT64_C(4093642639), // VST1d32 2428 UINT64_C(4093641359), // VST1d32Q 2429 UINT64_C(0), // VST1d32QPseudo 2430 UINT64_C(4093641357), // VST1d32Qwb_fixed 2431 UINT64_C(4093641344), // VST1d32Qwb_register 2432 UINT64_C(4093642383), // VST1d32T 2433 UINT64_C(0), // VST1d32TPseudo 2434 UINT64_C(4093642381), // VST1d32Twb_fixed 2435 UINT64_C(4093642368), // VST1d32Twb_register 2436 UINT64_C(4093642637), // VST1d32wb_fixed 2437 UINT64_C(4093642624), // VST1d32wb_register 2438 UINT64_C(4093642703), // VST1d64 2439 UINT64_C(4093641423), // VST1d64Q 2440 UINT64_C(0), // VST1d64QPseudo 2441 UINT64_C(0), // VST1d64QPseudoWB_fixed 2442 UINT64_C(0), // VST1d64QPseudoWB_register 2443 UINT64_C(4093641421), // VST1d64Qwb_fixed 2444 UINT64_C(4093641408), // VST1d64Qwb_register 2445 UINT64_C(4093642447), // VST1d64T 2446 UINT64_C(0), // VST1d64TPseudo 2447 UINT64_C(0), // VST1d64TPseudoWB_fixed 2448 UINT64_C(0), // VST1d64TPseudoWB_register 2449 UINT64_C(4093642445), // VST1d64Twb_fixed 2450 UINT64_C(4093642432), // VST1d64Twb_register 2451 UINT64_C(4093642701), // VST1d64wb_fixed 2452 UINT64_C(4093642688), // VST1d64wb_register 2453 UINT64_C(4093642511), // VST1d8 2454 UINT64_C(4093641231), // VST1d8Q 2455 UINT64_C(0), // VST1d8QPseudo 2456 UINT64_C(4093641229), // VST1d8Qwb_fixed 2457 UINT64_C(4093641216), // VST1d8Qwb_register 2458 UINT64_C(4093642255), // VST1d8T 2459 UINT64_C(0), // VST1d8TPseudo 2460 UINT64_C(4093642253), // VST1d8Twb_fixed 2461 UINT64_C(4093642240), // VST1d8Twb_register 2462 UINT64_C(4093642509), // VST1d8wb_fixed 2463 UINT64_C(4093642496), // VST1d8wb_register 2464 UINT64_C(4093643343), // VST1q16 2465 UINT64_C(0), // VST1q16HighQPseudo 2466 UINT64_C(0), // VST1q16HighTPseudo 2467 UINT64_C(0), // VST1q16LowQPseudo_UPD 2468 UINT64_C(0), // VST1q16LowTPseudo_UPD 2469 UINT64_C(4093643341), // VST1q16wb_fixed 2470 UINT64_C(4093643328), // VST1q16wb_register 2471 UINT64_C(4093643407), // VST1q32 2472 UINT64_C(0), // VST1q32HighQPseudo 2473 UINT64_C(0), // VST1q32HighTPseudo 2474 UINT64_C(0), // VST1q32LowQPseudo_UPD 2475 UINT64_C(0), // VST1q32LowTPseudo_UPD 2476 UINT64_C(4093643405), // VST1q32wb_fixed 2477 UINT64_C(4093643392), // VST1q32wb_register 2478 UINT64_C(4093643471), // VST1q64 2479 UINT64_C(0), // VST1q64HighQPseudo 2480 UINT64_C(0), // VST1q64HighTPseudo 2481 UINT64_C(0), // VST1q64LowQPseudo_UPD 2482 UINT64_C(0), // VST1q64LowTPseudo_UPD 2483 UINT64_C(4093643469), // VST1q64wb_fixed 2484 UINT64_C(4093643456), // VST1q64wb_register 2485 UINT64_C(4093643279), // VST1q8 2486 UINT64_C(0), // VST1q8HighQPseudo 2487 UINT64_C(0), // VST1q8HighTPseudo 2488 UINT64_C(0), // VST1q8LowQPseudo_UPD 2489 UINT64_C(0), // VST1q8LowTPseudo_UPD 2490 UINT64_C(4093643277), // VST1q8wb_fixed 2491 UINT64_C(4093643264), // VST1q8wb_register 2492 UINT64_C(4102030607), // VST2LNd16 2493 UINT64_C(0), // VST2LNd16Pseudo 2494 UINT64_C(0), // VST2LNd16Pseudo_UPD 2495 UINT64_C(4102030592), // VST2LNd16_UPD 2496 UINT64_C(4102031631), // VST2LNd32 2497 UINT64_C(0), // VST2LNd32Pseudo 2498 UINT64_C(0), // VST2LNd32Pseudo_UPD 2499 UINT64_C(4102031616), // VST2LNd32_UPD 2500 UINT64_C(4102029583), // VST2LNd8 2501 UINT64_C(0), // VST2LNd8Pseudo 2502 UINT64_C(0), // VST2LNd8Pseudo_UPD 2503 UINT64_C(4102029568), // VST2LNd8_UPD 2504 UINT64_C(4102030639), // VST2LNq16 2505 UINT64_C(0), // VST2LNq16Pseudo 2506 UINT64_C(0), // VST2LNq16Pseudo_UPD 2507 UINT64_C(4102030624), // VST2LNq16_UPD 2508 UINT64_C(4102031695), // VST2LNq32 2509 UINT64_C(0), // VST2LNq32Pseudo 2510 UINT64_C(0), // VST2LNq32Pseudo_UPD 2511 UINT64_C(4102031680), // VST2LNq32_UPD 2512 UINT64_C(4093643087), // VST2b16 2513 UINT64_C(4093643085), // VST2b16wb_fixed 2514 UINT64_C(4093643072), // VST2b16wb_register 2515 UINT64_C(4093643151), // VST2b32 2516 UINT64_C(4093643149), // VST2b32wb_fixed 2517 UINT64_C(4093643136), // VST2b32wb_register 2518 UINT64_C(4093643023), // VST2b8 2519 UINT64_C(4093643021), // VST2b8wb_fixed 2520 UINT64_C(4093643008), // VST2b8wb_register 2521 UINT64_C(4093642831), // VST2d16 2522 UINT64_C(4093642829), // VST2d16wb_fixed 2523 UINT64_C(4093642816), // VST2d16wb_register 2524 UINT64_C(4093642895), // VST2d32 2525 UINT64_C(4093642893), // VST2d32wb_fixed 2526 UINT64_C(4093642880), // VST2d32wb_register 2527 UINT64_C(4093642767), // VST2d8 2528 UINT64_C(4093642765), // VST2d8wb_fixed 2529 UINT64_C(4093642752), // VST2d8wb_register 2530 UINT64_C(4093641551), // VST2q16 2531 UINT64_C(0), // VST2q16Pseudo 2532 UINT64_C(0), // VST2q16PseudoWB_fixed 2533 UINT64_C(0), // VST2q16PseudoWB_register 2534 UINT64_C(4093641549), // VST2q16wb_fixed 2535 UINT64_C(4093641536), // VST2q16wb_register 2536 UINT64_C(4093641615), // VST2q32 2537 UINT64_C(0), // VST2q32Pseudo 2538 UINT64_C(0), // VST2q32PseudoWB_fixed 2539 UINT64_C(0), // VST2q32PseudoWB_register 2540 UINT64_C(4093641613), // VST2q32wb_fixed 2541 UINT64_C(4093641600), // VST2q32wb_register 2542 UINT64_C(4093641487), // VST2q8 2543 UINT64_C(0), // VST2q8Pseudo 2544 UINT64_C(0), // VST2q8PseudoWB_fixed 2545 UINT64_C(0), // VST2q8PseudoWB_register 2546 UINT64_C(4093641485), // VST2q8wb_fixed 2547 UINT64_C(4093641472), // VST2q8wb_register 2548 UINT64_C(4102030863), // VST3LNd16 2549 UINT64_C(0), // VST3LNd16Pseudo 2550 UINT64_C(0), // VST3LNd16Pseudo_UPD 2551 UINT64_C(4102030848), // VST3LNd16_UPD 2552 UINT64_C(4102031887), // VST3LNd32 2553 UINT64_C(0), // VST3LNd32Pseudo 2554 UINT64_C(0), // VST3LNd32Pseudo_UPD 2555 UINT64_C(4102031872), // VST3LNd32_UPD 2556 UINT64_C(4102029839), // VST3LNd8 2557 UINT64_C(0), // VST3LNd8Pseudo 2558 UINT64_C(0), // VST3LNd8Pseudo_UPD 2559 UINT64_C(4102029824), // VST3LNd8_UPD 2560 UINT64_C(4102030895), // VST3LNq16 2561 UINT64_C(0), // VST3LNq16Pseudo 2562 UINT64_C(0), // VST3LNq16Pseudo_UPD 2563 UINT64_C(4102030880), // VST3LNq16_UPD 2564 UINT64_C(4102031951), // VST3LNq32 2565 UINT64_C(0), // VST3LNq32Pseudo 2566 UINT64_C(0), // VST3LNq32Pseudo_UPD 2567 UINT64_C(4102031936), // VST3LNq32_UPD 2568 UINT64_C(4093641807), // VST3d16 2569 UINT64_C(0), // VST3d16Pseudo 2570 UINT64_C(0), // VST3d16Pseudo_UPD 2571 UINT64_C(4093641792), // VST3d16_UPD 2572 UINT64_C(4093641871), // VST3d32 2573 UINT64_C(0), // VST3d32Pseudo 2574 UINT64_C(0), // VST3d32Pseudo_UPD 2575 UINT64_C(4093641856), // VST3d32_UPD 2576 UINT64_C(4093641743), // VST3d8 2577 UINT64_C(0), // VST3d8Pseudo 2578 UINT64_C(0), // VST3d8Pseudo_UPD 2579 UINT64_C(4093641728), // VST3d8_UPD 2580 UINT64_C(4093642063), // VST3q16 2581 UINT64_C(0), // VST3q16Pseudo_UPD 2582 UINT64_C(4093642048), // VST3q16_UPD 2583 UINT64_C(0), // VST3q16oddPseudo 2584 UINT64_C(0), // VST3q16oddPseudo_UPD 2585 UINT64_C(4093642127), // VST3q32 2586 UINT64_C(0), // VST3q32Pseudo_UPD 2587 UINT64_C(4093642112), // VST3q32_UPD 2588 UINT64_C(0), // VST3q32oddPseudo 2589 UINT64_C(0), // VST3q32oddPseudo_UPD 2590 UINT64_C(4093641999), // VST3q8 2591 UINT64_C(0), // VST3q8Pseudo_UPD 2592 UINT64_C(4093641984), // VST3q8_UPD 2593 UINT64_C(0), // VST3q8oddPseudo 2594 UINT64_C(0), // VST3q8oddPseudo_UPD 2595 UINT64_C(4102031119), // VST4LNd16 2596 UINT64_C(0), // VST4LNd16Pseudo 2597 UINT64_C(0), // VST4LNd16Pseudo_UPD 2598 UINT64_C(4102031104), // VST4LNd16_UPD 2599 UINT64_C(4102032143), // VST4LNd32 2600 UINT64_C(0), // VST4LNd32Pseudo 2601 UINT64_C(0), // VST4LNd32Pseudo_UPD 2602 UINT64_C(4102032128), // VST4LNd32_UPD 2603 UINT64_C(4102030095), // VST4LNd8 2604 UINT64_C(0), // VST4LNd8Pseudo 2605 UINT64_C(0), // VST4LNd8Pseudo_UPD 2606 UINT64_C(4102030080), // VST4LNd8_UPD 2607 UINT64_C(4102031151), // VST4LNq16 2608 UINT64_C(0), // VST4LNq16Pseudo 2609 UINT64_C(0), // VST4LNq16Pseudo_UPD 2610 UINT64_C(4102031136), // VST4LNq16_UPD 2611 UINT64_C(4102032207), // VST4LNq32 2612 UINT64_C(0), // VST4LNq32Pseudo 2613 UINT64_C(0), // VST4LNq32Pseudo_UPD 2614 UINT64_C(4102032192), // VST4LNq32_UPD 2615 UINT64_C(4093640783), // VST4d16 2616 UINT64_C(0), // VST4d16Pseudo 2617 UINT64_C(0), // VST4d16Pseudo_UPD 2618 UINT64_C(4093640768), // VST4d16_UPD 2619 UINT64_C(4093640847), // VST4d32 2620 UINT64_C(0), // VST4d32Pseudo 2621 UINT64_C(0), // VST4d32Pseudo_UPD 2622 UINT64_C(4093640832), // VST4d32_UPD 2623 UINT64_C(4093640719), // VST4d8 2624 UINT64_C(0), // VST4d8Pseudo 2625 UINT64_C(0), // VST4d8Pseudo_UPD 2626 UINT64_C(4093640704), // VST4d8_UPD 2627 UINT64_C(4093641039), // VST4q16 2628 UINT64_C(0), // VST4q16Pseudo_UPD 2629 UINT64_C(4093641024), // VST4q16_UPD 2630 UINT64_C(0), // VST4q16oddPseudo 2631 UINT64_C(0), // VST4q16oddPseudo_UPD 2632 UINT64_C(4093641103), // VST4q32 2633 UINT64_C(0), // VST4q32Pseudo_UPD 2634 UINT64_C(4093641088), // VST4q32_UPD 2635 UINT64_C(0), // VST4q32oddPseudo 2636 UINT64_C(0), // VST4q32oddPseudo_UPD 2637 UINT64_C(4093640975), // VST4q8 2638 UINT64_C(0), // VST4q8Pseudo_UPD 2639 UINT64_C(4093640960), // VST4q8_UPD 2640 UINT64_C(0), // VST4q8oddPseudo 2641 UINT64_C(0), // VST4q8oddPseudo_UPD 2642 UINT64_C(220203776), // VSTMDDB_UPD 2643 UINT64_C(209718016), // VSTMDIA 2644 UINT64_C(211815168), // VSTMDIA_UPD 2645 UINT64_C(0), // VSTMQIA 2646 UINT64_C(220203520), // VSTMSDB_UPD 2647 UINT64_C(209717760), // VSTMSIA 2648 UINT64_C(211814912), // VSTMSIA_UPD 2649 UINT64_C(218106624), // VSTRD 2650 UINT64_C(218106112), // VSTRH 2651 UINT64_C(218106368), // VSTRS 2652 UINT64_C(238029632), // VSUBD 2653 UINT64_C(238029120), // VSUBH 2654 UINT64_C(4070573568), // VSUBHNv2i32 2655 UINT64_C(4069524992), // VSUBHNv4i16 2656 UINT64_C(4068476416), // VSUBHNv8i8 2657 UINT64_C(4070572544), // VSUBLsv2i64 2658 UINT64_C(4069523968), // VSUBLsv4i32 2659 UINT64_C(4068475392), // VSUBLsv8i16 2660 UINT64_C(4087349760), // VSUBLuv2i64 2661 UINT64_C(4086301184), // VSUBLuv4i32 2662 UINT64_C(4085252608), // VSUBLuv8i16 2663 UINT64_C(238029376), // VSUBS 2664 UINT64_C(4070572800), // VSUBWsv2i64 2665 UINT64_C(4069524224), // VSUBWsv4i32 2666 UINT64_C(4068475648), // VSUBWsv8i16 2667 UINT64_C(4087350016), // VSUBWuv2i64 2668 UINT64_C(4086301440), // VSUBWuv4i32 2669 UINT64_C(4085252864), // VSUBWuv8i16 2670 UINT64_C(4062186752), // VSUBfd 2671 UINT64_C(4062186816), // VSUBfq 2672 UINT64_C(4063235328), // VSUBhd 2673 UINT64_C(4063235392), // VSUBhq 2674 UINT64_C(4076865600), // VSUBv16i8 2675 UINT64_C(4080011264), // VSUBv1i64 2676 UINT64_C(4078962688), // VSUBv2i32 2677 UINT64_C(4080011328), // VSUBv2i64 2678 UINT64_C(4077914112), // VSUBv4i16 2679 UINT64_C(4078962752), // VSUBv4i32 2680 UINT64_C(4077914176), // VSUBv8i16 2681 UINT64_C(4076865536), // VSUBv8i8 2682 UINT64_C(4088528896), // VSWPd 2683 UINT64_C(4088528960), // VSWPq 2684 UINT64_C(4088399872), // VTBL1 2685 UINT64_C(4088400128), // VTBL2 2686 UINT64_C(4088400384), // VTBL3 2687 UINT64_C(0), // VTBL3Pseudo 2688 UINT64_C(4088400640), // VTBL4 2689 UINT64_C(0), // VTBL4Pseudo 2690 UINT64_C(4088399936), // VTBX1 2691 UINT64_C(4088400192), // VTBX2 2692 UINT64_C(4088400448), // VTBX3 2693 UINT64_C(0), // VTBX3Pseudo 2694 UINT64_C(4088400704), // VTBX4 2695 UINT64_C(0), // VTBX4Pseudo 2696 UINT64_C(247335744), // VTOSHD 2697 UINT64_C(247335232), // VTOSHH 2698 UINT64_C(247335488), // VTOSHS 2699 UINT64_C(247270208), // VTOSIRD 2700 UINT64_C(247269696), // VTOSIRH 2701 UINT64_C(247269952), // VTOSIRS 2702 UINT64_C(247270336), // VTOSIZD 2703 UINT64_C(247269824), // VTOSIZH 2704 UINT64_C(247270080), // VTOSIZS 2705 UINT64_C(247335872), // VTOSLD 2706 UINT64_C(247335360), // VTOSLH 2707 UINT64_C(247335616), // VTOSLS 2708 UINT64_C(247401280), // VTOUHD 2709 UINT64_C(247400768), // VTOUHH 2710 UINT64_C(247401024), // VTOUHS 2711 UINT64_C(247204672), // VTOUIRD 2712 UINT64_C(247204160), // VTOUIRH 2713 UINT64_C(247204416), // VTOUIRS 2714 UINT64_C(247204800), // VTOUIZD 2715 UINT64_C(247204288), // VTOUIZH 2716 UINT64_C(247204544), // VTOUIZS 2717 UINT64_C(247401408), // VTOULD 2718 UINT64_C(247400896), // VTOULH 2719 UINT64_C(247401152), // VTOULS 2720 UINT64_C(4088791168), // VTRNd16 2721 UINT64_C(4089053312), // VTRNd32 2722 UINT64_C(4088529024), // VTRNd8 2723 UINT64_C(4088791232), // VTRNq16 2724 UINT64_C(4089053376), // VTRNq32 2725 UINT64_C(4088529088), // VTRNq8 2726 UINT64_C(4060088400), // VTSTv16i8 2727 UINT64_C(4062185488), // VTSTv2i32 2728 UINT64_C(4061136912), // VTSTv4i16 2729 UINT64_C(4062185552), // VTSTv4i32 2730 UINT64_C(4061136976), // VTSTv8i16 2731 UINT64_C(4060088336), // VTSTv8i8 2732 UINT64_C(4229958928), // VUDOTD 2733 UINT64_C(4263513360), // VUDOTDI 2734 UINT64_C(4229958992), // VUDOTQ 2735 UINT64_C(4263513424), // VUDOTQI 2736 UINT64_C(247139136), // VUHTOD 2737 UINT64_C(247138624), // VUHTOH 2738 UINT64_C(247138880), // VUHTOS 2739 UINT64_C(246942528), // VUITOD 2740 UINT64_C(246942016), // VUITOH 2741 UINT64_C(246942272), // VUITOS 2742 UINT64_C(247139264), // VULTOD 2743 UINT64_C(247138752), // VULTOH 2744 UINT64_C(247139008), // VULTOS 2745 UINT64_C(4088791296), // VUZPd16 2746 UINT64_C(4088529152), // VUZPd8 2747 UINT64_C(4088791360), // VUZPq16 2748 UINT64_C(4089053504), // VUZPq32 2749 UINT64_C(4088529216), // VUZPq8 2750 UINT64_C(4088791424), // VZIPd16 2751 UINT64_C(4088529280), // VZIPd8 2752 UINT64_C(4088791488), // VZIPq16 2753 UINT64_C(4089053632), // VZIPq32 2754 UINT64_C(4088529344), // VZIPq8 2755 UINT64_C(139460608), // sysLDMDA 2756 UINT64_C(141557760), // sysLDMDA_UPD 2757 UINT64_C(156237824), // sysLDMDB 2758 UINT64_C(158334976), // sysLDMDB_UPD 2759 UINT64_C(147849216), // sysLDMIA 2760 UINT64_C(149946368), // sysLDMIA_UPD 2761 UINT64_C(164626432), // sysLDMIB 2762 UINT64_C(166723584), // sysLDMIB_UPD 2763 UINT64_C(138412032), // sysSTMDA 2764 UINT64_C(140509184), // sysSTMDA_UPD 2765 UINT64_C(155189248), // sysSTMDB 2766 UINT64_C(157286400), // sysSTMDB_UPD 2767 UINT64_C(146800640), // sysSTMIA 2768 UINT64_C(148897792), // sysSTMIA_UPD 2769 UINT64_C(163577856), // sysSTMIB 2770 UINT64_C(165675008), // sysSTMIB_UPD 2771 UINT64_C(4047503360), // t2ADCri 2772 UINT64_C(3946840064), // t2ADCrr 2773 UINT64_C(3946840064), // t2ADCrs 2774 UINT64_C(4043309056), // t2ADDri 2775 UINT64_C(4060086272), // t2ADDri12 2776 UINT64_C(3942645760), // t2ADDrr 2777 UINT64_C(3942645760), // t2ADDrs 2778 UINT64_C(4061069312), // t2ADR 2779 UINT64_C(4026531840), // t2ANDri 2780 UINT64_C(3925868544), // t2ANDrr 2781 UINT64_C(3925868544), // t2ANDrs 2782 UINT64_C(3931045920), // t2ASRri 2783 UINT64_C(4198559744), // t2ASRrr 2784 UINT64_C(4026568704), // t2B 2785 UINT64_C(4084137984), // t2BFC 2786 UINT64_C(4083154944), // t2BFI 2787 UINT64_C(4028628992), // t2BICri 2788 UINT64_C(3927965696), // t2BICrr 2789 UINT64_C(3927965696), // t2BICrs 2790 UINT64_C(4089483008), // t2BXJ 2791 UINT64_C(4026564608), // t2Bcc 2792 UINT64_C(3992977408), // t2CDP 2793 UINT64_C(4261412864), // t2CDP2 2794 UINT64_C(4089417519), // t2CLREX 2795 UINT64_C(4205899904), // t2CLZ 2796 UINT64_C(4044361472), // t2CMNri 2797 UINT64_C(3943698176), // t2CMNzrr 2798 UINT64_C(3943698176), // t2CMNzrs 2799 UINT64_C(4054847232), // t2CMPri 2800 UINT64_C(3954183936), // t2CMPrr 2801 UINT64_C(3954183936), // t2CMPrs 2802 UINT64_C(4088365312), // t2CPS1p 2803 UINT64_C(4088365056), // t2CPS2p 2804 UINT64_C(4088365312), // t2CPS3p 2805 UINT64_C(4206948480), // t2CRC32B 2806 UINT64_C(4207997056), // t2CRC32CB 2807 UINT64_C(4207997072), // t2CRC32CH 2808 UINT64_C(4207997088), // t2CRC32CW 2809 UINT64_C(4206948496), // t2CRC32H 2810 UINT64_C(4206948512), // t2CRC32W 2811 UINT64_C(4088365296), // t2DBG 2812 UINT64_C(4153376769), // t2DCPS1 2813 UINT64_C(4153376770), // t2DCPS2 2814 UINT64_C(4153376771), // t2DCPS3 2815 UINT64_C(4089417552), // t2DMB 2816 UINT64_C(4089417536), // t2DSB 2817 UINT64_C(4034920448), // t2EORri 2818 UINT64_C(3934257152), // t2EORrr 2819 UINT64_C(3934257152), // t2EORrs 2820 UINT64_C(4088365056), // t2HINT 2821 UINT64_C(4158685184), // t2HVC 2822 UINT64_C(4089417568), // t2ISB 2823 UINT64_C(48896), // t2IT 2824 UINT64_C(0), // t2Int_eh_sjlj_setjmp 2825 UINT64_C(0), // t2Int_eh_sjlj_setjmp_nofp 2826 UINT64_C(3905949615), // t2LDA 2827 UINT64_C(3905949583), // t2LDAB 2828 UINT64_C(3905949679), // t2LDAEX 2829 UINT64_C(3905949647), // t2LDAEXB 2830 UINT64_C(3905945855), // t2LDAEXD 2831 UINT64_C(3905949663), // t2LDAEXH 2832 UINT64_C(3905949599), // t2LDAH 2833 UINT64_C(4249878528), // t2LDC2L_OFFSET 2834 UINT64_C(4241489920), // t2LDC2L_OPTION 2835 UINT64_C(4235198464), // t2LDC2L_POST 2836 UINT64_C(4251975680), // t2LDC2L_PRE 2837 UINT64_C(4245684224), // t2LDC2_OFFSET 2838 UINT64_C(4237295616), // t2LDC2_OPTION 2839 UINT64_C(4231004160), // t2LDC2_POST 2840 UINT64_C(4247781376), // t2LDC2_PRE 2841 UINT64_C(3981443072), // t2LDCL_OFFSET 2842 UINT64_C(3973054464), // t2LDCL_OPTION 2843 UINT64_C(3966763008), // t2LDCL_POST 2844 UINT64_C(3983540224), // t2LDCL_PRE 2845 UINT64_C(3977248768), // t2LDC_OFFSET 2846 UINT64_C(3968860160), // t2LDC_OPTION 2847 UINT64_C(3962568704), // t2LDC_POST 2848 UINT64_C(3979345920), // t2LDC_PRE 2849 UINT64_C(3910139904), // t2LDMDB 2850 UINT64_C(3912237056), // t2LDMDB_UPD 2851 UINT64_C(3901751296), // t2LDMIA 2852 UINT64_C(3903848448), // t2LDMIA_UPD 2853 UINT64_C(4161801728), // t2LDRBT 2854 UINT64_C(4161800448), // t2LDRB_POST 2855 UINT64_C(4161801472), // t2LDRB_PRE 2856 UINT64_C(4170186752), // t2LDRBi12 2857 UINT64_C(4161801216), // t2LDRBi8 2858 UINT64_C(4162781184), // t2LDRBpci 2859 UINT64_C(4161798144), // t2LDRBs 2860 UINT64_C(3899654144), // t2LDRD_POST 2861 UINT64_C(3916431360), // t2LDRD_PRE 2862 UINT64_C(3914334208), // t2LDRDi8 2863 UINT64_C(3897560832), // t2LDREX 2864 UINT64_C(3905949519), // t2LDREXB 2865 UINT64_C(3905945727), // t2LDREXD 2866 UINT64_C(3905949535), // t2LDREXH 2867 UINT64_C(4163898880), // t2LDRHT 2868 UINT64_C(4163897600), // t2LDRH_POST 2869 UINT64_C(4163898624), // t2LDRH_PRE 2870 UINT64_C(4172283904), // t2LDRHi12 2871 UINT64_C(4163898368), // t2LDRHi8 2872 UINT64_C(4164878336), // t2LDRHpci 2873 UINT64_C(4163895296), // t2LDRHs 2874 UINT64_C(4178578944), // t2LDRSBT 2875 UINT64_C(4178577664), // t2LDRSB_POST 2876 UINT64_C(4178578688), // t2LDRSB_PRE 2877 UINT64_C(4186963968), // t2LDRSBi12 2878 UINT64_C(4178578432), // t2LDRSBi8 2879 UINT64_C(4179558400), // t2LDRSBpci 2880 UINT64_C(4178575360), // t2LDRSBs 2881 UINT64_C(4180676096), // t2LDRSHT 2882 UINT64_C(4180674816), // t2LDRSH_POST 2883 UINT64_C(4180675840), // t2LDRSH_PRE 2884 UINT64_C(4189061120), // t2LDRSHi12 2885 UINT64_C(4180675584), // t2LDRSHi8 2886 UINT64_C(4181655552), // t2LDRSHpci 2887 UINT64_C(4180672512), // t2LDRSHs 2888 UINT64_C(4165996032), // t2LDRT 2889 UINT64_C(4165994752), // t2LDR_POST 2890 UINT64_C(4165995776), // t2LDR_PRE 2891 UINT64_C(4174381056), // t2LDRi12 2892 UINT64_C(4165995520), // t2LDRi8 2893 UINT64_C(4166975488), // t2LDRpci 2894 UINT64_C(4165992448), // t2LDRs 2895 UINT64_C(3931045888), // t2LSLri 2896 UINT64_C(4194365440), // t2LSLrr 2897 UINT64_C(3931045904), // t2LSRri 2898 UINT64_C(4196462592), // t2LSRrr 2899 UINT64_C(3992977424), // t2MCR 2900 UINT64_C(4261412880), // t2MCR2 2901 UINT64_C(3963617280), // t2MCRR 2902 UINT64_C(4232052736), // t2MCRR2 2903 UINT64_C(4211081216), // t2MLA 2904 UINT64_C(4211081232), // t2MLS 2905 UINT64_C(4072669184), // t2MOVTi16 2906 UINT64_C(4031709184), // t2MOVi 2907 UINT64_C(4064280576), // t2MOVi16 2908 UINT64_C(3931045888), // t2MOVr 2909 UINT64_C(3932094560), // t2MOVsra_flag 2910 UINT64_C(3932094544), // t2MOVsrl_flag 2911 UINT64_C(3994026000), // t2MRC 2912 UINT64_C(4262461456), // t2MRC2 2913 UINT64_C(3964665856), // t2MRRC 2914 UINT64_C(4233101312), // t2MRRC2 2915 UINT64_C(4092559360), // t2MRS_AR 2916 UINT64_C(4092559360), // t2MRS_M 2917 UINT64_C(4091576352), // t2MRSbanked 2918 UINT64_C(4093607936), // t2MRSsys_AR 2919 UINT64_C(4085284864), // t2MSR_AR 2920 UINT64_C(4085284864), // t2MSR_M 2921 UINT64_C(4085284896), // t2MSRbanked 2922 UINT64_C(4211142656), // t2MUL 2923 UINT64_C(4033806336), // t2MVNi 2924 UINT64_C(3933143040), // t2MVNr 2925 UINT64_C(3933143040), // t2MVNs 2926 UINT64_C(4032823296), // t2ORNri 2927 UINT64_C(3932160000), // t2ORNrr 2928 UINT64_C(3932160000), // t2ORNrs 2929 UINT64_C(4030726144), // t2ORRri 2930 UINT64_C(3930062848), // t2ORRrr 2931 UINT64_C(3930062848), // t2ORRrs 2932 UINT64_C(3938451456), // t2PKHBT 2933 UINT64_C(3938451488), // t2PKHTB 2934 UINT64_C(4172345344), // t2PLDWi12 2935 UINT64_C(4163959808), // t2PLDWi8 2936 UINT64_C(4163956736), // t2PLDWs 2937 UINT64_C(4170248192), // t2PLDi12 2938 UINT64_C(4161862656), // t2PLDi8 2939 UINT64_C(4162842624), // t2PLDpci 2940 UINT64_C(4161859584), // t2PLDs 2941 UINT64_C(4187025408), // t2PLIi12 2942 UINT64_C(4178639872), // t2PLIi8 2943 UINT64_C(4179619840), // t2PLIpci 2944 UINT64_C(4178636800), // t2PLIs 2945 UINT64_C(4202754176), // t2QADD 2946 UINT64_C(4203802640), // t2QADD16 2947 UINT64_C(4202754064), // t2QADD8 2948 UINT64_C(4204851216), // t2QASX 2949 UINT64_C(4202754192), // t2QDADD 2950 UINT64_C(4202754224), // t2QDSUB 2951 UINT64_C(4209045520), // t2QSAX 2952 UINT64_C(4202754208), // t2QSUB 2953 UINT64_C(4207996944), // t2QSUB16 2954 UINT64_C(4206948368), // t2QSUB8 2955 UINT64_C(4203802784), // t2RBIT 2956 UINT64_C(4203802752), // t2REV 2957 UINT64_C(4203802768), // t2REV16 2958 UINT64_C(4203802800), // t2REVSH 2959 UINT64_C(3893411840), // t2RFEDB 2960 UINT64_C(3895508992), // t2RFEDBW 2961 UINT64_C(3918577664), // t2RFEIA 2962 UINT64_C(3920674816), // t2RFEIAW 2963 UINT64_C(3931045936), // t2RORri 2964 UINT64_C(4200656896), // t2RORrr 2965 UINT64_C(3931045936), // t2RRX 2966 UINT64_C(4055891968), // t2RSBri 2967 UINT64_C(3955228672), // t2RSBrr 2968 UINT64_C(3955228672), // t2RSBrs 2969 UINT64_C(4203802624), // t2SADD16 2970 UINT64_C(4202754048), // t2SADD8 2971 UINT64_C(4204851200), // t2SASX 2972 UINT64_C(4049600512), // t2SBCri 2973 UINT64_C(3948937216), // t2SBCrr 2974 UINT64_C(3948937216), // t2SBCrs 2975 UINT64_C(4081057792), // t2SBFX 2976 UINT64_C(4220580080), // t2SDIV 2977 UINT64_C(4204851328), // t2SEL 2978 UINT64_C(46608), // t2SETPAN 2979 UINT64_C(3917474175), // t2SG 2980 UINT64_C(4203802656), // t2SHADD16 2981 UINT64_C(4202754080), // t2SHADD8 2982 UINT64_C(4204851232), // t2SHASX 2983 UINT64_C(4209045536), // t2SHSAX 2984 UINT64_C(4207996960), // t2SHSUB16 2985 UINT64_C(4206948384), // t2SHSUB8 2986 UINT64_C(4159733760), // t2SMC 2987 UINT64_C(4212129792), // t2SMLABB 2988 UINT64_C(4212129808), // t2SMLABT 2989 UINT64_C(4213178368), // t2SMLAD 2990 UINT64_C(4213178384), // t2SMLADX 2991 UINT64_C(4223664128), // t2SMLAL 2992 UINT64_C(4223664256), // t2SMLALBB 2993 UINT64_C(4223664272), // t2SMLALBT 2994 UINT64_C(4223664320), // t2SMLALD 2995 UINT64_C(4223664336), // t2SMLALDX 2996 UINT64_C(4223664288), // t2SMLALTB 2997 UINT64_C(4223664304), // t2SMLALTT 2998 UINT64_C(4212129824), // t2SMLATB 2999 UINT64_C(4212129840), // t2SMLATT 3000 UINT64_C(4214226944), // t2SMLAWB 3001 UINT64_C(4214226960), // t2SMLAWT 3002 UINT64_C(4215275520), // t2SMLSD 3003 UINT64_C(4215275536), // t2SMLSDX 3004 UINT64_C(4224712896), // t2SMLSLD 3005 UINT64_C(4224712912), // t2SMLSLDX 3006 UINT64_C(4216324096), // t2SMMLA 3007 UINT64_C(4216324112), // t2SMMLAR 3008 UINT64_C(4217372672), // t2SMMLS 3009 UINT64_C(4217372688), // t2SMMLSR 3010 UINT64_C(4216385536), // t2SMMUL 3011 UINT64_C(4216385552), // t2SMMULR 3012 UINT64_C(4213239808), // t2SMUAD 3013 UINT64_C(4213239824), // t2SMUADX 3014 UINT64_C(4212191232), // t2SMULBB 3015 UINT64_C(4212191248), // t2SMULBT 3016 UINT64_C(4219469824), // t2SMULL 3017 UINT64_C(4212191264), // t2SMULTB 3018 UINT64_C(4212191280), // t2SMULTT 3019 UINT64_C(4214288384), // t2SMULWB 3020 UINT64_C(4214288400), // t2SMULWT 3021 UINT64_C(4215336960), // t2SMUSD 3022 UINT64_C(4215336976), // t2SMUSDX 3023 UINT64_C(3893215232), // t2SRSDB 3024 UINT64_C(3895312384), // t2SRSDB_UPD 3025 UINT64_C(3918381056), // t2SRSIA 3026 UINT64_C(3920478208), // t2SRSIA_UPD 3027 UINT64_C(4076863488), // t2SSAT 3028 UINT64_C(4078960640), // t2SSAT16 3029 UINT64_C(4209045504), // t2SSAX 3030 UINT64_C(4207996928), // t2SSUB16 3031 UINT64_C(4206948352), // t2SSUB8 3032 UINT64_C(4248829952), // t2STC2L_OFFSET 3033 UINT64_C(4240441344), // t2STC2L_OPTION 3034 UINT64_C(4234149888), // t2STC2L_POST 3035 UINT64_C(4250927104), // t2STC2L_PRE 3036 UINT64_C(4244635648), // t2STC2_OFFSET 3037 UINT64_C(4236247040), // t2STC2_OPTION 3038 UINT64_C(4229955584), // t2STC2_POST 3039 UINT64_C(4246732800), // t2STC2_PRE 3040 UINT64_C(3980394496), // t2STCL_OFFSET 3041 UINT64_C(3972005888), // t2STCL_OPTION 3042 UINT64_C(3965714432), // t2STCL_POST 3043 UINT64_C(3982491648), // t2STCL_PRE 3044 UINT64_C(3976200192), // t2STC_OFFSET 3045 UINT64_C(3967811584), // t2STC_OPTION 3046 UINT64_C(3961520128), // t2STC_POST 3047 UINT64_C(3978297344), // t2STC_PRE 3048 UINT64_C(3904901039), // t2STL 3049 UINT64_C(3904901007), // t2STLB 3050 UINT64_C(3904901088), // t2STLEX 3051 UINT64_C(3904901056), // t2STLEXB 3052 UINT64_C(3904897264), // t2STLEXD 3053 UINT64_C(3904901072), // t2STLEXH 3054 UINT64_C(3904901023), // t2STLH 3055 UINT64_C(3909091328), // t2STMDB 3056 UINT64_C(3911188480), // t2STMDB_UPD 3057 UINT64_C(3900702720), // t2STMIA 3058 UINT64_C(3902799872), // t2STMIA_UPD 3059 UINT64_C(4160753152), // t2STRBT 3060 UINT64_C(4160751872), // t2STRB_POST 3061 UINT64_C(4160752896), // t2STRB_PRE 3062 UINT64_C(4169138176), // t2STRBi12 3063 UINT64_C(4160752640), // t2STRBi8 3064 UINT64_C(4160749568), // t2STRBs 3065 UINT64_C(3898605568), // t2STRD_POST 3066 UINT64_C(3915382784), // t2STRD_PRE 3067 UINT64_C(3913285632), // t2STRDi8 3068 UINT64_C(3896508416), // t2STREX 3069 UINT64_C(3904900928), // t2STREXB 3070 UINT64_C(3904897136), // t2STREXD 3071 UINT64_C(3904900944), // t2STREXH 3072 UINT64_C(4162850304), // t2STRHT 3073 UINT64_C(4162849024), // t2STRH_POST 3074 UINT64_C(4162850048), // t2STRH_PRE 3075 UINT64_C(4171235328), // t2STRHi12 3076 UINT64_C(4162849792), // t2STRHi8 3077 UINT64_C(4162846720), // t2STRHs 3078 UINT64_C(4164947456), // t2STRT 3079 UINT64_C(4164946176), // t2STR_POST 3080 UINT64_C(4164947200), // t2STR_PRE 3081 UINT64_C(4173332480), // t2STRi12 3082 UINT64_C(4164946944), // t2STRi8 3083 UINT64_C(4164943872), // t2STRs 3084 UINT64_C(4091449088), // t2SUBS_PC_LR 3085 UINT64_C(4053794816), // t2SUBri 3086 UINT64_C(4070572032), // t2SUBri12 3087 UINT64_C(3953131520), // t2SUBrr 3088 UINT64_C(3953131520), // t2SUBrs 3089 UINT64_C(4198559872), // t2SXTAB 3090 UINT64_C(4196462720), // t2SXTAB16 3091 UINT64_C(4194365568), // t2SXTAH 3092 UINT64_C(4199542912), // t2SXTB 3093 UINT64_C(4197445760), // t2SXTB16 3094 UINT64_C(4195348608), // t2SXTH 3095 UINT64_C(3906007040), // t2TBB 3096 UINT64_C(3906007056), // t2TBH 3097 UINT64_C(4035972864), // t2TEQri 3098 UINT64_C(3935309568), // t2TEQrr 3099 UINT64_C(3935309568), // t2TEQrs 3100 UINT64_C(4088365074), // t2TSB 3101 UINT64_C(4027584256), // t2TSTri 3102 UINT64_C(3926920960), // t2TSTrr 3103 UINT64_C(3926920960), // t2TSTrs 3104 UINT64_C(3896569856), // t2TT 3105 UINT64_C(3896569984), // t2TTA 3106 UINT64_C(3896570048), // t2TTAT 3107 UINT64_C(3896569920), // t2TTT 3108 UINT64_C(4203802688), // t2UADD16 3109 UINT64_C(4202754112), // t2UADD8 3110 UINT64_C(4204851264), // t2UASX 3111 UINT64_C(4089446400), // t2UBFX 3112 UINT64_C(4159741952), // t2UDF 3113 UINT64_C(4222677232), // t2UDIV 3114 UINT64_C(4203802720), // t2UHADD16 3115 UINT64_C(4202754144), // t2UHADD8 3116 UINT64_C(4204851296), // t2UHASX 3117 UINT64_C(4209045600), // t2UHSAX 3118 UINT64_C(4207997024), // t2UHSUB16 3119 UINT64_C(4206948448), // t2UHSUB8 3120 UINT64_C(4225761376), // t2UMAAL 3121 UINT64_C(4225761280), // t2UMLAL 3122 UINT64_C(4221566976), // t2UMULL 3123 UINT64_C(4203802704), // t2UQADD16 3124 UINT64_C(4202754128), // t2UQADD8 3125 UINT64_C(4204851280), // t2UQASX 3126 UINT64_C(4209045584), // t2UQSAX 3127 UINT64_C(4207997008), // t2UQSUB16 3128 UINT64_C(4206948432), // t2UQSUB8 3129 UINT64_C(4218482688), // t2USAD8 3130 UINT64_C(4218421248), // t2USADA8 3131 UINT64_C(4085252096), // t2USAT 3132 UINT64_C(4087349248), // t2USAT16 3133 UINT64_C(4209045568), // t2USAX 3134 UINT64_C(4207996992), // t2USUB16 3135 UINT64_C(4206948416), // t2USUB8 3136 UINT64_C(4199608448), // t2UXTAB 3137 UINT64_C(4197511296), // t2UXTAB16 3138 UINT64_C(4195414144), // t2UXTAH 3139 UINT64_C(4200591488), // t2UXTB 3140 UINT64_C(4198494336), // t2UXTB16 3141 UINT64_C(4196397184), // t2UXTH 3142 UINT64_C(16704), // tADC 3143 UINT64_C(17408), // tADDhirr 3144 UINT64_C(7168), // tADDi3 3145 UINT64_C(12288), // tADDi8 3146 UINT64_C(17512), // tADDrSP 3147 UINT64_C(43008), // tADDrSPi 3148 UINT64_C(6144), // tADDrr 3149 UINT64_C(45056), // tADDspi 3150 UINT64_C(17541), // tADDspr 3151 UINT64_C(40960), // tADR 3152 UINT64_C(16384), // tAND 3153 UINT64_C(4096), // tASRri 3154 UINT64_C(16640), // tASRrr 3155 UINT64_C(57344), // tB 3156 UINT64_C(17280), // tBIC 3157 UINT64_C(48640), // tBKPT 3158 UINT64_C(4026585088), // tBL 3159 UINT64_C(18308), // tBLXNSr 3160 UINT64_C(4026580992), // tBLXi 3161 UINT64_C(18304), // tBLXr 3162 UINT64_C(18176), // tBX 3163 UINT64_C(18180), // tBXNS 3164 UINT64_C(53248), // tBcc 3165 UINT64_C(47360), // tCBNZ 3166 UINT64_C(45312), // tCBZ 3167 UINT64_C(17088), // tCMNz 3168 UINT64_C(17664), // tCMPhir 3169 UINT64_C(10240), // tCMPi8 3170 UINT64_C(17024), // tCMPr 3171 UINT64_C(46688), // tCPS 3172 UINT64_C(16448), // tEOR 3173 UINT64_C(48896), // tHINT 3174 UINT64_C(47744), // tHLT 3175 UINT64_C(0), // tInt_WIN_eh_sjlj_longjmp 3176 UINT64_C(0), // tInt_eh_sjlj_longjmp 3177 UINT64_C(0), // tInt_eh_sjlj_setjmp 3178 UINT64_C(51200), // tLDMIA 3179 UINT64_C(30720), // tLDRBi 3180 UINT64_C(23552), // tLDRBr 3181 UINT64_C(34816), // tLDRHi 3182 UINT64_C(23040), // tLDRHr 3183 UINT64_C(22016), // tLDRSB 3184 UINT64_C(24064), // tLDRSH 3185 UINT64_C(26624), // tLDRi 3186 UINT64_C(18432), // tLDRpci 3187 UINT64_C(22528), // tLDRr 3188 UINT64_C(38912), // tLDRspi 3189 UINT64_C(0), // tLSLri 3190 UINT64_C(16512), // tLSLrr 3191 UINT64_C(2048), // tLSRri 3192 UINT64_C(16576), // tLSRrr 3193 UINT64_C(0), // tMOVSr 3194 UINT64_C(8192), // tMOVi8 3195 UINT64_C(17920), // tMOVr 3196 UINT64_C(17216), // tMUL 3197 UINT64_C(17344), // tMVN 3198 UINT64_C(17152), // tORR 3199 UINT64_C(17528), // tPICADD 3200 UINT64_C(48128), // tPOP 3201 UINT64_C(46080), // tPUSH 3202 UINT64_C(47616), // tREV 3203 UINT64_C(47680), // tREV16 3204 UINT64_C(47808), // tREVSH 3205 UINT64_C(16832), // tROR 3206 UINT64_C(16960), // tRSB 3207 UINT64_C(16768), // tSBC 3208 UINT64_C(46672), // tSETEND 3209 UINT64_C(49152), // tSTMIA_UPD 3210 UINT64_C(28672), // tSTRBi 3211 UINT64_C(21504), // tSTRBr 3212 UINT64_C(32768), // tSTRHi 3213 UINT64_C(20992), // tSTRHr 3214 UINT64_C(24576), // tSTRi 3215 UINT64_C(20480), // tSTRr 3216 UINT64_C(36864), // tSTRspi 3217 UINT64_C(7680), // tSUBi3 3218 UINT64_C(14336), // tSUBi8 3219 UINT64_C(6656), // tSUBrr 3220 UINT64_C(45184), // tSUBspi 3221 UINT64_C(57088), // tSVC 3222 UINT64_C(45632), // tSXTB 3223 UINT64_C(45568), // tSXTH 3224 UINT64_C(57086), // tTRAP 3225 UINT64_C(16896), // tTST 3226 UINT64_C(56832), // tUDF 3227 UINT64_C(45760), // tUXTB 3228 UINT64_C(45696), // tUXTH 3229 UINT64_C(57081), // t__brkdiv0 3230 UINT64_C(0) 3231 }; 3232 const unsigned opcode = MI.getOpcode(); 3233 uint64_t Value = InstBits[opcode]; 3234 uint64_t op = 0; 3235 (void)op; // suppress warning 3236 switch (opcode) { 3237 case ARM::CLREX: 3238 case ARM::TRAP: 3239 case ARM::TRAPNaCl: 3240 case ARM::TSB: 3241 case ARM::VLD1LNq16Pseudo: 3242 case ARM::VLD1LNq16Pseudo_UPD: 3243 case ARM::VLD1LNq32Pseudo: 3244 case ARM::VLD1LNq32Pseudo_UPD: 3245 case ARM::VLD1LNq8Pseudo: 3246 case ARM::VLD1LNq8Pseudo_UPD: 3247 case ARM::VLD1d16QPseudo: 3248 case ARM::VLD1d16TPseudo: 3249 case ARM::VLD1d32QPseudo: 3250 case ARM::VLD1d32TPseudo: 3251 case ARM::VLD1d64QPseudo: 3252 case ARM::VLD1d64QPseudoWB_fixed: 3253 case ARM::VLD1d64QPseudoWB_register: 3254 case ARM::VLD1d64TPseudo: 3255 case ARM::VLD1d64TPseudoWB_fixed: 3256 case ARM::VLD1d64TPseudoWB_register: 3257 case ARM::VLD1d8QPseudo: 3258 case ARM::VLD1d8TPseudo: 3259 case ARM::VLD1q16HighQPseudo: 3260 case ARM::VLD1q16HighTPseudo: 3261 case ARM::VLD1q16LowQPseudo_UPD: 3262 case ARM::VLD1q16LowTPseudo_UPD: 3263 case ARM::VLD1q32HighQPseudo: 3264 case ARM::VLD1q32HighTPseudo: 3265 case ARM::VLD1q32LowQPseudo_UPD: 3266 case ARM::VLD1q32LowTPseudo_UPD: 3267 case ARM::VLD1q64HighQPseudo: 3268 case ARM::VLD1q64HighTPseudo: 3269 case ARM::VLD1q64LowQPseudo_UPD: 3270 case ARM::VLD1q64LowTPseudo_UPD: 3271 case ARM::VLD1q8HighQPseudo: 3272 case ARM::VLD1q8HighTPseudo: 3273 case ARM::VLD1q8LowQPseudo_UPD: 3274 case ARM::VLD1q8LowTPseudo_UPD: 3275 case ARM::VLD2DUPq16EvenPseudo: 3276 case ARM::VLD2DUPq16OddPseudo: 3277 case ARM::VLD2DUPq32EvenPseudo: 3278 case ARM::VLD2DUPq32OddPseudo: 3279 case ARM::VLD2DUPq8EvenPseudo: 3280 case ARM::VLD2DUPq8OddPseudo: 3281 case ARM::VLD2LNd16Pseudo: 3282 case ARM::VLD2LNd16Pseudo_UPD: 3283 case ARM::VLD2LNd32Pseudo: 3284 case ARM::VLD2LNd32Pseudo_UPD: 3285 case ARM::VLD2LNd8Pseudo: 3286 case ARM::VLD2LNd8Pseudo_UPD: 3287 case ARM::VLD2LNq16Pseudo: 3288 case ARM::VLD2LNq16Pseudo_UPD: 3289 case ARM::VLD2LNq32Pseudo: 3290 case ARM::VLD2LNq32Pseudo_UPD: 3291 case ARM::VLD2q16Pseudo: 3292 case ARM::VLD2q16PseudoWB_fixed: 3293 case ARM::VLD2q16PseudoWB_register: 3294 case ARM::VLD2q32Pseudo: 3295 case ARM::VLD2q32PseudoWB_fixed: 3296 case ARM::VLD2q32PseudoWB_register: 3297 case ARM::VLD2q8Pseudo: 3298 case ARM::VLD2q8PseudoWB_fixed: 3299 case ARM::VLD2q8PseudoWB_register: 3300 case ARM::VLD3DUPd16Pseudo: 3301 case ARM::VLD3DUPd16Pseudo_UPD: 3302 case ARM::VLD3DUPd32Pseudo: 3303 case ARM::VLD3DUPd32Pseudo_UPD: 3304 case ARM::VLD3DUPd8Pseudo: 3305 case ARM::VLD3DUPd8Pseudo_UPD: 3306 case ARM::VLD3DUPq16EvenPseudo: 3307 case ARM::VLD3DUPq16OddPseudo: 3308 case ARM::VLD3DUPq32EvenPseudo: 3309 case ARM::VLD3DUPq32OddPseudo: 3310 case ARM::VLD3DUPq8EvenPseudo: 3311 case ARM::VLD3DUPq8OddPseudo: 3312 case ARM::VLD3LNd16Pseudo: 3313 case ARM::VLD3LNd16Pseudo_UPD: 3314 case ARM::VLD3LNd32Pseudo: 3315 case ARM::VLD3LNd32Pseudo_UPD: 3316 case ARM::VLD3LNd8Pseudo: 3317 case ARM::VLD3LNd8Pseudo_UPD: 3318 case ARM::VLD3LNq16Pseudo: 3319 case ARM::VLD3LNq16Pseudo_UPD: 3320 case ARM::VLD3LNq32Pseudo: 3321 case ARM::VLD3LNq32Pseudo_UPD: 3322 case ARM::VLD3d16Pseudo: 3323 case ARM::VLD3d16Pseudo_UPD: 3324 case ARM::VLD3d32Pseudo: 3325 case ARM::VLD3d32Pseudo_UPD: 3326 case ARM::VLD3d8Pseudo: 3327 case ARM::VLD3d8Pseudo_UPD: 3328 case ARM::VLD3q16Pseudo_UPD: 3329 case ARM::VLD3q16oddPseudo: 3330 case ARM::VLD3q16oddPseudo_UPD: 3331 case ARM::VLD3q32Pseudo_UPD: 3332 case ARM::VLD3q32oddPseudo: 3333 case ARM::VLD3q32oddPseudo_UPD: 3334 case ARM::VLD3q8Pseudo_UPD: 3335 case ARM::VLD3q8oddPseudo: 3336 case ARM::VLD3q8oddPseudo_UPD: 3337 case ARM::VLD4DUPd16Pseudo: 3338 case ARM::VLD4DUPd16Pseudo_UPD: 3339 case ARM::VLD4DUPd32Pseudo: 3340 case ARM::VLD4DUPd32Pseudo_UPD: 3341 case ARM::VLD4DUPd8Pseudo: 3342 case ARM::VLD4DUPd8Pseudo_UPD: 3343 case ARM::VLD4DUPq16EvenPseudo: 3344 case ARM::VLD4DUPq16OddPseudo: 3345 case ARM::VLD4DUPq32EvenPseudo: 3346 case ARM::VLD4DUPq32OddPseudo: 3347 case ARM::VLD4DUPq8EvenPseudo: 3348 case ARM::VLD4DUPq8OddPseudo: 3349 case ARM::VLD4LNd16Pseudo: 3350 case ARM::VLD4LNd16Pseudo_UPD: 3351 case ARM::VLD4LNd32Pseudo: 3352 case ARM::VLD4LNd32Pseudo_UPD: 3353 case ARM::VLD4LNd8Pseudo: 3354 case ARM::VLD4LNd8Pseudo_UPD: 3355 case ARM::VLD4LNq16Pseudo: 3356 case ARM::VLD4LNq16Pseudo_UPD: 3357 case ARM::VLD4LNq32Pseudo: 3358 case ARM::VLD4LNq32Pseudo_UPD: 3359 case ARM::VLD4d16Pseudo: 3360 case ARM::VLD4d16Pseudo_UPD: 3361 case ARM::VLD4d32Pseudo: 3362 case ARM::VLD4d32Pseudo_UPD: 3363 case ARM::VLD4d8Pseudo: 3364 case ARM::VLD4d8Pseudo_UPD: 3365 case ARM::VLD4q16Pseudo_UPD: 3366 case ARM::VLD4q16oddPseudo: 3367 case ARM::VLD4q16oddPseudo_UPD: 3368 case ARM::VLD4q32Pseudo_UPD: 3369 case ARM::VLD4q32oddPseudo: 3370 case ARM::VLD4q32oddPseudo_UPD: 3371 case ARM::VLD4q8Pseudo_UPD: 3372 case ARM::VLD4q8oddPseudo: 3373 case ARM::VLD4q8oddPseudo_UPD: 3374 case ARM::VLDMQIA: 3375 case ARM::VST1LNq16Pseudo: 3376 case ARM::VST1LNq16Pseudo_UPD: 3377 case ARM::VST1LNq32Pseudo: 3378 case ARM::VST1LNq32Pseudo_UPD: 3379 case ARM::VST1LNq8Pseudo: 3380 case ARM::VST1LNq8Pseudo_UPD: 3381 case ARM::VST1d16QPseudo: 3382 case ARM::VST1d16TPseudo: 3383 case ARM::VST1d32QPseudo: 3384 case ARM::VST1d32TPseudo: 3385 case ARM::VST1d64QPseudo: 3386 case ARM::VST1d64QPseudoWB_fixed: 3387 case ARM::VST1d64QPseudoWB_register: 3388 case ARM::VST1d64TPseudo: 3389 case ARM::VST1d64TPseudoWB_fixed: 3390 case ARM::VST1d64TPseudoWB_register: 3391 case ARM::VST1d8QPseudo: 3392 case ARM::VST1d8TPseudo: 3393 case ARM::VST1q16HighQPseudo: 3394 case ARM::VST1q16HighTPseudo: 3395 case ARM::VST1q16LowQPseudo_UPD: 3396 case ARM::VST1q16LowTPseudo_UPD: 3397 case ARM::VST1q32HighQPseudo: 3398 case ARM::VST1q32HighTPseudo: 3399 case ARM::VST1q32LowQPseudo_UPD: 3400 case ARM::VST1q32LowTPseudo_UPD: 3401 case ARM::VST1q64HighQPseudo: 3402 case ARM::VST1q64HighTPseudo: 3403 case ARM::VST1q64LowQPseudo_UPD: 3404 case ARM::VST1q64LowTPseudo_UPD: 3405 case ARM::VST1q8HighQPseudo: 3406 case ARM::VST1q8HighTPseudo: 3407 case ARM::VST1q8LowQPseudo_UPD: 3408 case ARM::VST1q8LowTPseudo_UPD: 3409 case ARM::VST2LNd16Pseudo: 3410 case ARM::VST2LNd16Pseudo_UPD: 3411 case ARM::VST2LNd32Pseudo: 3412 case ARM::VST2LNd32Pseudo_UPD: 3413 case ARM::VST2LNd8Pseudo: 3414 case ARM::VST2LNd8Pseudo_UPD: 3415 case ARM::VST2LNq16Pseudo: 3416 case ARM::VST2LNq16Pseudo_UPD: 3417 case ARM::VST2LNq32Pseudo: 3418 case ARM::VST2LNq32Pseudo_UPD: 3419 case ARM::VST2q16Pseudo: 3420 case ARM::VST2q16PseudoWB_fixed: 3421 case ARM::VST2q16PseudoWB_register: 3422 case ARM::VST2q32Pseudo: 3423 case ARM::VST2q32PseudoWB_fixed: 3424 case ARM::VST2q32PseudoWB_register: 3425 case ARM::VST2q8Pseudo: 3426 case ARM::VST2q8PseudoWB_fixed: 3427 case ARM::VST2q8PseudoWB_register: 3428 case ARM::VST3LNd16Pseudo: 3429 case ARM::VST3LNd16Pseudo_UPD: 3430 case ARM::VST3LNd32Pseudo: 3431 case ARM::VST3LNd32Pseudo_UPD: 3432 case ARM::VST3LNd8Pseudo: 3433 case ARM::VST3LNd8Pseudo_UPD: 3434 case ARM::VST3LNq16Pseudo: 3435 case ARM::VST3LNq16Pseudo_UPD: 3436 case ARM::VST3LNq32Pseudo: 3437 case ARM::VST3LNq32Pseudo_UPD: 3438 case ARM::VST3d16Pseudo: 3439 case ARM::VST3d16Pseudo_UPD: 3440 case ARM::VST3d32Pseudo: 3441 case ARM::VST3d32Pseudo_UPD: 3442 case ARM::VST3d8Pseudo: 3443 case ARM::VST3d8Pseudo_UPD: 3444 case ARM::VST3q16Pseudo_UPD: 3445 case ARM::VST3q16oddPseudo: 3446 case ARM::VST3q16oddPseudo_UPD: 3447 case ARM::VST3q32Pseudo_UPD: 3448 case ARM::VST3q32oddPseudo: 3449 case ARM::VST3q32oddPseudo_UPD: 3450 case ARM::VST3q8Pseudo_UPD: 3451 case ARM::VST3q8oddPseudo: 3452 case ARM::VST3q8oddPseudo_UPD: 3453 case ARM::VST4LNd16Pseudo: 3454 case ARM::VST4LNd16Pseudo_UPD: 3455 case ARM::VST4LNd32Pseudo: 3456 case ARM::VST4LNd32Pseudo_UPD: 3457 case ARM::VST4LNd8Pseudo: 3458 case ARM::VST4LNd8Pseudo_UPD: 3459 case ARM::VST4LNq16Pseudo: 3460 case ARM::VST4LNq16Pseudo_UPD: 3461 case ARM::VST4LNq32Pseudo: 3462 case ARM::VST4LNq32Pseudo_UPD: 3463 case ARM::VST4d16Pseudo: 3464 case ARM::VST4d16Pseudo_UPD: 3465 case ARM::VST4d32Pseudo: 3466 case ARM::VST4d32Pseudo_UPD: 3467 case ARM::VST4d8Pseudo: 3468 case ARM::VST4d8Pseudo_UPD: 3469 case ARM::VST4q16Pseudo_UPD: 3470 case ARM::VST4q16oddPseudo: 3471 case ARM::VST4q16oddPseudo_UPD: 3472 case ARM::VST4q32Pseudo_UPD: 3473 case ARM::VST4q32oddPseudo: 3474 case ARM::VST4q32oddPseudo_UPD: 3475 case ARM::VST4q8Pseudo_UPD: 3476 case ARM::VST4q8oddPseudo: 3477 case ARM::VST4q8oddPseudo_UPD: 3478 case ARM::VSTMQIA: 3479 case ARM::VTBL3Pseudo: 3480 case ARM::VTBL4Pseudo: 3481 case ARM::VTBX3Pseudo: 3482 case ARM::VTBX4Pseudo: 3483 case ARM::t2CLREX: 3484 case ARM::t2DCPS1: 3485 case ARM::t2DCPS2: 3486 case ARM::t2DCPS3: 3487 case ARM::t2Int_eh_sjlj_setjmp: 3488 case ARM::t2Int_eh_sjlj_setjmp_nofp: 3489 case ARM::t2SG: 3490 case ARM::t2TSB: 3491 case ARM::tInt_WIN_eh_sjlj_longjmp: 3492 case ARM::tInt_eh_sjlj_longjmp: 3493 case ARM::tInt_eh_sjlj_setjmp: 3494 case ARM::tTRAP: 3495 case ARM::t__brkdiv0: { 3496 break; 3497 } 3498 case ARM::VRINTAD: 3499 case ARM::VRINTMD: 3500 case ARM::VRINTND: 3501 case ARM::VRINTPD: { 3502 // op: Dd 3503 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3504 Value |= (op & UINT64_C(16)) << 18; 3505 Value |= (op & UINT64_C(15)) << 12; 3506 // op: Dm 3507 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3508 Value |= (op & UINT64_C(16)) << 1; 3509 Value |= op & UINT64_C(15); 3510 break; 3511 } 3512 case ARM::VMAXNMD: 3513 case ARM::VMINNMD: 3514 case ARM::VSELEQD: 3515 case ARM::VSELGED: 3516 case ARM::VSELGTD: 3517 case ARM::VSELVSD: { 3518 // op: Dd 3519 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3520 Value |= (op & UINT64_C(16)) << 18; 3521 Value |= (op & UINT64_C(15)) << 12; 3522 // op: Dn 3523 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3524 Value |= (op & UINT64_C(15)) << 16; 3525 Value |= (op & UINT64_C(16)) << 3; 3526 // op: Dm 3527 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3528 Value |= (op & UINT64_C(16)) << 1; 3529 Value |= op & UINT64_C(15); 3530 break; 3531 } 3532 case ARM::CRC32B: 3533 case ARM::CRC32CB: 3534 case ARM::CRC32CH: 3535 case ARM::CRC32CW: 3536 case ARM::CRC32H: 3537 case ARM::CRC32W: { 3538 // op: Rd 3539 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3540 Value |= (op & UINT64_C(15)) << 12; 3541 // op: Rn 3542 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3543 Value |= (op & UINT64_C(15)) << 16; 3544 // op: Rm 3545 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3546 Value |= op & UINT64_C(15); 3547 break; 3548 } 3549 case ARM::t2MRS_AR: 3550 case ARM::t2MRSsys_AR: { 3551 // op: Rd 3552 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3553 Value |= (op & UINT64_C(15)) << 8; 3554 break; 3555 } 3556 case ARM::t2CLZ: 3557 case ARM::t2RBIT: 3558 case ARM::t2REV: 3559 case ARM::t2REV16: 3560 case ARM::t2REVSH: { 3561 // op: Rd 3562 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3563 Value |= (op & UINT64_C(15)) << 8; 3564 // op: Rm 3565 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3566 Value |= (op & UINT64_C(15)) << 16; 3567 Value |= op & UINT64_C(15); 3568 break; 3569 } 3570 case ARM::t2MOVsra_flag: 3571 case ARM::t2MOVsrl_flag: { 3572 // op: Rd 3573 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3574 Value |= (op & UINT64_C(15)) << 8; 3575 // op: Rm 3576 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3577 Value |= op & UINT64_C(15); 3578 break; 3579 } 3580 case ARM::t2SXTB: 3581 case ARM::t2SXTB16: 3582 case ARM::t2SXTH: 3583 case ARM::t2UXTB: 3584 case ARM::t2UXTB16: 3585 case ARM::t2UXTH: { 3586 // op: Rd 3587 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3588 Value |= (op & UINT64_C(15)) << 8; 3589 // op: Rm 3590 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3591 Value |= op & UINT64_C(15); 3592 // op: rot 3593 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3594 Value |= (op & UINT64_C(3)) << 4; 3595 break; 3596 } 3597 case ARM::t2CRC32B: 3598 case ARM::t2CRC32CB: 3599 case ARM::t2CRC32CH: 3600 case ARM::t2CRC32CW: 3601 case ARM::t2CRC32H: 3602 case ARM::t2CRC32W: 3603 case ARM::t2MUL: 3604 case ARM::t2QADD16: 3605 case ARM::t2QADD8: 3606 case ARM::t2QASX: 3607 case ARM::t2QSAX: 3608 case ARM::t2QSUB16: 3609 case ARM::t2QSUB8: 3610 case ARM::t2SADD16: 3611 case ARM::t2SADD8: 3612 case ARM::t2SASX: 3613 case ARM::t2SDIV: 3614 case ARM::t2SEL: 3615 case ARM::t2SHADD16: 3616 case ARM::t2SHADD8: 3617 case ARM::t2SHASX: 3618 case ARM::t2SHSAX: 3619 case ARM::t2SHSUB16: 3620 case ARM::t2SHSUB8: 3621 case ARM::t2SMMUL: 3622 case ARM::t2SMMULR: 3623 case ARM::t2SMUAD: 3624 case ARM::t2SMUADX: 3625 case ARM::t2SMULBB: 3626 case ARM::t2SMULBT: 3627 case ARM::t2SMULTB: 3628 case ARM::t2SMULTT: 3629 case ARM::t2SMULWB: 3630 case ARM::t2SMULWT: 3631 case ARM::t2SMUSD: 3632 case ARM::t2SMUSDX: 3633 case ARM::t2SSAX: 3634 case ARM::t2SSUB16: 3635 case ARM::t2SSUB8: 3636 case ARM::t2UADD16: 3637 case ARM::t2UADD8: 3638 case ARM::t2UASX: 3639 case ARM::t2UDIV: 3640 case ARM::t2UHADD16: 3641 case ARM::t2UHADD8: 3642 case ARM::t2UHASX: 3643 case ARM::t2UHSAX: 3644 case ARM::t2UHSUB16: 3645 case ARM::t2UHSUB8: 3646 case ARM::t2UQADD16: 3647 case ARM::t2UQADD8: 3648 case ARM::t2UQASX: 3649 case ARM::t2UQSAX: 3650 case ARM::t2UQSUB16: 3651 case ARM::t2UQSUB8: 3652 case ARM::t2USAD8: 3653 case ARM::t2USAX: 3654 case ARM::t2USUB16: 3655 case ARM::t2USUB8: { 3656 // op: Rd 3657 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3658 Value |= (op & UINT64_C(15)) << 8; 3659 // op: Rn 3660 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3661 Value |= (op & UINT64_C(15)) << 16; 3662 // op: Rm 3663 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3664 Value |= op & UINT64_C(15); 3665 break; 3666 } 3667 case ARM::t2MLA: 3668 case ARM::t2MLS: 3669 case ARM::t2SMLABB: 3670 case ARM::t2SMLABT: 3671 case ARM::t2SMLAD: 3672 case ARM::t2SMLADX: 3673 case ARM::t2SMLATB: 3674 case ARM::t2SMLATT: 3675 case ARM::t2SMLAWB: 3676 case ARM::t2SMLAWT: 3677 case ARM::t2SMLSD: 3678 case ARM::t2SMLSDX: 3679 case ARM::t2SMMLA: 3680 case ARM::t2SMMLAR: 3681 case ARM::t2SMMLS: 3682 case ARM::t2SMMLSR: 3683 case ARM::t2USADA8: { 3684 // op: Rd 3685 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3686 Value |= (op & UINT64_C(15)) << 8; 3687 // op: Rn 3688 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3689 Value |= (op & UINT64_C(15)) << 16; 3690 // op: Rm 3691 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3692 Value |= op & UINT64_C(15); 3693 // op: Ra 3694 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 3695 Value |= (op & UINT64_C(15)) << 12; 3696 break; 3697 } 3698 case ARM::t2SXTAB: 3699 case ARM::t2SXTAB16: 3700 case ARM::t2SXTAH: 3701 case ARM::t2UXTAB: 3702 case ARM::t2UXTAB16: 3703 case ARM::t2UXTAH: { 3704 // op: Rd 3705 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3706 Value |= (op & UINT64_C(15)) << 8; 3707 // op: Rn 3708 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3709 Value |= (op & UINT64_C(15)) << 16; 3710 // op: Rm 3711 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3712 Value |= op & UINT64_C(15); 3713 // op: rot 3714 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 3715 Value |= (op & UINT64_C(3)) << 4; 3716 break; 3717 } 3718 case ARM::t2PKHBT: 3719 case ARM::t2PKHTB: { 3720 // op: Rd 3721 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3722 Value |= (op & UINT64_C(15)) << 8; 3723 // op: Rn 3724 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3725 Value |= (op & UINT64_C(15)) << 16; 3726 // op: Rm 3727 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3728 Value |= op & UINT64_C(15); 3729 // op: sh 3730 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 3731 Value |= (op & UINT64_C(28)) << 10; 3732 Value |= (op & UINT64_C(3)) << 6; 3733 break; 3734 } 3735 case ARM::t2ADDri12: 3736 case ARM::t2SUBri12: { 3737 // op: Rd 3738 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3739 Value |= (op & UINT64_C(15)) << 8; 3740 // op: Rn 3741 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3742 Value |= (op & UINT64_C(15)) << 16; 3743 // op: imm 3744 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3745 Value |= (op & UINT64_C(2048)) << 15; 3746 Value |= (op & UINT64_C(1792)) << 4; 3747 Value |= op & UINT64_C(255); 3748 break; 3749 } 3750 case ARM::t2QADD: 3751 case ARM::t2QDADD: 3752 case ARM::t2QDSUB: 3753 case ARM::t2QSUB: { 3754 // op: Rd 3755 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3756 Value |= (op & UINT64_C(15)) << 8; 3757 // op: Rn 3758 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3759 Value |= (op & UINT64_C(15)) << 16; 3760 // op: Rm 3761 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3762 Value |= op & UINT64_C(15); 3763 break; 3764 } 3765 case ARM::t2BFI: { 3766 // op: Rd 3767 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3768 Value |= (op & UINT64_C(15)) << 8; 3769 // op: Rn 3770 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3771 Value |= (op & UINT64_C(15)) << 16; 3772 // op: imm 3773 op = getBitfieldInvertedMaskOpValue(MI, 3, Fixups, STI); 3774 Value |= (op & UINT64_C(28)) << 10; 3775 Value |= (op & UINT64_C(3)) << 6; 3776 Value |= (op & UINT64_C(992)) >> 5; 3777 break; 3778 } 3779 case ARM::t2SSAT16: 3780 case ARM::t2USAT16: { 3781 // op: Rd 3782 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3783 Value |= (op & UINT64_C(15)) << 8; 3784 // op: Rn 3785 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3786 Value |= (op & UINT64_C(15)) << 16; 3787 // op: sat_imm 3788 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3789 Value |= op & UINT64_C(15); 3790 break; 3791 } 3792 case ARM::t2SSAT: 3793 case ARM::t2USAT: { 3794 // op: Rd 3795 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3796 Value |= (op & UINT64_C(15)) << 8; 3797 // op: Rn 3798 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3799 Value |= (op & UINT64_C(15)) << 16; 3800 // op: sat_imm 3801 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3802 Value |= op & UINT64_C(31); 3803 // op: sh 3804 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 3805 Value |= (op & UINT64_C(32)) << 16; 3806 Value |= (op & UINT64_C(28)) << 10; 3807 Value |= (op & UINT64_C(3)) << 6; 3808 break; 3809 } 3810 case ARM::t2STREX: { 3811 // op: Rd 3812 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3813 Value |= (op & UINT64_C(15)) << 8; 3814 // op: Rt 3815 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3816 Value |= (op & UINT64_C(15)) << 12; 3817 // op: addr 3818 op = getT2AddrModeImm0_1020s4OpValue(MI, 2, Fixups, STI); 3819 Value |= (op & UINT64_C(3840)) << 8; 3820 Value |= op & UINT64_C(255); 3821 break; 3822 } 3823 case ARM::t2MRS_M: { 3824 // op: Rd 3825 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3826 Value |= (op & UINT64_C(15)) << 8; 3827 // op: SYSm 3828 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3829 Value |= op & UINT64_C(255); 3830 break; 3831 } 3832 case ARM::t2ADR: { 3833 // op: Rd 3834 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3835 Value |= (op & UINT64_C(15)) << 8; 3836 // op: addr 3837 op = getT2AdrLabelOpValue(MI, 1, Fixups, STI); 3838 Value |= (op & UINT64_C(2048)) << 15; 3839 Value |= (op & UINT64_C(4096)) << 11; 3840 Value |= (op & UINT64_C(4096)) << 9; 3841 Value |= (op & UINT64_C(1792)) << 4; 3842 Value |= op & UINT64_C(255); 3843 break; 3844 } 3845 case ARM::t2BFC: { 3846 // op: Rd 3847 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3848 Value |= (op & UINT64_C(15)) << 8; 3849 // op: imm 3850 op = getBitfieldInvertedMaskOpValue(MI, 2, Fixups, STI); 3851 Value |= (op & UINT64_C(28)) << 10; 3852 Value |= (op & UINT64_C(3)) << 6; 3853 Value |= (op & UINT64_C(992)) >> 5; 3854 break; 3855 } 3856 case ARM::t2MOVi16: { 3857 // op: Rd 3858 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3859 Value |= (op & UINT64_C(15)) << 8; 3860 // op: imm 3861 op = getHiLo16ImmOpValue(MI, 1, Fixups, STI); 3862 Value |= (op & UINT64_C(2048)) << 15; 3863 Value |= (op & UINT64_C(61440)) << 4; 3864 Value |= (op & UINT64_C(1792)) << 4; 3865 Value |= op & UINT64_C(255); 3866 break; 3867 } 3868 case ARM::t2MOVTi16: { 3869 // op: Rd 3870 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3871 Value |= (op & UINT64_C(15)) << 8; 3872 // op: imm 3873 op = getHiLo16ImmOpValue(MI, 2, Fixups, STI); 3874 Value |= (op & UINT64_C(2048)) << 15; 3875 Value |= (op & UINT64_C(61440)) << 4; 3876 Value |= (op & UINT64_C(1792)) << 4; 3877 Value |= op & UINT64_C(255); 3878 break; 3879 } 3880 case ARM::t2SBFX: 3881 case ARM::t2UBFX: { 3882 // op: Rd 3883 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3884 Value |= (op & UINT64_C(15)) << 8; 3885 // op: msb 3886 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 3887 Value |= op & UINT64_C(31); 3888 // op: lsb 3889 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3890 Value |= (op & UINT64_C(28)) << 10; 3891 Value |= (op & UINT64_C(3)) << 6; 3892 // op: Rn 3893 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3894 Value |= (op & UINT64_C(15)) << 16; 3895 break; 3896 } 3897 case ARM::tADR: { 3898 // op: Rd 3899 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3900 Value |= (op & UINT64_C(7)) << 8; 3901 // op: addr 3902 op = getThumbAdrLabelOpValue(MI, 1, Fixups, STI); 3903 Value |= op & UINT64_C(255); 3904 break; 3905 } 3906 case ARM::tMOVi8: { 3907 // op: Rd 3908 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3909 Value |= (op & UINT64_C(7)) << 8; 3910 // op: imm8 3911 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3912 Value |= op & UINT64_C(255); 3913 break; 3914 } 3915 case ARM::tMOVr: { 3916 // op: Rd 3917 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3918 Value |= (op & UINT64_C(8)) << 4; 3919 Value |= op & UINT64_C(7); 3920 // op: Rm 3921 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3922 Value |= (op & UINT64_C(15)) << 3; 3923 break; 3924 } 3925 case ARM::t2STLEX: { 3926 // op: Rd 3927 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3928 Value |= op & UINT64_C(15); 3929 // op: Rt 3930 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3931 Value |= (op & UINT64_C(15)) << 12; 3932 // op: addr 3933 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3934 Value |= (op & UINT64_C(15)) << 16; 3935 break; 3936 } 3937 case ARM::t2STLEXB: 3938 case ARM::t2STLEXH: 3939 case ARM::t2STREXB: 3940 case ARM::t2STREXH: { 3941 // op: Rd 3942 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3943 Value |= op & UINT64_C(15); 3944 // op: addr 3945 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3946 Value |= (op & UINT64_C(15)) << 16; 3947 // op: Rt 3948 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3949 Value |= (op & UINT64_C(15)) << 12; 3950 break; 3951 } 3952 case ARM::t2STLEXD: 3953 case ARM::t2STREXD: { 3954 // op: Rd 3955 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3956 Value |= op & UINT64_C(15); 3957 // op: addr 3958 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 3959 Value |= (op & UINT64_C(15)) << 16; 3960 // op: Rt 3961 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3962 Value |= (op & UINT64_C(15)) << 12; 3963 // op: Rt2 3964 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3965 Value |= (op & UINT64_C(15)) << 8; 3966 break; 3967 } 3968 case ARM::tMOVSr: { 3969 // op: Rd 3970 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3971 Value |= op & UINT64_C(7); 3972 // op: Rm 3973 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 3974 Value |= (op & UINT64_C(7)) << 3; 3975 break; 3976 } 3977 case ARM::tADDi3: 3978 case ARM::tSUBi3: { 3979 // op: Rd 3980 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3981 Value |= op & UINT64_C(7); 3982 // op: Rm 3983 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3984 Value |= (op & UINT64_C(7)) << 3; 3985 // op: imm3 3986 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 3987 Value |= (op & UINT64_C(7)) << 6; 3988 break; 3989 } 3990 case ARM::tASRri: 3991 case ARM::tLSLri: 3992 case ARM::tLSRri: { 3993 // op: Rd 3994 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 3995 Value |= op & UINT64_C(7); 3996 // op: Rm 3997 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 3998 Value |= (op & UINT64_C(7)) << 3; 3999 // op: imm5 4000 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4001 Value |= (op & UINT64_C(31)) << 6; 4002 break; 4003 } 4004 case ARM::tMUL: 4005 case ARM::tMVN: 4006 case ARM::tRSB: { 4007 // op: Rd 4008 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4009 Value |= op & UINT64_C(7); 4010 // op: Rn 4011 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4012 Value |= (op & UINT64_C(7)) << 3; 4013 break; 4014 } 4015 case ARM::t2SMLALD: 4016 case ARM::t2SMLALDX: 4017 case ARM::t2SMLSLD: 4018 case ARM::t2SMLSLDX: { 4019 // op: Rd 4020 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4021 Value |= (op & UINT64_C(15)) << 8; 4022 // op: Rn 4023 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4024 Value |= (op & UINT64_C(15)) << 16; 4025 // op: Rm 4026 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4027 Value |= op & UINT64_C(15); 4028 // op: Ra 4029 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4030 Value |= (op & UINT64_C(15)) << 12; 4031 break; 4032 } 4033 case ARM::t2SMLAL: 4034 case ARM::t2SMLALBB: 4035 case ARM::t2SMLALBT: 4036 case ARM::t2SMLALTB: 4037 case ARM::t2SMLALTT: 4038 case ARM::t2SMULL: 4039 case ARM::t2UMAAL: 4040 case ARM::t2UMLAL: 4041 case ARM::t2UMULL: { 4042 // op: RdLo 4043 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4044 Value |= (op & UINT64_C(15)) << 12; 4045 // op: RdHi 4046 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4047 Value |= (op & UINT64_C(15)) << 8; 4048 // op: Rn 4049 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4050 Value |= (op & UINT64_C(15)) << 16; 4051 // op: Rm 4052 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4053 Value |= op & UINT64_C(15); 4054 break; 4055 } 4056 case ARM::tADDi8: 4057 case ARM::tSUBi8: { 4058 // op: Rdn 4059 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4060 Value |= (op & UINT64_C(7)) << 8; 4061 // op: imm8 4062 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4063 Value |= op & UINT64_C(255); 4064 break; 4065 } 4066 case ARM::tADDrSP: { 4067 // op: Rdn 4068 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4069 Value |= (op & UINT64_C(8)) << 4; 4070 Value |= op & UINT64_C(7); 4071 break; 4072 } 4073 case ARM::tADDhirr: { 4074 // op: Rdn 4075 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4076 Value |= (op & UINT64_C(8)) << 4; 4077 Value |= op & UINT64_C(7); 4078 // op: Rm 4079 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4080 Value |= (op & UINT64_C(15)) << 3; 4081 break; 4082 } 4083 case ARM::tADC: 4084 case ARM::tAND: 4085 case ARM::tASRrr: 4086 case ARM::tBIC: 4087 case ARM::tEOR: 4088 case ARM::tLSLrr: 4089 case ARM::tLSRrr: 4090 case ARM::tORR: 4091 case ARM::tROR: 4092 case ARM::tSBC: { 4093 // op: Rdn 4094 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4095 Value |= op & UINT64_C(7); 4096 // op: Rm 4097 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4098 Value |= (op & UINT64_C(7)) << 3; 4099 break; 4100 } 4101 case ARM::tBX: 4102 case ARM::tBXNS: { 4103 // op: Rm 4104 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4105 Value |= (op & UINT64_C(15)) << 3; 4106 break; 4107 } 4108 case ARM::tCMPhir: { 4109 // op: Rm 4110 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4111 Value |= (op & UINT64_C(15)) << 3; 4112 // op: Rn 4113 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4114 Value |= (op & UINT64_C(8)) << 4; 4115 Value |= op & UINT64_C(7); 4116 break; 4117 } 4118 case ARM::tREV: 4119 case ARM::tREV16: 4120 case ARM::tREVSH: 4121 case ARM::tSXTB: 4122 case ARM::tSXTH: 4123 case ARM::tUXTB: 4124 case ARM::tUXTH: { 4125 // op: Rm 4126 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4127 Value |= (op & UINT64_C(7)) << 3; 4128 // op: Rd 4129 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4130 Value |= op & UINT64_C(7); 4131 break; 4132 } 4133 case ARM::tCMNz: 4134 case ARM::tCMPr: 4135 case ARM::tTST: { 4136 // op: Rm 4137 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4138 Value |= (op & UINT64_C(7)) << 3; 4139 // op: Rn 4140 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4141 Value |= op & UINT64_C(7); 4142 break; 4143 } 4144 case ARM::tADDspr: { 4145 // op: Rm 4146 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4147 Value |= (op & UINT64_C(15)) << 3; 4148 break; 4149 } 4150 case ARM::tADDrr: 4151 case ARM::tSUBrr: { 4152 // op: Rm 4153 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4154 Value |= (op & UINT64_C(7)) << 6; 4155 // op: Rn 4156 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4157 Value |= (op & UINT64_C(7)) << 3; 4158 // op: Rd 4159 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4160 Value |= op & UINT64_C(7); 4161 break; 4162 } 4163 case ARM::RFEDA: 4164 case ARM::RFEDA_UPD: 4165 case ARM::RFEDB: 4166 case ARM::RFEDB_UPD: 4167 case ARM::RFEIA: 4168 case ARM::RFEIA_UPD: 4169 case ARM::RFEIB: 4170 case ARM::RFEIB_UPD: 4171 case ARM::t2RFEDB: 4172 case ARM::t2RFEDBW: 4173 case ARM::t2RFEIA: 4174 case ARM::t2RFEIAW: { 4175 // op: Rn 4176 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4177 Value |= (op & UINT64_C(15)) << 16; 4178 break; 4179 } 4180 case ARM::t2CMNzrr: 4181 case ARM::t2CMPrr: 4182 case ARM::t2TBB: 4183 case ARM::t2TBH: 4184 case ARM::t2TEQrr: 4185 case ARM::t2TSTrr: { 4186 // op: Rn 4187 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4188 Value |= (op & UINT64_C(15)) << 16; 4189 // op: Rm 4190 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4191 Value |= op & UINT64_C(15); 4192 break; 4193 } 4194 case ARM::t2CMNzrs: 4195 case ARM::t2CMPrs: 4196 case ARM::t2TEQrs: 4197 case ARM::t2TSTrs: { 4198 // op: Rn 4199 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4200 Value |= (op & UINT64_C(15)) << 16; 4201 // op: ShiftedRm 4202 op = getT2SORegOpValue(MI, 1, Fixups, STI); 4203 Value |= (op & UINT64_C(3584)) << 3; 4204 Value |= (op & UINT64_C(480)) >> 1; 4205 Value |= op & UINT64_C(15); 4206 break; 4207 } 4208 case ARM::t2CMNri: 4209 case ARM::t2CMPri: 4210 case ARM::t2TEQri: 4211 case ARM::t2TSTri: { 4212 // op: Rn 4213 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4214 Value |= (op & UINT64_C(15)) << 16; 4215 // op: imm 4216 op = getT2SOImmOpValue(MI, 1, Fixups, STI); 4217 Value |= (op & UINT64_C(2048)) << 15; 4218 Value |= (op & UINT64_C(1792)) << 4; 4219 Value |= op & UINT64_C(255); 4220 break; 4221 } 4222 case ARM::t2STMDB: 4223 case ARM::t2STMIA: { 4224 // op: Rn 4225 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4226 Value |= (op & UINT64_C(15)) << 16; 4227 // op: regs 4228 op = getRegisterListOpValue(MI, 3, Fixups, STI); 4229 Value |= op & UINT64_C(16384); 4230 Value |= op & UINT64_C(8191); 4231 break; 4232 } 4233 case ARM::t2LDMDB: 4234 case ARM::t2LDMIA: { 4235 // op: Rn 4236 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4237 Value |= (op & UINT64_C(15)) << 16; 4238 // op: regs 4239 op = getRegisterListOpValue(MI, 3, Fixups, STI); 4240 Value |= op & UINT64_C(65535); 4241 break; 4242 } 4243 case ARM::tCMPi8: { 4244 // op: Rn 4245 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4246 Value |= (op & UINT64_C(7)) << 8; 4247 // op: imm8 4248 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4249 Value |= op & UINT64_C(255); 4250 break; 4251 } 4252 case ARM::tLDMIA: { 4253 // op: Rn 4254 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4255 Value |= (op & UINT64_C(7)) << 8; 4256 // op: regs 4257 op = getRegisterListOpValue(MI, 3, Fixups, STI); 4258 Value |= op & UINT64_C(255); 4259 break; 4260 } 4261 case ARM::t2TT: 4262 case ARM::t2TTA: 4263 case ARM::t2TTAT: 4264 case ARM::t2TTT: { 4265 // op: Rn 4266 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4267 Value |= (op & UINT64_C(15)) << 16; 4268 // op: Rt 4269 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4270 Value |= (op & UINT64_C(15)) << 8; 4271 break; 4272 } 4273 case ARM::t2STMDB_UPD: 4274 case ARM::t2STMIA_UPD: { 4275 // op: Rn 4276 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4277 Value |= (op & UINT64_C(15)) << 16; 4278 // op: regs 4279 op = getRegisterListOpValue(MI, 4, Fixups, STI); 4280 Value |= op & UINT64_C(16384); 4281 Value |= op & UINT64_C(8191); 4282 break; 4283 } 4284 case ARM::t2LDMDB_UPD: 4285 case ARM::t2LDMIA_UPD: { 4286 // op: Rn 4287 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4288 Value |= (op & UINT64_C(15)) << 16; 4289 // op: regs 4290 op = getRegisterListOpValue(MI, 4, Fixups, STI); 4291 Value |= op & UINT64_C(65535); 4292 break; 4293 } 4294 case ARM::tSTMIA_UPD: { 4295 // op: Rn 4296 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4297 Value |= (op & UINT64_C(7)) << 8; 4298 // op: regs 4299 op = getRegisterListOpValue(MI, 4, Fixups, STI); 4300 Value |= op & UINT64_C(255); 4301 break; 4302 } 4303 case ARM::t2LDRB_POST: 4304 case ARM::t2LDRH_POST: 4305 case ARM::t2LDRSB_POST: 4306 case ARM::t2LDRSH_POST: 4307 case ARM::t2LDR_POST: { 4308 // op: Rt 4309 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4310 Value |= (op & UINT64_C(15)) << 12; 4311 // op: Rn 4312 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4313 Value |= (op & UINT64_C(15)) << 16; 4314 // op: offset 4315 op = getT2AddrModeImm8OffsetOpValue(MI, 3, Fixups, STI); 4316 Value |= (op & UINT64_C(256)) << 1; 4317 Value |= op & UINT64_C(255); 4318 break; 4319 } 4320 case ARM::MRRC2: 4321 case ARM::t2MRRC: 4322 case ARM::t2MRRC2: { 4323 // op: Rt 4324 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4325 Value |= (op & UINT64_C(15)) << 12; 4326 // op: Rt2 4327 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4328 Value |= (op & UINT64_C(15)) << 16; 4329 // op: cop 4330 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4331 Value |= (op & UINT64_C(15)) << 8; 4332 // op: opc1 4333 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4334 Value |= (op & UINT64_C(15)) << 4; 4335 // op: CRm 4336 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 4337 Value |= op & UINT64_C(15); 4338 break; 4339 } 4340 case ARM::t2LDRD_POST: { 4341 // op: Rt 4342 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4343 Value |= (op & UINT64_C(15)) << 12; 4344 // op: Rt2 4345 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4346 Value |= (op & UINT64_C(15)) << 8; 4347 // op: addr 4348 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4349 Value |= (op & UINT64_C(15)) << 16; 4350 // op: imm 4351 op = getT2Imm8s4OpValue(MI, 4, Fixups, STI); 4352 Value |= (op & UINT64_C(256)) << 15; 4353 Value |= op & UINT64_C(255); 4354 break; 4355 } 4356 case ARM::t2LDRDi8: 4357 case ARM::t2STRDi8: { 4358 // op: Rt 4359 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4360 Value |= (op & UINT64_C(15)) << 12; 4361 // op: Rt2 4362 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4363 Value |= (op & UINT64_C(15)) << 8; 4364 // op: addr 4365 op = getT2AddrModeImm8s4OpValue(MI, 2, Fixups, STI); 4366 Value |= (op & UINT64_C(256)) << 15; 4367 Value |= (op & UINT64_C(7680)) << 7; 4368 Value |= op & UINT64_C(255); 4369 break; 4370 } 4371 case ARM::t2LDRD_PRE: { 4372 // op: Rt 4373 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4374 Value |= (op & UINT64_C(15)) << 12; 4375 // op: Rt2 4376 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4377 Value |= (op & UINT64_C(15)) << 8; 4378 // op: addr 4379 op = getT2AddrModeImm8s4OpValue(MI, 3, Fixups, STI); 4380 Value |= (op & UINT64_C(256)) << 15; 4381 Value |= (op & UINT64_C(7680)) << 7; 4382 Value |= op & UINT64_C(255); 4383 break; 4384 } 4385 case ARM::t2LDRBi12: 4386 case ARM::t2LDRHi12: 4387 case ARM::t2LDRSBi12: 4388 case ARM::t2LDRSHi12: 4389 case ARM::t2LDRi12: 4390 case ARM::t2STRBi12: 4391 case ARM::t2STRHi12: 4392 case ARM::t2STRi12: { 4393 // op: Rt 4394 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4395 Value |= (op & UINT64_C(15)) << 12; 4396 // op: addr 4397 op = getAddrModeImm12OpValue(MI, 1, Fixups, STI); 4398 Value |= (op & UINT64_C(122880)) << 3; 4399 Value |= op & UINT64_C(4095); 4400 break; 4401 } 4402 case ARM::t2LDRBpci: 4403 case ARM::t2LDRHpci: 4404 case ARM::t2LDRSBpci: 4405 case ARM::t2LDRSHpci: 4406 case ARM::t2LDRpci: { 4407 // op: Rt 4408 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4409 Value |= (op & UINT64_C(15)) << 12; 4410 // op: addr 4411 op = getAddrModeImm12OpValue(MI, 1, Fixups, STI); 4412 Value |= (op & UINT64_C(4096)) << 11; 4413 Value |= op & UINT64_C(4095); 4414 break; 4415 } 4416 case ARM::t2LDA: 4417 case ARM::t2LDAB: 4418 case ARM::t2LDAEX: 4419 case ARM::t2LDAH: 4420 case ARM::t2STL: 4421 case ARM::t2STLB: 4422 case ARM::t2STLH: { 4423 // op: Rt 4424 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4425 Value |= (op & UINT64_C(15)) << 12; 4426 // op: addr 4427 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4428 Value |= (op & UINT64_C(15)) << 16; 4429 break; 4430 } 4431 case ARM::t2LDREX: { 4432 // op: Rt 4433 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4434 Value |= (op & UINT64_C(15)) << 12; 4435 // op: addr 4436 op = getT2AddrModeImm0_1020s4OpValue(MI, 1, Fixups, STI); 4437 Value |= (op & UINT64_C(3840)) << 8; 4438 Value |= op & UINT64_C(255); 4439 break; 4440 } 4441 case ARM::t2LDRBi8: 4442 case ARM::t2LDRHi8: 4443 case ARM::t2LDRSBi8: 4444 case ARM::t2LDRSHi8: 4445 case ARM::t2LDRi8: 4446 case ARM::t2STRBi8: 4447 case ARM::t2STRHi8: 4448 case ARM::t2STRi8: { 4449 // op: Rt 4450 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4451 Value |= (op & UINT64_C(15)) << 12; 4452 // op: addr 4453 op = getT2AddrModeImm8OpValue(MI, 1, Fixups, STI); 4454 Value |= (op & UINT64_C(7680)) << 7; 4455 Value |= (op & UINT64_C(256)) << 1; 4456 Value |= op & UINT64_C(255); 4457 break; 4458 } 4459 case ARM::t2LDRBT: 4460 case ARM::t2LDRHT: 4461 case ARM::t2LDRSBT: 4462 case ARM::t2LDRSHT: 4463 case ARM::t2LDRT: 4464 case ARM::t2STRBT: 4465 case ARM::t2STRHT: 4466 case ARM::t2STRT: { 4467 // op: Rt 4468 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4469 Value |= (op & UINT64_C(15)) << 12; 4470 // op: addr 4471 op = getT2AddrModeImm8OpValue(MI, 1, Fixups, STI); 4472 Value |= (op & UINT64_C(7680)) << 7; 4473 Value |= op & UINT64_C(255); 4474 break; 4475 } 4476 case ARM::t2LDRB_PRE: 4477 case ARM::t2LDRH_PRE: 4478 case ARM::t2LDRSB_PRE: 4479 case ARM::t2LDRSH_PRE: 4480 case ARM::t2LDR_PRE: { 4481 // op: Rt 4482 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4483 Value |= (op & UINT64_C(15)) << 12; 4484 // op: addr 4485 op = getT2AddrModeImm8OpValue(MI, 2, Fixups, STI); 4486 Value |= (op & UINT64_C(7680)) << 7; 4487 Value |= (op & UINT64_C(256)) << 1; 4488 Value |= op & UINT64_C(255); 4489 break; 4490 } 4491 case ARM::t2LDRBs: 4492 case ARM::t2LDRHs: 4493 case ARM::t2LDRSBs: 4494 case ARM::t2LDRSHs: 4495 case ARM::t2LDRs: 4496 case ARM::t2STRBs: 4497 case ARM::t2STRHs: 4498 case ARM::t2STRs: { 4499 // op: Rt 4500 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4501 Value |= (op & UINT64_C(15)) << 12; 4502 // op: addr 4503 op = getT2AddrModeSORegOpValue(MI, 1, Fixups, STI); 4504 Value |= (op & UINT64_C(960)) << 10; 4505 Value |= (op & UINT64_C(3)) << 4; 4506 Value |= (op & UINT64_C(60)) >> 2; 4507 break; 4508 } 4509 case ARM::MRC2: 4510 case ARM::t2MRC: 4511 case ARM::t2MRC2: { 4512 // op: Rt 4513 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4514 Value |= (op & UINT64_C(15)) << 12; 4515 // op: cop 4516 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4517 Value |= (op & UINT64_C(15)) << 8; 4518 // op: opc1 4519 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4520 Value |= (op & UINT64_C(7)) << 21; 4521 // op: opc2 4522 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 4523 Value |= (op & UINT64_C(7)) << 5; 4524 // op: CRm 4525 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 4526 Value |= op & UINT64_C(15); 4527 // op: CRn 4528 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4529 Value |= (op & UINT64_C(15)) << 16; 4530 break; 4531 } 4532 case ARM::tLDRpci: { 4533 // op: Rt 4534 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4535 Value |= (op & UINT64_C(7)) << 8; 4536 // op: addr 4537 op = getAddrModePCOpValue(MI, 1, Fixups, STI); 4538 Value |= op & UINT64_C(255); 4539 break; 4540 } 4541 case ARM::tLDRspi: 4542 case ARM::tSTRspi: { 4543 // op: Rt 4544 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4545 Value |= (op & UINT64_C(7)) << 8; 4546 // op: addr 4547 op = getAddrModeThumbSPOpValue(MI, 1, Fixups, STI); 4548 Value |= op & UINT64_C(255); 4549 break; 4550 } 4551 case ARM::tLDRBi: 4552 case ARM::tLDRHi: 4553 case ARM::tLDRi: 4554 case ARM::tSTRBi: 4555 case ARM::tSTRHi: 4556 case ARM::tSTRi: { 4557 // op: Rt 4558 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4559 Value |= op & UINT64_C(7); 4560 // op: addr 4561 op = getAddrModeISOpValue(MI, 1, Fixups, STI); 4562 Value |= (op & UINT64_C(255)) << 3; 4563 break; 4564 } 4565 case ARM::tLDRBr: 4566 case ARM::tLDRHr: 4567 case ARM::tLDRSB: 4568 case ARM::tLDRSH: 4569 case ARM::tLDRr: 4570 case ARM::tSTRBr: 4571 case ARM::tSTRHr: 4572 case ARM::tSTRr: { 4573 // op: Rt 4574 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4575 Value |= op & UINT64_C(7); 4576 // op: addr 4577 op = getThumbAddrModeRegRegOpValue(MI, 1, Fixups, STI); 4578 Value |= (op & UINT64_C(63)) << 3; 4579 break; 4580 } 4581 case ARM::t2STRB_POST: 4582 case ARM::t2STRH_POST: 4583 case ARM::t2STR_POST: { 4584 // op: Rt 4585 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4586 Value |= (op & UINT64_C(15)) << 12; 4587 // op: Rn 4588 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4589 Value |= (op & UINT64_C(15)) << 16; 4590 // op: offset 4591 op = getT2AddrModeImm8OffsetOpValue(MI, 3, Fixups, STI); 4592 Value |= (op & UINT64_C(256)) << 1; 4593 Value |= op & UINT64_C(255); 4594 break; 4595 } 4596 case ARM::t2STRD_POST: { 4597 // op: Rt 4598 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4599 Value |= (op & UINT64_C(15)) << 12; 4600 // op: Rt2 4601 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4602 Value |= (op & UINT64_C(15)) << 8; 4603 // op: addr 4604 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4605 Value |= (op & UINT64_C(15)) << 16; 4606 // op: imm 4607 op = getT2Imm8s4OpValue(MI, 4, Fixups, STI); 4608 Value |= (op & UINT64_C(256)) << 15; 4609 Value |= op & UINT64_C(255); 4610 break; 4611 } 4612 case ARM::t2STRD_PRE: { 4613 // op: Rt 4614 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4615 Value |= (op & UINT64_C(15)) << 12; 4616 // op: Rt2 4617 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4618 Value |= (op & UINT64_C(15)) << 8; 4619 // op: addr 4620 op = getT2AddrModeImm8s4OpValue(MI, 3, Fixups, STI); 4621 Value |= (op & UINT64_C(256)) << 15; 4622 Value |= (op & UINT64_C(7680)) << 7; 4623 Value |= op & UINT64_C(255); 4624 break; 4625 } 4626 case ARM::t2STRB_PRE: 4627 case ARM::t2STRH_PRE: 4628 case ARM::t2STR_PRE: { 4629 // op: Rt 4630 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4631 Value |= (op & UINT64_C(15)) << 12; 4632 // op: addr 4633 op = getT2AddrModeImm8OpValue(MI, 2, Fixups, STI); 4634 Value |= (op & UINT64_C(7680)) << 7; 4635 Value |= (op & UINT64_C(256)) << 1; 4636 Value |= op & UINT64_C(255); 4637 break; 4638 } 4639 case ARM::MCRR2: 4640 case ARM::t2MCRR: 4641 case ARM::t2MCRR2: { 4642 // op: Rt 4643 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4644 Value |= (op & UINT64_C(15)) << 12; 4645 // op: Rt2 4646 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4647 Value |= (op & UINT64_C(15)) << 16; 4648 // op: cop 4649 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4650 Value |= (op & UINT64_C(15)) << 8; 4651 // op: opc1 4652 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4653 Value |= (op & UINT64_C(15)) << 4; 4654 // op: CRm 4655 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 4656 Value |= op & UINT64_C(15); 4657 break; 4658 } 4659 case ARM::MCR2: 4660 case ARM::t2MCR: 4661 case ARM::t2MCR2: { 4662 // op: Rt 4663 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4664 Value |= (op & UINT64_C(15)) << 12; 4665 // op: cop 4666 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4667 Value |= (op & UINT64_C(15)) << 8; 4668 // op: opc1 4669 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4670 Value |= (op & UINT64_C(7)) << 21; 4671 // op: opc2 4672 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 4673 Value |= (op & UINT64_C(7)) << 5; 4674 // op: CRm 4675 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 4676 Value |= op & UINT64_C(15); 4677 // op: CRn 4678 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4679 Value |= (op & UINT64_C(15)) << 16; 4680 break; 4681 } 4682 case ARM::t2MSR_M: { 4683 // op: SYSm 4684 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4685 Value |= op & UINT64_C(3072); 4686 Value |= op & UINT64_C(255); 4687 // op: Rn 4688 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4689 Value |= (op & UINT64_C(15)) << 16; 4690 break; 4691 } 4692 case ARM::VCVTASD: 4693 case ARM::VCVTAUD: 4694 case ARM::VCVTMSD: 4695 case ARM::VCVTMUD: 4696 case ARM::VCVTNSD: 4697 case ARM::VCVTNUD: 4698 case ARM::VCVTPSD: 4699 case ARM::VCVTPUD: { 4700 // op: Sd 4701 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4702 Value |= (op & UINT64_C(1)) << 22; 4703 Value |= (op & UINT64_C(30)) << 11; 4704 // op: Dm 4705 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4706 Value |= (op & UINT64_C(16)) << 1; 4707 Value |= op & UINT64_C(15); 4708 break; 4709 } 4710 case ARM::VCVTASH: 4711 case ARM::VCVTASS: 4712 case ARM::VCVTAUH: 4713 case ARM::VCVTAUS: 4714 case ARM::VCVTMSH: 4715 case ARM::VCVTMSS: 4716 case ARM::VCVTMUH: 4717 case ARM::VCVTMUS: 4718 case ARM::VCVTNSH: 4719 case ARM::VCVTNSS: 4720 case ARM::VCVTNUH: 4721 case ARM::VCVTNUS: 4722 case ARM::VCVTPSH: 4723 case ARM::VCVTPSS: 4724 case ARM::VCVTPUH: 4725 case ARM::VCVTPUS: 4726 case ARM::VINSH: 4727 case ARM::VMOVH: 4728 case ARM::VRINTAH: 4729 case ARM::VRINTAS: 4730 case ARM::VRINTMH: 4731 case ARM::VRINTMS: 4732 case ARM::VRINTNH: 4733 case ARM::VRINTNS: 4734 case ARM::VRINTPH: 4735 case ARM::VRINTPS: { 4736 // op: Sd 4737 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4738 Value |= (op & UINT64_C(1)) << 22; 4739 Value |= (op & UINT64_C(30)) << 11; 4740 // op: Sm 4741 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4742 Value |= (op & UINT64_C(1)) << 5; 4743 Value |= (op & UINT64_C(30)) >> 1; 4744 break; 4745 } 4746 case ARM::VMAXNMH: 4747 case ARM::VMAXNMS: 4748 case ARM::VMINNMH: 4749 case ARM::VMINNMS: 4750 case ARM::VSELEQH: 4751 case ARM::VSELEQS: 4752 case ARM::VSELGEH: 4753 case ARM::VSELGES: 4754 case ARM::VSELGTH: 4755 case ARM::VSELGTS: 4756 case ARM::VSELVSH: 4757 case ARM::VSELVSS: { 4758 // op: Sd 4759 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4760 Value |= (op & UINT64_C(1)) << 22; 4761 Value |= (op & UINT64_C(30)) << 11; 4762 // op: Sn 4763 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4764 Value |= (op & UINT64_C(30)) << 15; 4765 Value |= (op & UINT64_C(1)) << 7; 4766 // op: Sm 4767 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4768 Value |= (op & UINT64_C(1)) << 5; 4769 Value |= (op & UINT64_C(30)) >> 1; 4770 break; 4771 } 4772 case ARM::VDUP16d: 4773 case ARM::VDUP16q: 4774 case ARM::VDUP32d: 4775 case ARM::VDUP32q: 4776 case ARM::VDUP8d: 4777 case ARM::VDUP8q: { 4778 // op: V 4779 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4780 Value |= (op & UINT64_C(15)) << 16; 4781 Value |= (op & UINT64_C(16)) << 3; 4782 // op: R 4783 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4784 Value |= (op & UINT64_C(15)) << 12; 4785 // op: p 4786 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4787 Value |= (op & UINT64_C(15)) << 28; 4788 Value = NEONThumb2DupPostEncoder(MI, Value, STI); 4789 break; 4790 } 4791 case ARM::VSETLNi32: { 4792 // op: V 4793 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4794 Value |= (op & UINT64_C(15)) << 16; 4795 Value |= (op & UINT64_C(16)) << 3; 4796 // op: R 4797 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4798 Value |= (op & UINT64_C(15)) << 12; 4799 // op: p 4800 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 4801 Value |= (op & UINT64_C(15)) << 28; 4802 // op: lane 4803 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4804 Value |= (op & UINT64_C(1)) << 21; 4805 Value = NEONThumb2DupPostEncoder(MI, Value, STI); 4806 break; 4807 } 4808 case ARM::VSETLNi16: { 4809 // op: V 4810 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4811 Value |= (op & UINT64_C(15)) << 16; 4812 Value |= (op & UINT64_C(16)) << 3; 4813 // op: R 4814 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4815 Value |= (op & UINT64_C(15)) << 12; 4816 // op: p 4817 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 4818 Value |= (op & UINT64_C(15)) << 28; 4819 // op: lane 4820 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4821 Value |= (op & UINT64_C(2)) << 20; 4822 Value |= (op & UINT64_C(1)) << 6; 4823 Value = NEONThumb2DupPostEncoder(MI, Value, STI); 4824 break; 4825 } 4826 case ARM::VSETLNi8: { 4827 // op: V 4828 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4829 Value |= (op & UINT64_C(15)) << 16; 4830 Value |= (op & UINT64_C(16)) << 3; 4831 // op: R 4832 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4833 Value |= (op & UINT64_C(15)) << 12; 4834 // op: p 4835 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 4836 Value |= (op & UINT64_C(15)) << 28; 4837 // op: lane 4838 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4839 Value |= (op & UINT64_C(4)) << 19; 4840 Value |= (op & UINT64_C(3)) << 5; 4841 Value = NEONThumb2DupPostEncoder(MI, Value, STI); 4842 break; 4843 } 4844 case ARM::VGETLNi32: { 4845 // op: V 4846 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4847 Value |= (op & UINT64_C(15)) << 16; 4848 Value |= (op & UINT64_C(16)) << 3; 4849 // op: R 4850 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4851 Value |= (op & UINT64_C(15)) << 12; 4852 // op: p 4853 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4854 Value |= (op & UINT64_C(15)) << 28; 4855 // op: lane 4856 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4857 Value |= (op & UINT64_C(1)) << 21; 4858 Value = NEONThumb2DupPostEncoder(MI, Value, STI); 4859 break; 4860 } 4861 case ARM::VGETLNs16: 4862 case ARM::VGETLNu16: { 4863 // op: V 4864 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4865 Value |= (op & UINT64_C(15)) << 16; 4866 Value |= (op & UINT64_C(16)) << 3; 4867 // op: R 4868 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4869 Value |= (op & UINT64_C(15)) << 12; 4870 // op: p 4871 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4872 Value |= (op & UINT64_C(15)) << 28; 4873 // op: lane 4874 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4875 Value |= (op & UINT64_C(2)) << 20; 4876 Value |= (op & UINT64_C(1)) << 6; 4877 Value = NEONThumb2DupPostEncoder(MI, Value, STI); 4878 break; 4879 } 4880 case ARM::VGETLNs8: 4881 case ARM::VGETLNu8: { 4882 // op: V 4883 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 4884 Value |= (op & UINT64_C(15)) << 16; 4885 Value |= (op & UINT64_C(16)) << 3; 4886 // op: R 4887 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4888 Value |= (op & UINT64_C(15)) << 12; 4889 // op: p 4890 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 4891 Value |= (op & UINT64_C(15)) << 28; 4892 // op: lane 4893 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 4894 Value |= (op & UINT64_C(4)) << 19; 4895 Value |= (op & UINT64_C(3)) << 5; 4896 Value = NEONThumb2DupPostEncoder(MI, Value, STI); 4897 break; 4898 } 4899 case ARM::VLD1LNd8: { 4900 // op: Vd 4901 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4902 Value |= (op & UINT64_C(16)) << 18; 4903 Value |= (op & UINT64_C(15)) << 12; 4904 // op: Rn 4905 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 4906 Value |= (op & UINT64_C(15)) << 16; 4907 // op: lane 4908 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 4909 Value |= (op & UINT64_C(7)) << 5; 4910 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 4911 break; 4912 } 4913 case ARM::VLD1d16: 4914 case ARM::VLD1d16T: 4915 case ARM::VLD1d32: 4916 case ARM::VLD1d32T: 4917 case ARM::VLD1d64: 4918 case ARM::VLD1d64T: 4919 case ARM::VLD1d8: 4920 case ARM::VLD1d8T: { 4921 // op: Vd 4922 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4923 Value |= (op & UINT64_C(16)) << 18; 4924 Value |= (op & UINT64_C(15)) << 12; 4925 // op: Rn 4926 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 4927 Value |= (op & UINT64_C(15)) << 16; 4928 Value |= op & UINT64_C(16); 4929 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 4930 break; 4931 } 4932 case ARM::VLD1LNd16: { 4933 // op: Vd 4934 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4935 Value |= (op & UINT64_C(16)) << 18; 4936 Value |= (op & UINT64_C(15)) << 12; 4937 // op: Rn 4938 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 4939 Value |= (op & UINT64_C(15)) << 16; 4940 Value |= op & UINT64_C(48); 4941 // op: lane 4942 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 4943 Value |= (op & UINT64_C(3)) << 6; 4944 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 4945 break; 4946 } 4947 case ARM::VLD1d16Q: 4948 case ARM::VLD1d32Q: 4949 case ARM::VLD1d64Q: 4950 case ARM::VLD1d8Q: 4951 case ARM::VLD1q16: 4952 case ARM::VLD1q32: 4953 case ARM::VLD1q64: 4954 case ARM::VLD1q8: 4955 case ARM::VLD2b16: 4956 case ARM::VLD2b32: 4957 case ARM::VLD2b8: 4958 case ARM::VLD2d16: 4959 case ARM::VLD2d32: 4960 case ARM::VLD2d8: 4961 case ARM::VLD2q16: 4962 case ARM::VLD2q32: 4963 case ARM::VLD2q8: { 4964 // op: Vd 4965 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4966 Value |= (op & UINT64_C(16)) << 18; 4967 Value |= (op & UINT64_C(15)) << 12; 4968 // op: Rn 4969 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 4970 Value |= (op & UINT64_C(15)) << 16; 4971 Value |= op & UINT64_C(48); 4972 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 4973 break; 4974 } 4975 case ARM::VLD1LNd8_UPD: { 4976 // op: Vd 4977 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4978 Value |= (op & UINT64_C(16)) << 18; 4979 Value |= (op & UINT64_C(15)) << 12; 4980 // op: Rn 4981 op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI); 4982 Value |= (op & UINT64_C(15)) << 16; 4983 // op: Rm 4984 op = getAddrMode6OffsetOpValue(MI, 4, Fixups, STI); 4985 Value |= op & UINT64_C(15); 4986 // op: lane 4987 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 4988 Value |= (op & UINT64_C(7)) << 5; 4989 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 4990 break; 4991 } 4992 case ARM::VLD1LNd32_UPD: { 4993 // op: Vd 4994 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 4995 Value |= (op & UINT64_C(16)) << 18; 4996 Value |= (op & UINT64_C(15)) << 12; 4997 // op: Rn 4998 op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI); 4999 Value |= (op & UINT64_C(15)) << 16; 5000 Value |= (op & UINT64_C(16)) << 1; 5001 Value |= op & UINT64_C(16); 5002 // op: Rm 5003 op = getAddrMode6OffsetOpValue(MI, 4, Fixups, STI); 5004 Value |= op & UINT64_C(15); 5005 // op: lane 5006 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 5007 Value |= (op & UINT64_C(1)) << 7; 5008 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5009 break; 5010 } 5011 case ARM::VLD1LNd16_UPD: { 5012 // op: Vd 5013 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5014 Value |= (op & UINT64_C(16)) << 18; 5015 Value |= (op & UINT64_C(15)) << 12; 5016 // op: Rn 5017 op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI); 5018 Value |= (op & UINT64_C(15)) << 16; 5019 Value |= op & UINT64_C(16); 5020 // op: Rm 5021 op = getAddrMode6OffsetOpValue(MI, 4, Fixups, STI); 5022 Value |= op & UINT64_C(15); 5023 // op: lane 5024 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 5025 Value |= (op & UINT64_C(3)) << 6; 5026 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5027 break; 5028 } 5029 case ARM::VLD1d16Twb_register: 5030 case ARM::VLD1d16wb_register: 5031 case ARM::VLD1d32Twb_register: 5032 case ARM::VLD1d32wb_register: 5033 case ARM::VLD1d64Twb_register: 5034 case ARM::VLD1d64wb_register: 5035 case ARM::VLD1d8Twb_register: 5036 case ARM::VLD1d8wb_register: { 5037 // op: Vd 5038 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5039 Value |= (op & UINT64_C(16)) << 18; 5040 Value |= (op & UINT64_C(15)) << 12; 5041 // op: Rn 5042 op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI); 5043 Value |= (op & UINT64_C(15)) << 16; 5044 Value |= op & UINT64_C(16); 5045 // op: Rm 5046 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 5047 Value |= op & UINT64_C(15); 5048 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5049 break; 5050 } 5051 case ARM::VLD2LNd32: 5052 case ARM::VLD2LNq32: { 5053 // op: Vd 5054 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5055 Value |= (op & UINT64_C(16)) << 18; 5056 Value |= (op & UINT64_C(15)) << 12; 5057 // op: Rn 5058 op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI); 5059 Value |= (op & UINT64_C(15)) << 16; 5060 Value |= op & UINT64_C(16); 5061 // op: lane 5062 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 5063 Value |= (op & UINT64_C(1)) << 7; 5064 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5065 break; 5066 } 5067 case ARM::VLD2LNd16: 5068 case ARM::VLD2LNq16: { 5069 // op: Vd 5070 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5071 Value |= (op & UINT64_C(16)) << 18; 5072 Value |= (op & UINT64_C(15)) << 12; 5073 // op: Rn 5074 op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI); 5075 Value |= (op & UINT64_C(15)) << 16; 5076 Value |= op & UINT64_C(16); 5077 // op: lane 5078 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 5079 Value |= (op & UINT64_C(3)) << 6; 5080 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5081 break; 5082 } 5083 case ARM::VLD2LNd8: { 5084 // op: Vd 5085 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5086 Value |= (op & UINT64_C(16)) << 18; 5087 Value |= (op & UINT64_C(15)) << 12; 5088 // op: Rn 5089 op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI); 5090 Value |= (op & UINT64_C(15)) << 16; 5091 Value |= op & UINT64_C(16); 5092 // op: lane 5093 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 5094 Value |= (op & UINT64_C(7)) << 5; 5095 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5096 break; 5097 } 5098 case ARM::VLD1d16Twb_fixed: 5099 case ARM::VLD1d16wb_fixed: 5100 case ARM::VLD1d32Twb_fixed: 5101 case ARM::VLD1d32wb_fixed: 5102 case ARM::VLD1d64Twb_fixed: 5103 case ARM::VLD1d64wb_fixed: 5104 case ARM::VLD1d8Twb_fixed: 5105 case ARM::VLD1d8wb_fixed: { 5106 // op: Vd 5107 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5108 Value |= (op & UINT64_C(16)) << 18; 5109 Value |= (op & UINT64_C(15)) << 12; 5110 // op: Rn 5111 op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI); 5112 Value |= (op & UINT64_C(15)) << 16; 5113 Value |= op & UINT64_C(16); 5114 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5115 break; 5116 } 5117 case ARM::VLD1d16Qwb_register: 5118 case ARM::VLD1d32Qwb_register: 5119 case ARM::VLD1d64Qwb_register: 5120 case ARM::VLD1d8Qwb_register: 5121 case ARM::VLD1q16wb_register: 5122 case ARM::VLD1q32wb_register: 5123 case ARM::VLD1q64wb_register: 5124 case ARM::VLD1q8wb_register: 5125 case ARM::VLD2b16wb_register: 5126 case ARM::VLD2b32wb_register: 5127 case ARM::VLD2b8wb_register: 5128 case ARM::VLD2d16wb_register: 5129 case ARM::VLD2d32wb_register: 5130 case ARM::VLD2d8wb_register: 5131 case ARM::VLD2q16wb_register: 5132 case ARM::VLD2q32wb_register: 5133 case ARM::VLD2q8wb_register: { 5134 // op: Vd 5135 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5136 Value |= (op & UINT64_C(16)) << 18; 5137 Value |= (op & UINT64_C(15)) << 12; 5138 // op: Rn 5139 op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI); 5140 Value |= (op & UINT64_C(15)) << 16; 5141 Value |= op & UINT64_C(48); 5142 // op: Rm 5143 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 5144 Value |= op & UINT64_C(15); 5145 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5146 break; 5147 } 5148 case ARM::VLD1d16Qwb_fixed: 5149 case ARM::VLD1d32Qwb_fixed: 5150 case ARM::VLD1d64Qwb_fixed: 5151 case ARM::VLD1d8Qwb_fixed: 5152 case ARM::VLD1q16wb_fixed: 5153 case ARM::VLD1q32wb_fixed: 5154 case ARM::VLD1q64wb_fixed: 5155 case ARM::VLD1q8wb_fixed: 5156 case ARM::VLD2b16wb_fixed: 5157 case ARM::VLD2b32wb_fixed: 5158 case ARM::VLD2b8wb_fixed: 5159 case ARM::VLD2d16wb_fixed: 5160 case ARM::VLD2d32wb_fixed: 5161 case ARM::VLD2d8wb_fixed: 5162 case ARM::VLD2q16wb_fixed: 5163 case ARM::VLD2q32wb_fixed: 5164 case ARM::VLD2q8wb_fixed: { 5165 // op: Vd 5166 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5167 Value |= (op & UINT64_C(16)) << 18; 5168 Value |= (op & UINT64_C(15)) << 12; 5169 // op: Rn 5170 op = getAddrMode6AddressOpValue(MI, 2, Fixups, STI); 5171 Value |= (op & UINT64_C(15)) << 16; 5172 Value |= op & UINT64_C(48); 5173 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5174 break; 5175 } 5176 case ARM::VLD3LNd32: 5177 case ARM::VLD3LNq32: { 5178 // op: Vd 5179 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5180 Value |= (op & UINT64_C(16)) << 18; 5181 Value |= (op & UINT64_C(15)) << 12; 5182 // op: Rn 5183 op = getAddrMode6AddressOpValue(MI, 3, Fixups, STI); 5184 Value |= (op & UINT64_C(15)) << 16; 5185 // op: lane 5186 op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI); 5187 Value |= (op & UINT64_C(1)) << 7; 5188 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5189 break; 5190 } 5191 case ARM::VLD3LNd16: 5192 case ARM::VLD3LNq16: { 5193 // op: Vd 5194 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5195 Value |= (op & UINT64_C(16)) << 18; 5196 Value |= (op & UINT64_C(15)) << 12; 5197 // op: Rn 5198 op = getAddrMode6AddressOpValue(MI, 3, Fixups, STI); 5199 Value |= (op & UINT64_C(15)) << 16; 5200 // op: lane 5201 op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI); 5202 Value |= (op & UINT64_C(3)) << 6; 5203 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5204 break; 5205 } 5206 case ARM::VLD3LNd8: { 5207 // op: Vd 5208 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5209 Value |= (op & UINT64_C(16)) << 18; 5210 Value |= (op & UINT64_C(15)) << 12; 5211 // op: Rn 5212 op = getAddrMode6AddressOpValue(MI, 3, Fixups, STI); 5213 Value |= (op & UINT64_C(15)) << 16; 5214 // op: lane 5215 op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI); 5216 Value |= (op & UINT64_C(7)) << 5; 5217 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5218 break; 5219 } 5220 case ARM::VLD2LNd32_UPD: 5221 case ARM::VLD2LNq32_UPD: { 5222 // op: Vd 5223 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5224 Value |= (op & UINT64_C(16)) << 18; 5225 Value |= (op & UINT64_C(15)) << 12; 5226 // op: Rn 5227 op = getAddrMode6AddressOpValue(MI, 3, Fixups, STI); 5228 Value |= (op & UINT64_C(15)) << 16; 5229 Value |= op & UINT64_C(16); 5230 // op: Rm 5231 op = getAddrMode6OffsetOpValue(MI, 5, Fixups, STI); 5232 Value |= op & UINT64_C(15); 5233 // op: lane 5234 op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI); 5235 Value |= (op & UINT64_C(1)) << 7; 5236 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5237 break; 5238 } 5239 case ARM::VLD2LNd16_UPD: 5240 case ARM::VLD2LNq16_UPD: { 5241 // op: Vd 5242 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5243 Value |= (op & UINT64_C(16)) << 18; 5244 Value |= (op & UINT64_C(15)) << 12; 5245 // op: Rn 5246 op = getAddrMode6AddressOpValue(MI, 3, Fixups, STI); 5247 Value |= (op & UINT64_C(15)) << 16; 5248 Value |= op & UINT64_C(16); 5249 // op: Rm 5250 op = getAddrMode6OffsetOpValue(MI, 5, Fixups, STI); 5251 Value |= op & UINT64_C(15); 5252 // op: lane 5253 op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI); 5254 Value |= (op & UINT64_C(3)) << 6; 5255 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5256 break; 5257 } 5258 case ARM::VLD2LNd8_UPD: { 5259 // op: Vd 5260 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5261 Value |= (op & UINT64_C(16)) << 18; 5262 Value |= (op & UINT64_C(15)) << 12; 5263 // op: Rn 5264 op = getAddrMode6AddressOpValue(MI, 3, Fixups, STI); 5265 Value |= (op & UINT64_C(15)) << 16; 5266 Value |= op & UINT64_C(16); 5267 // op: Rm 5268 op = getAddrMode6OffsetOpValue(MI, 5, Fixups, STI); 5269 Value |= op & UINT64_C(15); 5270 // op: lane 5271 op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI); 5272 Value |= (op & UINT64_C(7)) << 5; 5273 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5274 break; 5275 } 5276 case ARM::VLD3d16: 5277 case ARM::VLD3d32: 5278 case ARM::VLD3d8: 5279 case ARM::VLD3q16: 5280 case ARM::VLD3q32: 5281 case ARM::VLD3q8: { 5282 // op: Vd 5283 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5284 Value |= (op & UINT64_C(16)) << 18; 5285 Value |= (op & UINT64_C(15)) << 12; 5286 // op: Rn 5287 op = getAddrMode6AddressOpValue(MI, 3, Fixups, STI); 5288 Value |= (op & UINT64_C(15)) << 16; 5289 Value |= op & UINT64_C(16); 5290 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5291 break; 5292 } 5293 case ARM::VLD3LNd32_UPD: 5294 case ARM::VLD3LNq32_UPD: { 5295 // op: Vd 5296 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5297 Value |= (op & UINT64_C(16)) << 18; 5298 Value |= (op & UINT64_C(15)) << 12; 5299 // op: Rn 5300 op = getAddrMode6AddressOpValue(MI, 4, Fixups, STI); 5301 Value |= (op & UINT64_C(15)) << 16; 5302 // op: Rm 5303 op = getAddrMode6OffsetOpValue(MI, 6, Fixups, STI); 5304 Value |= op & UINT64_C(15); 5305 // op: lane 5306 op = getMachineOpValue(MI, MI.getOperand(10), Fixups, STI); 5307 Value |= (op & UINT64_C(1)) << 7; 5308 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5309 break; 5310 } 5311 case ARM::VLD3LNd16_UPD: 5312 case ARM::VLD3LNq16_UPD: { 5313 // op: Vd 5314 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5315 Value |= (op & UINT64_C(16)) << 18; 5316 Value |= (op & UINT64_C(15)) << 12; 5317 // op: Rn 5318 op = getAddrMode6AddressOpValue(MI, 4, Fixups, STI); 5319 Value |= (op & UINT64_C(15)) << 16; 5320 // op: Rm 5321 op = getAddrMode6OffsetOpValue(MI, 6, Fixups, STI); 5322 Value |= op & UINT64_C(15); 5323 // op: lane 5324 op = getMachineOpValue(MI, MI.getOperand(10), Fixups, STI); 5325 Value |= (op & UINT64_C(3)) << 6; 5326 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5327 break; 5328 } 5329 case ARM::VLD3LNd8_UPD: { 5330 // op: Vd 5331 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5332 Value |= (op & UINT64_C(16)) << 18; 5333 Value |= (op & UINT64_C(15)) << 12; 5334 // op: Rn 5335 op = getAddrMode6AddressOpValue(MI, 4, Fixups, STI); 5336 Value |= (op & UINT64_C(15)) << 16; 5337 // op: Rm 5338 op = getAddrMode6OffsetOpValue(MI, 6, Fixups, STI); 5339 Value |= op & UINT64_C(15); 5340 // op: lane 5341 op = getMachineOpValue(MI, MI.getOperand(10), Fixups, STI); 5342 Value |= (op & UINT64_C(7)) << 5; 5343 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5344 break; 5345 } 5346 case ARM::VLD3d16_UPD: 5347 case ARM::VLD3d32_UPD: 5348 case ARM::VLD3d8_UPD: 5349 case ARM::VLD3q16_UPD: 5350 case ARM::VLD3q32_UPD: 5351 case ARM::VLD3q8_UPD: { 5352 // op: Vd 5353 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5354 Value |= (op & UINT64_C(16)) << 18; 5355 Value |= (op & UINT64_C(15)) << 12; 5356 // op: Rn 5357 op = getAddrMode6AddressOpValue(MI, 4, Fixups, STI); 5358 Value |= (op & UINT64_C(15)) << 16; 5359 Value |= op & UINT64_C(16); 5360 // op: Rm 5361 op = getAddrMode6OffsetOpValue(MI, 6, Fixups, STI); 5362 Value |= op & UINT64_C(15); 5363 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5364 break; 5365 } 5366 case ARM::VLD4LNd16: 5367 case ARM::VLD4LNq16: { 5368 // op: Vd 5369 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5370 Value |= (op & UINT64_C(16)) << 18; 5371 Value |= (op & UINT64_C(15)) << 12; 5372 // op: Rn 5373 op = getAddrMode6AddressOpValue(MI, 4, Fixups, STI); 5374 Value |= (op & UINT64_C(15)) << 16; 5375 Value |= op & UINT64_C(16); 5376 // op: lane 5377 op = getMachineOpValue(MI, MI.getOperand(10), Fixups, STI); 5378 Value |= (op & UINT64_C(3)) << 6; 5379 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5380 break; 5381 } 5382 case ARM::VLD4LNd8: { 5383 // op: Vd 5384 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5385 Value |= (op & UINT64_C(16)) << 18; 5386 Value |= (op & UINT64_C(15)) << 12; 5387 // op: Rn 5388 op = getAddrMode6AddressOpValue(MI, 4, Fixups, STI); 5389 Value |= (op & UINT64_C(15)) << 16; 5390 Value |= op & UINT64_C(16); 5391 // op: lane 5392 op = getMachineOpValue(MI, MI.getOperand(10), Fixups, STI); 5393 Value |= (op & UINT64_C(7)) << 5; 5394 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5395 break; 5396 } 5397 case ARM::VLD4LNd32: 5398 case ARM::VLD4LNq32: { 5399 // op: Vd 5400 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5401 Value |= (op & UINT64_C(16)) << 18; 5402 Value |= (op & UINT64_C(15)) << 12; 5403 // op: Rn 5404 op = getAddrMode6AddressOpValue(MI, 4, Fixups, STI); 5405 Value |= (op & UINT64_C(15)) << 16; 5406 Value |= op & UINT64_C(48); 5407 // op: lane 5408 op = getMachineOpValue(MI, MI.getOperand(10), Fixups, STI); 5409 Value |= (op & UINT64_C(1)) << 7; 5410 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5411 break; 5412 } 5413 case ARM::VLD4d16: 5414 case ARM::VLD4d32: 5415 case ARM::VLD4d8: 5416 case ARM::VLD4q16: 5417 case ARM::VLD4q32: 5418 case ARM::VLD4q8: { 5419 // op: Vd 5420 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5421 Value |= (op & UINT64_C(16)) << 18; 5422 Value |= (op & UINT64_C(15)) << 12; 5423 // op: Rn 5424 op = getAddrMode6AddressOpValue(MI, 4, Fixups, STI); 5425 Value |= (op & UINT64_C(15)) << 16; 5426 Value |= op & UINT64_C(48); 5427 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5428 break; 5429 } 5430 case ARM::VLD4LNd16_UPD: 5431 case ARM::VLD4LNq16_UPD: { 5432 // op: Vd 5433 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5434 Value |= (op & UINT64_C(16)) << 18; 5435 Value |= (op & UINT64_C(15)) << 12; 5436 // op: Rn 5437 op = getAddrMode6AddressOpValue(MI, 5, Fixups, STI); 5438 Value |= (op & UINT64_C(15)) << 16; 5439 Value |= op & UINT64_C(16); 5440 // op: Rm 5441 op = getAddrMode6OffsetOpValue(MI, 7, Fixups, STI); 5442 Value |= op & UINT64_C(15); 5443 // op: lane 5444 op = getMachineOpValue(MI, MI.getOperand(12), Fixups, STI); 5445 Value |= (op & UINT64_C(3)) << 6; 5446 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5447 break; 5448 } 5449 case ARM::VLD4LNd8_UPD: { 5450 // op: Vd 5451 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5452 Value |= (op & UINT64_C(16)) << 18; 5453 Value |= (op & UINT64_C(15)) << 12; 5454 // op: Rn 5455 op = getAddrMode6AddressOpValue(MI, 5, Fixups, STI); 5456 Value |= (op & UINT64_C(15)) << 16; 5457 Value |= op & UINT64_C(16); 5458 // op: Rm 5459 op = getAddrMode6OffsetOpValue(MI, 7, Fixups, STI); 5460 Value |= op & UINT64_C(15); 5461 // op: lane 5462 op = getMachineOpValue(MI, MI.getOperand(12), Fixups, STI); 5463 Value |= (op & UINT64_C(7)) << 5; 5464 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5465 break; 5466 } 5467 case ARM::VLD4LNd32_UPD: 5468 case ARM::VLD4LNq32_UPD: { 5469 // op: Vd 5470 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5471 Value |= (op & UINT64_C(16)) << 18; 5472 Value |= (op & UINT64_C(15)) << 12; 5473 // op: Rn 5474 op = getAddrMode6AddressOpValue(MI, 5, Fixups, STI); 5475 Value |= (op & UINT64_C(15)) << 16; 5476 Value |= op & UINT64_C(48); 5477 // op: Rm 5478 op = getAddrMode6OffsetOpValue(MI, 7, Fixups, STI); 5479 Value |= op & UINT64_C(15); 5480 // op: lane 5481 op = getMachineOpValue(MI, MI.getOperand(12), Fixups, STI); 5482 Value |= (op & UINT64_C(1)) << 7; 5483 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5484 break; 5485 } 5486 case ARM::VLD4d16_UPD: 5487 case ARM::VLD4d32_UPD: 5488 case ARM::VLD4d8_UPD: 5489 case ARM::VLD4q16_UPD: 5490 case ARM::VLD4q32_UPD: 5491 case ARM::VLD4q8_UPD: { 5492 // op: Vd 5493 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5494 Value |= (op & UINT64_C(16)) << 18; 5495 Value |= (op & UINT64_C(15)) << 12; 5496 // op: Rn 5497 op = getAddrMode6AddressOpValue(MI, 5, Fixups, STI); 5498 Value |= (op & UINT64_C(15)) << 16; 5499 Value |= op & UINT64_C(48); 5500 // op: Rm 5501 op = getAddrMode6OffsetOpValue(MI, 7, Fixups, STI); 5502 Value |= op & UINT64_C(15); 5503 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5504 break; 5505 } 5506 case ARM::VLD1DUPd16: 5507 case ARM::VLD1DUPd32: 5508 case ARM::VLD1DUPd8: 5509 case ARM::VLD1DUPq16: 5510 case ARM::VLD1DUPq32: 5511 case ARM::VLD1DUPq8: 5512 case ARM::VLD2DUPd16: 5513 case ARM::VLD2DUPd16x2: 5514 case ARM::VLD2DUPd32: 5515 case ARM::VLD2DUPd32x2: 5516 case ARM::VLD2DUPd8: 5517 case ARM::VLD2DUPd8x2: { 5518 // op: Vd 5519 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5520 Value |= (op & UINT64_C(16)) << 18; 5521 Value |= (op & UINT64_C(15)) << 12; 5522 // op: Rn 5523 op = getAddrMode6DupAddressOpValue(MI, 1, Fixups, STI); 5524 Value |= (op & UINT64_C(15)) << 16; 5525 Value |= op & UINT64_C(16); 5526 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5527 break; 5528 } 5529 case ARM::VLD1DUPd16wb_register: 5530 case ARM::VLD1DUPd32wb_register: 5531 case ARM::VLD1DUPd8wb_register: 5532 case ARM::VLD1DUPq16wb_register: 5533 case ARM::VLD1DUPq32wb_register: 5534 case ARM::VLD1DUPq8wb_register: 5535 case ARM::VLD2DUPd16wb_register: 5536 case ARM::VLD2DUPd16x2wb_register: 5537 case ARM::VLD2DUPd32wb_register: 5538 case ARM::VLD2DUPd32x2wb_register: 5539 case ARM::VLD2DUPd8wb_register: 5540 case ARM::VLD2DUPd8x2wb_register: { 5541 // op: Vd 5542 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5543 Value |= (op & UINT64_C(16)) << 18; 5544 Value |= (op & UINT64_C(15)) << 12; 5545 // op: Rn 5546 op = getAddrMode6DupAddressOpValue(MI, 2, Fixups, STI); 5547 Value |= (op & UINT64_C(15)) << 16; 5548 Value |= op & UINT64_C(16); 5549 // op: Rm 5550 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 5551 Value |= op & UINT64_C(15); 5552 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5553 break; 5554 } 5555 case ARM::VLD1DUPd16wb_fixed: 5556 case ARM::VLD1DUPd32wb_fixed: 5557 case ARM::VLD1DUPd8wb_fixed: 5558 case ARM::VLD1DUPq16wb_fixed: 5559 case ARM::VLD1DUPq32wb_fixed: 5560 case ARM::VLD1DUPq8wb_fixed: 5561 case ARM::VLD2DUPd16wb_fixed: 5562 case ARM::VLD2DUPd16x2wb_fixed: 5563 case ARM::VLD2DUPd32wb_fixed: 5564 case ARM::VLD2DUPd32x2wb_fixed: 5565 case ARM::VLD2DUPd8wb_fixed: 5566 case ARM::VLD2DUPd8x2wb_fixed: { 5567 // op: Vd 5568 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5569 Value |= (op & UINT64_C(16)) << 18; 5570 Value |= (op & UINT64_C(15)) << 12; 5571 // op: Rn 5572 op = getAddrMode6DupAddressOpValue(MI, 2, Fixups, STI); 5573 Value |= (op & UINT64_C(15)) << 16; 5574 Value |= op & UINT64_C(16); 5575 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5576 break; 5577 } 5578 case ARM::VLD3DUPd16: 5579 case ARM::VLD3DUPd32: 5580 case ARM::VLD3DUPd8: 5581 case ARM::VLD3DUPq16: 5582 case ARM::VLD3DUPq32: 5583 case ARM::VLD3DUPq8: { 5584 // op: Vd 5585 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5586 Value |= (op & UINT64_C(16)) << 18; 5587 Value |= (op & UINT64_C(15)) << 12; 5588 // op: Rn 5589 op = getAddrMode6DupAddressOpValue(MI, 3, Fixups, STI); 5590 Value |= (op & UINT64_C(15)) << 16; 5591 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5592 break; 5593 } 5594 case ARM::VLD3DUPd16_UPD: 5595 case ARM::VLD3DUPd32_UPD: 5596 case ARM::VLD3DUPd8_UPD: 5597 case ARM::VLD3DUPq16_UPD: 5598 case ARM::VLD3DUPq32_UPD: 5599 case ARM::VLD3DUPq8_UPD: { 5600 // op: Vd 5601 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5602 Value |= (op & UINT64_C(16)) << 18; 5603 Value |= (op & UINT64_C(15)) << 12; 5604 // op: Rn 5605 op = getAddrMode6DupAddressOpValue(MI, 4, Fixups, STI); 5606 Value |= (op & UINT64_C(15)) << 16; 5607 // op: Rm 5608 op = getAddrMode6OffsetOpValue(MI, 6, Fixups, STI); 5609 Value |= op & UINT64_C(15); 5610 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5611 break; 5612 } 5613 case ARM::VLD4DUPd32: 5614 case ARM::VLD4DUPq32: { 5615 // op: Vd 5616 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5617 Value |= (op & UINT64_C(16)) << 18; 5618 Value |= (op & UINT64_C(15)) << 12; 5619 // op: Rn 5620 op = getAddrMode6DupAddressOpValue(MI, 4, Fixups, STI); 5621 Value |= (op & UINT64_C(15)) << 16; 5622 Value |= (op & UINT64_C(32)) << 1; 5623 Value |= op & UINT64_C(16); 5624 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5625 break; 5626 } 5627 case ARM::VLD4DUPd16: 5628 case ARM::VLD4DUPd8: 5629 case ARM::VLD4DUPq16: 5630 case ARM::VLD4DUPq8: { 5631 // op: Vd 5632 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5633 Value |= (op & UINT64_C(16)) << 18; 5634 Value |= (op & UINT64_C(15)) << 12; 5635 // op: Rn 5636 op = getAddrMode6DupAddressOpValue(MI, 4, Fixups, STI); 5637 Value |= (op & UINT64_C(15)) << 16; 5638 Value |= op & UINT64_C(16); 5639 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5640 break; 5641 } 5642 case ARM::VLD4DUPd32_UPD: 5643 case ARM::VLD4DUPq32_UPD: { 5644 // op: Vd 5645 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5646 Value |= (op & UINT64_C(16)) << 18; 5647 Value |= (op & UINT64_C(15)) << 12; 5648 // op: Rn 5649 op = getAddrMode6DupAddressOpValue(MI, 5, Fixups, STI); 5650 Value |= (op & UINT64_C(15)) << 16; 5651 Value |= (op & UINT64_C(32)) << 1; 5652 Value |= op & UINT64_C(16); 5653 // op: Rm 5654 op = getAddrMode6OffsetOpValue(MI, 7, Fixups, STI); 5655 Value |= op & UINT64_C(15); 5656 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5657 break; 5658 } 5659 case ARM::VLD4DUPd16_UPD: 5660 case ARM::VLD4DUPd8_UPD: 5661 case ARM::VLD4DUPq16_UPD: 5662 case ARM::VLD4DUPq8_UPD: { 5663 // op: Vd 5664 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5665 Value |= (op & UINT64_C(16)) << 18; 5666 Value |= (op & UINT64_C(15)) << 12; 5667 // op: Rn 5668 op = getAddrMode6DupAddressOpValue(MI, 5, Fixups, STI); 5669 Value |= (op & UINT64_C(15)) << 16; 5670 Value |= op & UINT64_C(16); 5671 // op: Rm 5672 op = getAddrMode6OffsetOpValue(MI, 7, Fixups, STI); 5673 Value |= op & UINT64_C(15); 5674 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5675 break; 5676 } 5677 case ARM::VLD1LNd32: { 5678 // op: Vd 5679 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5680 Value |= (op & UINT64_C(16)) << 18; 5681 Value |= (op & UINT64_C(15)) << 12; 5682 // op: Rn 5683 op = getAddrMode6OneLane32AddressOpValue(MI, 1, Fixups, STI); 5684 Value |= (op & UINT64_C(15)) << 16; 5685 Value |= op & UINT64_C(48); 5686 // op: lane 5687 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 5688 Value |= (op & UINT64_C(1)) << 7; 5689 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 5690 break; 5691 } 5692 case ARM::VMOVv16i8: 5693 case ARM::VMOVv1i64: 5694 case ARM::VMOVv2f32: 5695 case ARM::VMOVv2i64: 5696 case ARM::VMOVv4f32: 5697 case ARM::VMOVv8i8: { 5698 // op: Vd 5699 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5700 Value |= (op & UINT64_C(16)) << 18; 5701 Value |= (op & UINT64_C(15)) << 12; 5702 // op: SIMM 5703 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5704 Value |= (op & UINT64_C(128)) << 17; 5705 Value |= (op & UINT64_C(112)) << 12; 5706 Value |= op & UINT64_C(15); 5707 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 5708 break; 5709 } 5710 case ARM::VBICiv2i32: 5711 case ARM::VBICiv4i32: 5712 case ARM::VORRiv2i32: 5713 case ARM::VORRiv4i32: { 5714 // op: Vd 5715 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5716 Value |= (op & UINT64_C(16)) << 18; 5717 Value |= (op & UINT64_C(15)) << 12; 5718 // op: SIMM 5719 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5720 Value |= (op & UINT64_C(128)) << 17; 5721 Value |= (op & UINT64_C(112)) << 12; 5722 Value |= op & UINT64_C(1536); 5723 Value |= op & UINT64_C(15); 5724 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 5725 break; 5726 } 5727 case ARM::VMOVv2i32: 5728 case ARM::VMOVv4i32: 5729 case ARM::VMVNv2i32: 5730 case ARM::VMVNv4i32: { 5731 // op: Vd 5732 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5733 Value |= (op & UINT64_C(16)) << 18; 5734 Value |= (op & UINT64_C(15)) << 12; 5735 // op: SIMM 5736 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5737 Value |= (op & UINT64_C(128)) << 17; 5738 Value |= (op & UINT64_C(112)) << 12; 5739 Value |= op & UINT64_C(3840); 5740 Value |= op & UINT64_C(15); 5741 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 5742 break; 5743 } 5744 case ARM::VBICiv4i16: 5745 case ARM::VBICiv8i16: 5746 case ARM::VMOVv4i16: 5747 case ARM::VMOVv8i16: 5748 case ARM::VMVNv4i16: 5749 case ARM::VMVNv8i16: 5750 case ARM::VORRiv4i16: 5751 case ARM::VORRiv8i16: { 5752 // op: Vd 5753 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5754 Value |= (op & UINT64_C(16)) << 18; 5755 Value |= (op & UINT64_C(15)) << 12; 5756 // op: SIMM 5757 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5758 Value |= (op & UINT64_C(128)) << 17; 5759 Value |= (op & UINT64_C(112)) << 12; 5760 Value |= op & UINT64_C(512); 5761 Value |= op & UINT64_C(15); 5762 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 5763 break; 5764 } 5765 case ARM::VQSHLsiv4i16: 5766 case ARM::VQSHLsiv8i16: 5767 case ARM::VQSHLsuv4i16: 5768 case ARM::VQSHLsuv8i16: 5769 case ARM::VQSHLuiv4i16: 5770 case ARM::VQSHLuiv8i16: 5771 case ARM::VSHLLsv4i32: 5772 case ARM::VSHLLuv4i32: 5773 case ARM::VSHLiv4i16: 5774 case ARM::VSHLiv8i16: { 5775 // op: Vd 5776 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5777 Value |= (op & UINT64_C(16)) << 18; 5778 Value |= (op & UINT64_C(15)) << 12; 5779 // op: Vm 5780 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5781 Value |= (op & UINT64_C(16)) << 1; 5782 Value |= op & UINT64_C(15); 5783 // op: SIMM 5784 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5785 Value |= (op & UINT64_C(15)) << 16; 5786 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 5787 break; 5788 } 5789 case ARM::VQSHLsiv2i32: 5790 case ARM::VQSHLsiv4i32: 5791 case ARM::VQSHLsuv2i32: 5792 case ARM::VQSHLsuv4i32: 5793 case ARM::VQSHLuiv2i32: 5794 case ARM::VQSHLuiv4i32: 5795 case ARM::VSHLLsv2i64: 5796 case ARM::VSHLLuv2i64: 5797 case ARM::VSHLiv2i32: 5798 case ARM::VSHLiv4i32: { 5799 // op: Vd 5800 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5801 Value |= (op & UINT64_C(16)) << 18; 5802 Value |= (op & UINT64_C(15)) << 12; 5803 // op: Vm 5804 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5805 Value |= (op & UINT64_C(16)) << 1; 5806 Value |= op & UINT64_C(15); 5807 // op: SIMM 5808 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5809 Value |= (op & UINT64_C(31)) << 16; 5810 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 5811 break; 5812 } 5813 case ARM::VQSHLsiv1i64: 5814 case ARM::VQSHLsiv2i64: 5815 case ARM::VQSHLsuv1i64: 5816 case ARM::VQSHLsuv2i64: 5817 case ARM::VQSHLuiv1i64: 5818 case ARM::VQSHLuiv2i64: 5819 case ARM::VSHLiv1i64: 5820 case ARM::VSHLiv2i64: { 5821 // op: Vd 5822 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5823 Value |= (op & UINT64_C(16)) << 18; 5824 Value |= (op & UINT64_C(15)) << 12; 5825 // op: Vm 5826 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5827 Value |= (op & UINT64_C(16)) << 1; 5828 Value |= op & UINT64_C(15); 5829 // op: SIMM 5830 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5831 Value |= (op & UINT64_C(63)) << 16; 5832 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 5833 break; 5834 } 5835 case ARM::VQSHLsiv16i8: 5836 case ARM::VQSHLsiv8i8: 5837 case ARM::VQSHLsuv16i8: 5838 case ARM::VQSHLsuv8i8: 5839 case ARM::VQSHLuiv16i8: 5840 case ARM::VQSHLuiv8i8: 5841 case ARM::VSHLLsv8i16: 5842 case ARM::VSHLLuv8i16: 5843 case ARM::VSHLiv16i8: 5844 case ARM::VSHLiv8i8: { 5845 // op: Vd 5846 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5847 Value |= (op & UINT64_C(16)) << 18; 5848 Value |= (op & UINT64_C(15)) << 12; 5849 // op: Vm 5850 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5851 Value |= (op & UINT64_C(16)) << 1; 5852 Value |= op & UINT64_C(15); 5853 // op: SIMM 5854 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 5855 Value |= (op & UINT64_C(7)) << 16; 5856 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 5857 break; 5858 } 5859 case ARM::VCVTf2xsd: 5860 case ARM::VCVTf2xsq: 5861 case ARM::VCVTf2xud: 5862 case ARM::VCVTf2xuq: 5863 case ARM::VCVTh2xsd: 5864 case ARM::VCVTh2xsq: 5865 case ARM::VCVTh2xud: 5866 case ARM::VCVTh2xuq: 5867 case ARM::VCVTxs2fd: 5868 case ARM::VCVTxs2fq: 5869 case ARM::VCVTxs2hd: 5870 case ARM::VCVTxs2hq: 5871 case ARM::VCVTxu2fd: 5872 case ARM::VCVTxu2fq: 5873 case ARM::VCVTxu2hd: 5874 case ARM::VCVTxu2hq: { 5875 // op: Vd 5876 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5877 Value |= (op & UINT64_C(16)) << 18; 5878 Value |= (op & UINT64_C(15)) << 12; 5879 // op: Vm 5880 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5881 Value |= (op & UINT64_C(16)) << 1; 5882 Value |= op & UINT64_C(15); 5883 // op: SIMM 5884 op = getNEONVcvtImm32OpValue(MI, 2, Fixups, STI); 5885 Value |= (op & UINT64_C(63)) << 16; 5886 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 5887 break; 5888 } 5889 case ARM::VQRSHRNsv4i16: 5890 case ARM::VQRSHRNuv4i16: 5891 case ARM::VQRSHRUNv4i16: 5892 case ARM::VQSHRNsv4i16: 5893 case ARM::VQSHRNuv4i16: 5894 case ARM::VQSHRUNv4i16: 5895 case ARM::VRSHRNv4i16: 5896 case ARM::VRSHRsv4i16: 5897 case ARM::VRSHRsv8i16: 5898 case ARM::VRSHRuv4i16: 5899 case ARM::VRSHRuv8i16: 5900 case ARM::VSHRNv4i16: 5901 case ARM::VSHRsv4i16: 5902 case ARM::VSHRsv8i16: 5903 case ARM::VSHRuv4i16: 5904 case ARM::VSHRuv8i16: { 5905 // op: Vd 5906 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5907 Value |= (op & UINT64_C(16)) << 18; 5908 Value |= (op & UINT64_C(15)) << 12; 5909 // op: Vm 5910 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5911 Value |= (op & UINT64_C(16)) << 1; 5912 Value |= op & UINT64_C(15); 5913 // op: SIMM 5914 op = getShiftRight16Imm(MI, 2, Fixups, STI); 5915 Value |= (op & UINT64_C(15)) << 16; 5916 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 5917 break; 5918 } 5919 case ARM::VQRSHRNsv2i32: 5920 case ARM::VQRSHRNuv2i32: 5921 case ARM::VQRSHRUNv2i32: 5922 case ARM::VQSHRNsv2i32: 5923 case ARM::VQSHRNuv2i32: 5924 case ARM::VQSHRUNv2i32: 5925 case ARM::VRSHRNv2i32: 5926 case ARM::VRSHRsv2i32: 5927 case ARM::VRSHRsv4i32: 5928 case ARM::VRSHRuv2i32: 5929 case ARM::VRSHRuv4i32: 5930 case ARM::VSHRNv2i32: 5931 case ARM::VSHRsv2i32: 5932 case ARM::VSHRsv4i32: 5933 case ARM::VSHRuv2i32: 5934 case ARM::VSHRuv4i32: { 5935 // op: Vd 5936 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5937 Value |= (op & UINT64_C(16)) << 18; 5938 Value |= (op & UINT64_C(15)) << 12; 5939 // op: Vm 5940 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5941 Value |= (op & UINT64_C(16)) << 1; 5942 Value |= op & UINT64_C(15); 5943 // op: SIMM 5944 op = getShiftRight32Imm(MI, 2, Fixups, STI); 5945 Value |= (op & UINT64_C(31)) << 16; 5946 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 5947 break; 5948 } 5949 case ARM::VRSHRsv1i64: 5950 case ARM::VRSHRsv2i64: 5951 case ARM::VRSHRuv1i64: 5952 case ARM::VRSHRuv2i64: 5953 case ARM::VSHRsv1i64: 5954 case ARM::VSHRsv2i64: 5955 case ARM::VSHRuv1i64: 5956 case ARM::VSHRuv2i64: { 5957 // op: Vd 5958 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5959 Value |= (op & UINT64_C(16)) << 18; 5960 Value |= (op & UINT64_C(15)) << 12; 5961 // op: Vm 5962 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5963 Value |= (op & UINT64_C(16)) << 1; 5964 Value |= op & UINT64_C(15); 5965 // op: SIMM 5966 op = getShiftRight64Imm(MI, 2, Fixups, STI); 5967 Value |= (op & UINT64_C(63)) << 16; 5968 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 5969 break; 5970 } 5971 case ARM::VQRSHRNsv8i8: 5972 case ARM::VQRSHRNuv8i8: 5973 case ARM::VQRSHRUNv8i8: 5974 case ARM::VQSHRNsv8i8: 5975 case ARM::VQSHRNuv8i8: 5976 case ARM::VQSHRUNv8i8: 5977 case ARM::VRSHRNv8i8: 5978 case ARM::VRSHRsv16i8: 5979 case ARM::VRSHRsv8i8: 5980 case ARM::VRSHRuv16i8: 5981 case ARM::VRSHRuv8i8: 5982 case ARM::VSHRNv8i8: 5983 case ARM::VSHRsv16i8: 5984 case ARM::VSHRsv8i8: 5985 case ARM::VSHRuv16i8: 5986 case ARM::VSHRuv8i8: { 5987 // op: Vd 5988 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 5989 Value |= (op & UINT64_C(16)) << 18; 5990 Value |= (op & UINT64_C(15)) << 12; 5991 // op: Vm 5992 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 5993 Value |= (op & UINT64_C(16)) << 1; 5994 Value |= op & UINT64_C(15); 5995 // op: SIMM 5996 op = getShiftRight8Imm(MI, 2, Fixups, STI); 5997 Value |= (op & UINT64_C(7)) << 16; 5998 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 5999 break; 6000 } 6001 case ARM::VDUPLN32d: 6002 case ARM::VDUPLN32q: { 6003 // op: Vd 6004 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6005 Value |= (op & UINT64_C(16)) << 18; 6006 Value |= (op & UINT64_C(15)) << 12; 6007 // op: Vm 6008 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6009 Value |= (op & UINT64_C(16)) << 1; 6010 Value |= op & UINT64_C(15); 6011 // op: lane 6012 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6013 Value |= (op & UINT64_C(1)) << 19; 6014 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 6015 break; 6016 } 6017 case ARM::VDUPLN16d: 6018 case ARM::VDUPLN16q: { 6019 // op: Vd 6020 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6021 Value |= (op & UINT64_C(16)) << 18; 6022 Value |= (op & UINT64_C(15)) << 12; 6023 // op: Vm 6024 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6025 Value |= (op & UINT64_C(16)) << 1; 6026 Value |= op & UINT64_C(15); 6027 // op: lane 6028 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6029 Value |= (op & UINT64_C(3)) << 18; 6030 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 6031 break; 6032 } 6033 case ARM::VDUPLN8d: 6034 case ARM::VDUPLN8q: { 6035 // op: Vd 6036 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6037 Value |= (op & UINT64_C(16)) << 18; 6038 Value |= (op & UINT64_C(15)) << 12; 6039 // op: Vm 6040 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6041 Value |= (op & UINT64_C(16)) << 1; 6042 Value |= op & UINT64_C(15); 6043 // op: lane 6044 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6045 Value |= (op & UINT64_C(7)) << 17; 6046 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 6047 break; 6048 } 6049 case ARM::AESIMC: 6050 case ARM::AESMC: 6051 case ARM::SHA1H: 6052 case ARM::VABSfd: 6053 case ARM::VABSfq: 6054 case ARM::VABShd: 6055 case ARM::VABShq: 6056 case ARM::VABSv16i8: 6057 case ARM::VABSv2i32: 6058 case ARM::VABSv4i16: 6059 case ARM::VABSv4i32: 6060 case ARM::VABSv8i16: 6061 case ARM::VABSv8i8: 6062 case ARM::VCEQzv16i8: 6063 case ARM::VCEQzv2f32: 6064 case ARM::VCEQzv2i32: 6065 case ARM::VCEQzv4f16: 6066 case ARM::VCEQzv4f32: 6067 case ARM::VCEQzv4i16: 6068 case ARM::VCEQzv4i32: 6069 case ARM::VCEQzv8f16: 6070 case ARM::VCEQzv8i16: 6071 case ARM::VCEQzv8i8: 6072 case ARM::VCGEzv16i8: 6073 case ARM::VCGEzv2f32: 6074 case ARM::VCGEzv2i32: 6075 case ARM::VCGEzv4f16: 6076 case ARM::VCGEzv4f32: 6077 case ARM::VCGEzv4i16: 6078 case ARM::VCGEzv4i32: 6079 case ARM::VCGEzv8f16: 6080 case ARM::VCGEzv8i16: 6081 case ARM::VCGEzv8i8: 6082 case ARM::VCGTzv16i8: 6083 case ARM::VCGTzv2f32: 6084 case ARM::VCGTzv2i32: 6085 case ARM::VCGTzv4f16: 6086 case ARM::VCGTzv4f32: 6087 case ARM::VCGTzv4i16: 6088 case ARM::VCGTzv4i32: 6089 case ARM::VCGTzv8f16: 6090 case ARM::VCGTzv8i16: 6091 case ARM::VCGTzv8i8: 6092 case ARM::VCLEzv16i8: 6093 case ARM::VCLEzv2f32: 6094 case ARM::VCLEzv2i32: 6095 case ARM::VCLEzv4f16: 6096 case ARM::VCLEzv4f32: 6097 case ARM::VCLEzv4i16: 6098 case ARM::VCLEzv4i32: 6099 case ARM::VCLEzv8f16: 6100 case ARM::VCLEzv8i16: 6101 case ARM::VCLEzv8i8: 6102 case ARM::VCLSv16i8: 6103 case ARM::VCLSv2i32: 6104 case ARM::VCLSv4i16: 6105 case ARM::VCLSv4i32: 6106 case ARM::VCLSv8i16: 6107 case ARM::VCLSv8i8: 6108 case ARM::VCLTzv16i8: 6109 case ARM::VCLTzv2f32: 6110 case ARM::VCLTzv2i32: 6111 case ARM::VCLTzv4f16: 6112 case ARM::VCLTzv4f32: 6113 case ARM::VCLTzv4i16: 6114 case ARM::VCLTzv4i32: 6115 case ARM::VCLTzv8f16: 6116 case ARM::VCLTzv8i16: 6117 case ARM::VCLTzv8i8: 6118 case ARM::VCLZv16i8: 6119 case ARM::VCLZv2i32: 6120 case ARM::VCLZv4i16: 6121 case ARM::VCLZv4i32: 6122 case ARM::VCLZv8i16: 6123 case ARM::VCLZv8i8: 6124 case ARM::VCNTd: 6125 case ARM::VCNTq: 6126 case ARM::VCVTf2h: 6127 case ARM::VCVTf2sd: 6128 case ARM::VCVTf2sq: 6129 case ARM::VCVTf2ud: 6130 case ARM::VCVTf2uq: 6131 case ARM::VCVTh2f: 6132 case ARM::VCVTh2sd: 6133 case ARM::VCVTh2sq: 6134 case ARM::VCVTh2ud: 6135 case ARM::VCVTh2uq: 6136 case ARM::VCVTs2fd: 6137 case ARM::VCVTs2fq: 6138 case ARM::VCVTs2hd: 6139 case ARM::VCVTs2hq: 6140 case ARM::VCVTu2fd: 6141 case ARM::VCVTu2fq: 6142 case ARM::VCVTu2hd: 6143 case ARM::VCVTu2hq: 6144 case ARM::VMOVLsv2i64: 6145 case ARM::VMOVLsv4i32: 6146 case ARM::VMOVLsv8i16: 6147 case ARM::VMOVLuv2i64: 6148 case ARM::VMOVLuv4i32: 6149 case ARM::VMOVLuv8i16: 6150 case ARM::VMOVNv2i32: 6151 case ARM::VMOVNv4i16: 6152 case ARM::VMOVNv8i8: 6153 case ARM::VMVNd: 6154 case ARM::VMVNq: 6155 case ARM::VNEGf32q: 6156 case ARM::VNEGfd: 6157 case ARM::VNEGhd: 6158 case ARM::VNEGhq: 6159 case ARM::VNEGs16d: 6160 case ARM::VNEGs16q: 6161 case ARM::VNEGs32d: 6162 case ARM::VNEGs32q: 6163 case ARM::VNEGs8d: 6164 case ARM::VNEGs8q: 6165 case ARM::VPADDLsv16i8: 6166 case ARM::VPADDLsv2i32: 6167 case ARM::VPADDLsv4i16: 6168 case ARM::VPADDLsv4i32: 6169 case ARM::VPADDLsv8i16: 6170 case ARM::VPADDLsv8i8: 6171 case ARM::VPADDLuv16i8: 6172 case ARM::VPADDLuv2i32: 6173 case ARM::VPADDLuv4i16: 6174 case ARM::VPADDLuv4i32: 6175 case ARM::VPADDLuv8i16: 6176 case ARM::VPADDLuv8i8: 6177 case ARM::VQABSv16i8: 6178 case ARM::VQABSv2i32: 6179 case ARM::VQABSv4i16: 6180 case ARM::VQABSv4i32: 6181 case ARM::VQABSv8i16: 6182 case ARM::VQABSv8i8: 6183 case ARM::VQMOVNsuv2i32: 6184 case ARM::VQMOVNsuv4i16: 6185 case ARM::VQMOVNsuv8i8: 6186 case ARM::VQMOVNsv2i32: 6187 case ARM::VQMOVNsv4i16: 6188 case ARM::VQMOVNsv8i8: 6189 case ARM::VQMOVNuv2i32: 6190 case ARM::VQMOVNuv4i16: 6191 case ARM::VQMOVNuv8i8: 6192 case ARM::VQNEGv16i8: 6193 case ARM::VQNEGv2i32: 6194 case ARM::VQNEGv4i16: 6195 case ARM::VQNEGv4i32: 6196 case ARM::VQNEGv8i16: 6197 case ARM::VQNEGv8i8: 6198 case ARM::VRECPEd: 6199 case ARM::VRECPEfd: 6200 case ARM::VRECPEfq: 6201 case ARM::VRECPEhd: 6202 case ARM::VRECPEhq: 6203 case ARM::VRECPEq: 6204 case ARM::VREV16d8: 6205 case ARM::VREV16q8: 6206 case ARM::VREV32d16: 6207 case ARM::VREV32d8: 6208 case ARM::VREV32q16: 6209 case ARM::VREV32q8: 6210 case ARM::VREV64d16: 6211 case ARM::VREV64d32: 6212 case ARM::VREV64d8: 6213 case ARM::VREV64q16: 6214 case ARM::VREV64q32: 6215 case ARM::VREV64q8: 6216 case ARM::VRSQRTEd: 6217 case ARM::VRSQRTEfd: 6218 case ARM::VRSQRTEfq: 6219 case ARM::VRSQRTEhd: 6220 case ARM::VRSQRTEhq: 6221 case ARM::VRSQRTEq: 6222 case ARM::VSHLLi16: 6223 case ARM::VSHLLi32: 6224 case ARM::VSHLLi8: 6225 case ARM::VSWPd: 6226 case ARM::VSWPq: 6227 case ARM::VTRNd16: 6228 case ARM::VTRNd32: 6229 case ARM::VTRNd8: 6230 case ARM::VTRNq16: 6231 case ARM::VTRNq32: 6232 case ARM::VTRNq8: 6233 case ARM::VUZPd16: 6234 case ARM::VUZPd8: 6235 case ARM::VUZPq16: 6236 case ARM::VUZPq32: 6237 case ARM::VUZPq8: 6238 case ARM::VZIPd16: 6239 case ARM::VZIPd8: 6240 case ARM::VZIPq16: 6241 case ARM::VZIPq32: 6242 case ARM::VZIPq8: { 6243 // op: Vd 6244 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6245 Value |= (op & UINT64_C(16)) << 18; 6246 Value |= (op & UINT64_C(15)) << 12; 6247 // op: Vm 6248 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6249 Value |= (op & UINT64_C(16)) << 1; 6250 Value |= op & UINT64_C(15); 6251 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 6252 break; 6253 } 6254 case ARM::VCVTANSDf: 6255 case ARM::VCVTANSDh: 6256 case ARM::VCVTANSQf: 6257 case ARM::VCVTANSQh: 6258 case ARM::VCVTANUDf: 6259 case ARM::VCVTANUDh: 6260 case ARM::VCVTANUQf: 6261 case ARM::VCVTANUQh: 6262 case ARM::VCVTMNSDf: 6263 case ARM::VCVTMNSDh: 6264 case ARM::VCVTMNSQf: 6265 case ARM::VCVTMNSQh: 6266 case ARM::VCVTMNUDf: 6267 case ARM::VCVTMNUDh: 6268 case ARM::VCVTMNUQf: 6269 case ARM::VCVTMNUQh: 6270 case ARM::VCVTNNSDf: 6271 case ARM::VCVTNNSDh: 6272 case ARM::VCVTNNSQf: 6273 case ARM::VCVTNNSQh: 6274 case ARM::VCVTNNUDf: 6275 case ARM::VCVTNNUDh: 6276 case ARM::VCVTNNUQf: 6277 case ARM::VCVTNNUQh: 6278 case ARM::VCVTPNSDf: 6279 case ARM::VCVTPNSDh: 6280 case ARM::VCVTPNSQf: 6281 case ARM::VCVTPNSQh: 6282 case ARM::VCVTPNUDf: 6283 case ARM::VCVTPNUDh: 6284 case ARM::VCVTPNUQf: 6285 case ARM::VCVTPNUQh: 6286 case ARM::VRINTANDf: 6287 case ARM::VRINTANDh: 6288 case ARM::VRINTANQf: 6289 case ARM::VRINTANQh: 6290 case ARM::VRINTMNDf: 6291 case ARM::VRINTMNDh: 6292 case ARM::VRINTMNQf: 6293 case ARM::VRINTMNQh: 6294 case ARM::VRINTNNDf: 6295 case ARM::VRINTNNDh: 6296 case ARM::VRINTNNQf: 6297 case ARM::VRINTNNQh: 6298 case ARM::VRINTPNDf: 6299 case ARM::VRINTPNDh: 6300 case ARM::VRINTPNQf: 6301 case ARM::VRINTPNQh: 6302 case ARM::VRINTXNDf: 6303 case ARM::VRINTXNDh: 6304 case ARM::VRINTXNQf: 6305 case ARM::VRINTXNQh: 6306 case ARM::VRINTZNDf: 6307 case ARM::VRINTZNDh: 6308 case ARM::VRINTZNQf: 6309 case ARM::VRINTZNQh: { 6310 // op: Vd 6311 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6312 Value |= (op & UINT64_C(16)) << 18; 6313 Value |= (op & UINT64_C(15)) << 12; 6314 // op: Vm 6315 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6316 Value |= (op & UINT64_C(16)) << 1; 6317 Value |= op & UINT64_C(15); 6318 Value = NEONThumb2V8PostEncoder(MI, Value, STI); 6319 break; 6320 } 6321 case ARM::VSLIv4i16: 6322 case ARM::VSLIv8i16: { 6323 // op: Vd 6324 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6325 Value |= (op & UINT64_C(16)) << 18; 6326 Value |= (op & UINT64_C(15)) << 12; 6327 // op: Vm 6328 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6329 Value |= (op & UINT64_C(16)) << 1; 6330 Value |= op & UINT64_C(15); 6331 // op: SIMM 6332 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6333 Value |= (op & UINT64_C(15)) << 16; 6334 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 6335 break; 6336 } 6337 case ARM::VSLIv2i32: 6338 case ARM::VSLIv4i32: { 6339 // op: Vd 6340 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6341 Value |= (op & UINT64_C(16)) << 18; 6342 Value |= (op & UINT64_C(15)) << 12; 6343 // op: Vm 6344 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6345 Value |= (op & UINT64_C(16)) << 1; 6346 Value |= op & UINT64_C(15); 6347 // op: SIMM 6348 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6349 Value |= (op & UINT64_C(31)) << 16; 6350 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 6351 break; 6352 } 6353 case ARM::VSLIv1i64: 6354 case ARM::VSLIv2i64: { 6355 // op: Vd 6356 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6357 Value |= (op & UINT64_C(16)) << 18; 6358 Value |= (op & UINT64_C(15)) << 12; 6359 // op: Vm 6360 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6361 Value |= (op & UINT64_C(16)) << 1; 6362 Value |= op & UINT64_C(15); 6363 // op: SIMM 6364 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6365 Value |= (op & UINT64_C(63)) << 16; 6366 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 6367 break; 6368 } 6369 case ARM::VSLIv16i8: 6370 case ARM::VSLIv8i8: { 6371 // op: Vd 6372 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6373 Value |= (op & UINT64_C(16)) << 18; 6374 Value |= (op & UINT64_C(15)) << 12; 6375 // op: Vm 6376 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6377 Value |= (op & UINT64_C(16)) << 1; 6378 Value |= op & UINT64_C(15); 6379 // op: SIMM 6380 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6381 Value |= (op & UINT64_C(7)) << 16; 6382 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 6383 break; 6384 } 6385 case ARM::VRSRAsv4i16: 6386 case ARM::VRSRAsv8i16: 6387 case ARM::VRSRAuv4i16: 6388 case ARM::VRSRAuv8i16: 6389 case ARM::VSRAsv4i16: 6390 case ARM::VSRAsv8i16: 6391 case ARM::VSRAuv4i16: 6392 case ARM::VSRAuv8i16: 6393 case ARM::VSRIv4i16: 6394 case ARM::VSRIv8i16: { 6395 // op: Vd 6396 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6397 Value |= (op & UINT64_C(16)) << 18; 6398 Value |= (op & UINT64_C(15)) << 12; 6399 // op: Vm 6400 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6401 Value |= (op & UINT64_C(16)) << 1; 6402 Value |= op & UINT64_C(15); 6403 // op: SIMM 6404 op = getShiftRight16Imm(MI, 3, Fixups, STI); 6405 Value |= (op & UINT64_C(15)) << 16; 6406 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 6407 break; 6408 } 6409 case ARM::VRSRAsv2i32: 6410 case ARM::VRSRAsv4i32: 6411 case ARM::VRSRAuv2i32: 6412 case ARM::VRSRAuv4i32: 6413 case ARM::VSRAsv2i32: 6414 case ARM::VSRAsv4i32: 6415 case ARM::VSRAuv2i32: 6416 case ARM::VSRAuv4i32: 6417 case ARM::VSRIv2i32: 6418 case ARM::VSRIv4i32: { 6419 // op: Vd 6420 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6421 Value |= (op & UINT64_C(16)) << 18; 6422 Value |= (op & UINT64_C(15)) << 12; 6423 // op: Vm 6424 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6425 Value |= (op & UINT64_C(16)) << 1; 6426 Value |= op & UINT64_C(15); 6427 // op: SIMM 6428 op = getShiftRight32Imm(MI, 3, Fixups, STI); 6429 Value |= (op & UINT64_C(31)) << 16; 6430 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 6431 break; 6432 } 6433 case ARM::VRSRAsv1i64: 6434 case ARM::VRSRAsv2i64: 6435 case ARM::VRSRAuv1i64: 6436 case ARM::VRSRAuv2i64: 6437 case ARM::VSRAsv1i64: 6438 case ARM::VSRAsv2i64: 6439 case ARM::VSRAuv1i64: 6440 case ARM::VSRAuv2i64: 6441 case ARM::VSRIv1i64: 6442 case ARM::VSRIv2i64: { 6443 // op: Vd 6444 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6445 Value |= (op & UINT64_C(16)) << 18; 6446 Value |= (op & UINT64_C(15)) << 12; 6447 // op: Vm 6448 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6449 Value |= (op & UINT64_C(16)) << 1; 6450 Value |= op & UINT64_C(15); 6451 // op: SIMM 6452 op = getShiftRight64Imm(MI, 3, Fixups, STI); 6453 Value |= (op & UINT64_C(63)) << 16; 6454 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 6455 break; 6456 } 6457 case ARM::VRSRAsv16i8: 6458 case ARM::VRSRAsv8i8: 6459 case ARM::VRSRAuv16i8: 6460 case ARM::VRSRAuv8i8: 6461 case ARM::VSRAsv16i8: 6462 case ARM::VSRAsv8i8: 6463 case ARM::VSRAuv16i8: 6464 case ARM::VSRAuv8i8: 6465 case ARM::VSRIv16i8: 6466 case ARM::VSRIv8i8: { 6467 // op: Vd 6468 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6469 Value |= (op & UINT64_C(16)) << 18; 6470 Value |= (op & UINT64_C(15)) << 12; 6471 // op: Vm 6472 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6473 Value |= (op & UINT64_C(16)) << 1; 6474 Value |= op & UINT64_C(15); 6475 // op: SIMM 6476 op = getShiftRight8Imm(MI, 3, Fixups, STI); 6477 Value |= (op & UINT64_C(7)) << 16; 6478 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 6479 break; 6480 } 6481 case ARM::AESD: 6482 case ARM::AESE: 6483 case ARM::SHA1SU1: 6484 case ARM::SHA256SU0: 6485 case ARM::VPADALsv16i8: 6486 case ARM::VPADALsv2i32: 6487 case ARM::VPADALsv4i16: 6488 case ARM::VPADALsv4i32: 6489 case ARM::VPADALsv8i16: 6490 case ARM::VPADALsv8i8: 6491 case ARM::VPADALuv16i8: 6492 case ARM::VPADALuv2i32: 6493 case ARM::VPADALuv4i16: 6494 case ARM::VPADALuv4i32: 6495 case ARM::VPADALuv8i16: 6496 case ARM::VPADALuv8i8: { 6497 // op: Vd 6498 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6499 Value |= (op & UINT64_C(16)) << 18; 6500 Value |= (op & UINT64_C(15)) << 12; 6501 // op: Vm 6502 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6503 Value |= (op & UINT64_C(16)) << 1; 6504 Value |= op & UINT64_C(15); 6505 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 6506 break; 6507 } 6508 case ARM::VEXTd32: { 6509 // op: Vd 6510 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6511 Value |= (op & UINT64_C(16)) << 18; 6512 Value |= (op & UINT64_C(15)) << 12; 6513 // op: Vn 6514 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6515 Value |= (op & UINT64_C(15)) << 16; 6516 Value |= (op & UINT64_C(16)) << 3; 6517 // op: Vm 6518 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6519 Value |= (op & UINT64_C(16)) << 1; 6520 Value |= op & UINT64_C(15); 6521 // op: index 6522 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6523 Value |= (op & UINT64_C(1)) << 10; 6524 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 6525 break; 6526 } 6527 case ARM::VEXTq64: { 6528 // op: Vd 6529 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6530 Value |= (op & UINT64_C(16)) << 18; 6531 Value |= (op & UINT64_C(15)) << 12; 6532 // op: Vn 6533 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6534 Value |= (op & UINT64_C(15)) << 16; 6535 Value |= (op & UINT64_C(16)) << 3; 6536 // op: Vm 6537 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6538 Value |= (op & UINT64_C(16)) << 1; 6539 Value |= op & UINT64_C(15); 6540 // op: index 6541 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6542 Value |= (op & UINT64_C(1)) << 11; 6543 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 6544 break; 6545 } 6546 case ARM::VEXTq8: { 6547 // op: Vd 6548 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6549 Value |= (op & UINT64_C(16)) << 18; 6550 Value |= (op & UINT64_C(15)) << 12; 6551 // op: Vn 6552 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6553 Value |= (op & UINT64_C(15)) << 16; 6554 Value |= (op & UINT64_C(16)) << 3; 6555 // op: Vm 6556 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6557 Value |= (op & UINT64_C(16)) << 1; 6558 Value |= op & UINT64_C(15); 6559 // op: index 6560 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6561 Value |= (op & UINT64_C(15)) << 8; 6562 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 6563 break; 6564 } 6565 case ARM::VEXTq32: { 6566 // op: Vd 6567 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6568 Value |= (op & UINT64_C(16)) << 18; 6569 Value |= (op & UINT64_C(15)) << 12; 6570 // op: Vn 6571 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6572 Value |= (op & UINT64_C(15)) << 16; 6573 Value |= (op & UINT64_C(16)) << 3; 6574 // op: Vm 6575 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6576 Value |= (op & UINT64_C(16)) << 1; 6577 Value |= op & UINT64_C(15); 6578 // op: index 6579 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6580 Value |= (op & UINT64_C(3)) << 10; 6581 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 6582 break; 6583 } 6584 case ARM::VEXTd16: { 6585 // op: Vd 6586 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6587 Value |= (op & UINT64_C(16)) << 18; 6588 Value |= (op & UINT64_C(15)) << 12; 6589 // op: Vn 6590 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6591 Value |= (op & UINT64_C(15)) << 16; 6592 Value |= (op & UINT64_C(16)) << 3; 6593 // op: Vm 6594 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6595 Value |= (op & UINT64_C(16)) << 1; 6596 Value |= op & UINT64_C(15); 6597 // op: index 6598 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6599 Value |= (op & UINT64_C(3)) << 9; 6600 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 6601 break; 6602 } 6603 case ARM::VEXTd8: { 6604 // op: Vd 6605 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6606 Value |= (op & UINT64_C(16)) << 18; 6607 Value |= (op & UINT64_C(15)) << 12; 6608 // op: Vn 6609 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6610 Value |= (op & UINT64_C(15)) << 16; 6611 Value |= (op & UINT64_C(16)) << 3; 6612 // op: Vm 6613 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6614 Value |= (op & UINT64_C(16)) << 1; 6615 Value |= op & UINT64_C(15); 6616 // op: index 6617 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6618 Value |= (op & UINT64_C(7)) << 8; 6619 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 6620 break; 6621 } 6622 case ARM::VEXTq16: { 6623 // op: Vd 6624 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6625 Value |= (op & UINT64_C(16)) << 18; 6626 Value |= (op & UINT64_C(15)) << 12; 6627 // op: Vn 6628 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6629 Value |= (op & UINT64_C(15)) << 16; 6630 Value |= (op & UINT64_C(16)) << 3; 6631 // op: Vm 6632 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6633 Value |= (op & UINT64_C(16)) << 1; 6634 Value |= op & UINT64_C(15); 6635 // op: index 6636 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6637 Value |= (op & UINT64_C(7)) << 9; 6638 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 6639 break; 6640 } 6641 case ARM::VCADDv2f32: 6642 case ARM::VCADDv4f16: 6643 case ARM::VCADDv4f32: 6644 case ARM::VCADDv8f16: { 6645 // op: Vd 6646 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6647 Value |= (op & UINT64_C(16)) << 18; 6648 Value |= (op & UINT64_C(15)) << 12; 6649 // op: Vn 6650 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6651 Value |= (op & UINT64_C(15)) << 16; 6652 Value |= (op & UINT64_C(16)) << 3; 6653 // op: Vm 6654 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6655 Value |= (op & UINT64_C(16)) << 1; 6656 Value |= op & UINT64_C(15); 6657 // op: rot 6658 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 6659 Value |= (op & UINT64_C(1)) << 24; 6660 break; 6661 } 6662 case ARM::VABDLsv2i64: 6663 case ARM::VABDLsv4i32: 6664 case ARM::VABDLsv8i16: 6665 case ARM::VABDLuv2i64: 6666 case ARM::VABDLuv4i32: 6667 case ARM::VABDLuv8i16: 6668 case ARM::VABDfd: 6669 case ARM::VABDfq: 6670 case ARM::VABDhd: 6671 case ARM::VABDhq: 6672 case ARM::VABDsv16i8: 6673 case ARM::VABDsv2i32: 6674 case ARM::VABDsv4i16: 6675 case ARM::VABDsv4i32: 6676 case ARM::VABDsv8i16: 6677 case ARM::VABDsv8i8: 6678 case ARM::VABDuv16i8: 6679 case ARM::VABDuv2i32: 6680 case ARM::VABDuv4i16: 6681 case ARM::VABDuv4i32: 6682 case ARM::VABDuv8i16: 6683 case ARM::VABDuv8i8: 6684 case ARM::VACGEfd: 6685 case ARM::VACGEfq: 6686 case ARM::VACGEhd: 6687 case ARM::VACGEhq: 6688 case ARM::VACGTfd: 6689 case ARM::VACGTfq: 6690 case ARM::VACGThd: 6691 case ARM::VACGThq: 6692 case ARM::VADDHNv2i32: 6693 case ARM::VADDHNv4i16: 6694 case ARM::VADDHNv8i8: 6695 case ARM::VADDLsv2i64: 6696 case ARM::VADDLsv4i32: 6697 case ARM::VADDLsv8i16: 6698 case ARM::VADDLuv2i64: 6699 case ARM::VADDLuv4i32: 6700 case ARM::VADDLuv8i16: 6701 case ARM::VADDWsv2i64: 6702 case ARM::VADDWsv4i32: 6703 case ARM::VADDWsv8i16: 6704 case ARM::VADDWuv2i64: 6705 case ARM::VADDWuv4i32: 6706 case ARM::VADDWuv8i16: 6707 case ARM::VADDfd: 6708 case ARM::VADDfq: 6709 case ARM::VADDhd: 6710 case ARM::VADDhq: 6711 case ARM::VADDv16i8: 6712 case ARM::VADDv1i64: 6713 case ARM::VADDv2i32: 6714 case ARM::VADDv2i64: 6715 case ARM::VADDv4i16: 6716 case ARM::VADDv4i32: 6717 case ARM::VADDv8i16: 6718 case ARM::VADDv8i8: 6719 case ARM::VANDd: 6720 case ARM::VANDq: 6721 case ARM::VBICd: 6722 case ARM::VBICq: 6723 case ARM::VCEQfd: 6724 case ARM::VCEQfq: 6725 case ARM::VCEQhd: 6726 case ARM::VCEQhq: 6727 case ARM::VCEQv16i8: 6728 case ARM::VCEQv2i32: 6729 case ARM::VCEQv4i16: 6730 case ARM::VCEQv4i32: 6731 case ARM::VCEQv8i16: 6732 case ARM::VCEQv8i8: 6733 case ARM::VCGEfd: 6734 case ARM::VCGEfq: 6735 case ARM::VCGEhd: 6736 case ARM::VCGEhq: 6737 case ARM::VCGEsv16i8: 6738 case ARM::VCGEsv2i32: 6739 case ARM::VCGEsv4i16: 6740 case ARM::VCGEsv4i32: 6741 case ARM::VCGEsv8i16: 6742 case ARM::VCGEsv8i8: 6743 case ARM::VCGEuv16i8: 6744 case ARM::VCGEuv2i32: 6745 case ARM::VCGEuv4i16: 6746 case ARM::VCGEuv4i32: 6747 case ARM::VCGEuv8i16: 6748 case ARM::VCGEuv8i8: 6749 case ARM::VCGTfd: 6750 case ARM::VCGTfq: 6751 case ARM::VCGThd: 6752 case ARM::VCGThq: 6753 case ARM::VCGTsv16i8: 6754 case ARM::VCGTsv2i32: 6755 case ARM::VCGTsv4i16: 6756 case ARM::VCGTsv4i32: 6757 case ARM::VCGTsv8i16: 6758 case ARM::VCGTsv8i8: 6759 case ARM::VCGTuv16i8: 6760 case ARM::VCGTuv2i32: 6761 case ARM::VCGTuv4i16: 6762 case ARM::VCGTuv4i32: 6763 case ARM::VCGTuv8i16: 6764 case ARM::VCGTuv8i8: 6765 case ARM::VEORd: 6766 case ARM::VEORq: 6767 case ARM::VHADDsv16i8: 6768 case ARM::VHADDsv2i32: 6769 case ARM::VHADDsv4i16: 6770 case ARM::VHADDsv4i32: 6771 case ARM::VHADDsv8i16: 6772 case ARM::VHADDsv8i8: 6773 case ARM::VHADDuv16i8: 6774 case ARM::VHADDuv2i32: 6775 case ARM::VHADDuv4i16: 6776 case ARM::VHADDuv4i32: 6777 case ARM::VHADDuv8i16: 6778 case ARM::VHADDuv8i8: 6779 case ARM::VHSUBsv16i8: 6780 case ARM::VHSUBsv2i32: 6781 case ARM::VHSUBsv4i16: 6782 case ARM::VHSUBsv4i32: 6783 case ARM::VHSUBsv8i16: 6784 case ARM::VHSUBsv8i8: 6785 case ARM::VHSUBuv16i8: 6786 case ARM::VHSUBuv2i32: 6787 case ARM::VHSUBuv4i16: 6788 case ARM::VHSUBuv4i32: 6789 case ARM::VHSUBuv8i16: 6790 case ARM::VHSUBuv8i8: 6791 case ARM::VMAXfd: 6792 case ARM::VMAXfq: 6793 case ARM::VMAXhd: 6794 case ARM::VMAXhq: 6795 case ARM::VMAXsv16i8: 6796 case ARM::VMAXsv2i32: 6797 case ARM::VMAXsv4i16: 6798 case ARM::VMAXsv4i32: 6799 case ARM::VMAXsv8i16: 6800 case ARM::VMAXsv8i8: 6801 case ARM::VMAXuv16i8: 6802 case ARM::VMAXuv2i32: 6803 case ARM::VMAXuv4i16: 6804 case ARM::VMAXuv4i32: 6805 case ARM::VMAXuv8i16: 6806 case ARM::VMAXuv8i8: 6807 case ARM::VMINfd: 6808 case ARM::VMINfq: 6809 case ARM::VMINhd: 6810 case ARM::VMINhq: 6811 case ARM::VMINsv16i8: 6812 case ARM::VMINsv2i32: 6813 case ARM::VMINsv4i16: 6814 case ARM::VMINsv4i32: 6815 case ARM::VMINsv8i16: 6816 case ARM::VMINsv8i8: 6817 case ARM::VMINuv16i8: 6818 case ARM::VMINuv2i32: 6819 case ARM::VMINuv4i16: 6820 case ARM::VMINuv4i32: 6821 case ARM::VMINuv8i16: 6822 case ARM::VMINuv8i8: 6823 case ARM::VMULLp64: 6824 case ARM::VMULLp8: 6825 case ARM::VMULLsv2i64: 6826 case ARM::VMULLsv4i32: 6827 case ARM::VMULLsv8i16: 6828 case ARM::VMULLuv2i64: 6829 case ARM::VMULLuv4i32: 6830 case ARM::VMULLuv8i16: 6831 case ARM::VMULfd: 6832 case ARM::VMULfq: 6833 case ARM::VMULhd: 6834 case ARM::VMULhq: 6835 case ARM::VMULpd: 6836 case ARM::VMULpq: 6837 case ARM::VMULv16i8: 6838 case ARM::VMULv2i32: 6839 case ARM::VMULv4i16: 6840 case ARM::VMULv4i32: 6841 case ARM::VMULv8i16: 6842 case ARM::VMULv8i8: 6843 case ARM::VORNd: 6844 case ARM::VORNq: 6845 case ARM::VORRd: 6846 case ARM::VORRq: 6847 case ARM::VPADDf: 6848 case ARM::VPADDh: 6849 case ARM::VPADDi16: 6850 case ARM::VPADDi32: 6851 case ARM::VPADDi8: 6852 case ARM::VPMAXf: 6853 case ARM::VPMAXh: 6854 case ARM::VPMAXs16: 6855 case ARM::VPMAXs32: 6856 case ARM::VPMAXs8: 6857 case ARM::VPMAXu16: 6858 case ARM::VPMAXu32: 6859 case ARM::VPMAXu8: 6860 case ARM::VPMINf: 6861 case ARM::VPMINh: 6862 case ARM::VPMINs16: 6863 case ARM::VPMINs32: 6864 case ARM::VPMINs8: 6865 case ARM::VPMINu16: 6866 case ARM::VPMINu32: 6867 case ARM::VPMINu8: 6868 case ARM::VQADDsv16i8: 6869 case ARM::VQADDsv1i64: 6870 case ARM::VQADDsv2i32: 6871 case ARM::VQADDsv2i64: 6872 case ARM::VQADDsv4i16: 6873 case ARM::VQADDsv4i32: 6874 case ARM::VQADDsv8i16: 6875 case ARM::VQADDsv8i8: 6876 case ARM::VQADDuv16i8: 6877 case ARM::VQADDuv1i64: 6878 case ARM::VQADDuv2i32: 6879 case ARM::VQADDuv2i64: 6880 case ARM::VQADDuv4i16: 6881 case ARM::VQADDuv4i32: 6882 case ARM::VQADDuv8i16: 6883 case ARM::VQADDuv8i8: 6884 case ARM::VQDMULHv2i32: 6885 case ARM::VQDMULHv4i16: 6886 case ARM::VQDMULHv4i32: 6887 case ARM::VQDMULHv8i16: 6888 case ARM::VQDMULLv2i64: 6889 case ARM::VQDMULLv4i32: 6890 case ARM::VQRDMULHv2i32: 6891 case ARM::VQRDMULHv4i16: 6892 case ARM::VQRDMULHv4i32: 6893 case ARM::VQRDMULHv8i16: 6894 case ARM::VQSUBsv16i8: 6895 case ARM::VQSUBsv1i64: 6896 case ARM::VQSUBsv2i32: 6897 case ARM::VQSUBsv2i64: 6898 case ARM::VQSUBsv4i16: 6899 case ARM::VQSUBsv4i32: 6900 case ARM::VQSUBsv8i16: 6901 case ARM::VQSUBsv8i8: 6902 case ARM::VQSUBuv16i8: 6903 case ARM::VQSUBuv1i64: 6904 case ARM::VQSUBuv2i32: 6905 case ARM::VQSUBuv2i64: 6906 case ARM::VQSUBuv4i16: 6907 case ARM::VQSUBuv4i32: 6908 case ARM::VQSUBuv8i16: 6909 case ARM::VQSUBuv8i8: 6910 case ARM::VRADDHNv2i32: 6911 case ARM::VRADDHNv4i16: 6912 case ARM::VRADDHNv8i8: 6913 case ARM::VRECPSfd: 6914 case ARM::VRECPSfq: 6915 case ARM::VRECPShd: 6916 case ARM::VRECPShq: 6917 case ARM::VRHADDsv16i8: 6918 case ARM::VRHADDsv2i32: 6919 case ARM::VRHADDsv4i16: 6920 case ARM::VRHADDsv4i32: 6921 case ARM::VRHADDsv8i16: 6922 case ARM::VRHADDsv8i8: 6923 case ARM::VRHADDuv16i8: 6924 case ARM::VRHADDuv2i32: 6925 case ARM::VRHADDuv4i16: 6926 case ARM::VRHADDuv4i32: 6927 case ARM::VRHADDuv8i16: 6928 case ARM::VRHADDuv8i8: 6929 case ARM::VRSQRTSfd: 6930 case ARM::VRSQRTSfq: 6931 case ARM::VRSQRTShd: 6932 case ARM::VRSQRTShq: 6933 case ARM::VRSUBHNv2i32: 6934 case ARM::VRSUBHNv4i16: 6935 case ARM::VRSUBHNv8i8: 6936 case ARM::VSUBHNv2i32: 6937 case ARM::VSUBHNv4i16: 6938 case ARM::VSUBHNv8i8: 6939 case ARM::VSUBLsv2i64: 6940 case ARM::VSUBLsv4i32: 6941 case ARM::VSUBLsv8i16: 6942 case ARM::VSUBLuv2i64: 6943 case ARM::VSUBLuv4i32: 6944 case ARM::VSUBLuv8i16: 6945 case ARM::VSUBWsv2i64: 6946 case ARM::VSUBWsv4i32: 6947 case ARM::VSUBWsv8i16: 6948 case ARM::VSUBWuv2i64: 6949 case ARM::VSUBWuv4i32: 6950 case ARM::VSUBWuv8i16: 6951 case ARM::VSUBfd: 6952 case ARM::VSUBfq: 6953 case ARM::VSUBhd: 6954 case ARM::VSUBhq: 6955 case ARM::VSUBv16i8: 6956 case ARM::VSUBv1i64: 6957 case ARM::VSUBv2i32: 6958 case ARM::VSUBv2i64: 6959 case ARM::VSUBv4i16: 6960 case ARM::VSUBv4i32: 6961 case ARM::VSUBv8i16: 6962 case ARM::VSUBv8i8: 6963 case ARM::VTBL1: 6964 case ARM::VTBL2: 6965 case ARM::VTBL3: 6966 case ARM::VTBL4: 6967 case ARM::VTSTv16i8: 6968 case ARM::VTSTv2i32: 6969 case ARM::VTSTv4i16: 6970 case ARM::VTSTv4i32: 6971 case ARM::VTSTv8i16: 6972 case ARM::VTSTv8i8: { 6973 // op: Vd 6974 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6975 Value |= (op & UINT64_C(16)) << 18; 6976 Value |= (op & UINT64_C(15)) << 12; 6977 // op: Vn 6978 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 6979 Value |= (op & UINT64_C(15)) << 16; 6980 Value |= (op & UINT64_C(16)) << 3; 6981 // op: Vm 6982 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 6983 Value |= (op & UINT64_C(16)) << 1; 6984 Value |= op & UINT64_C(15); 6985 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 6986 break; 6987 } 6988 case ARM::VMAXNMNDf: 6989 case ARM::VMAXNMNDh: 6990 case ARM::VMAXNMNQf: 6991 case ARM::VMAXNMNQh: 6992 case ARM::VMINNMNDf: 6993 case ARM::VMINNMNDh: 6994 case ARM::VMINNMNQf: 6995 case ARM::VMINNMNQh: { 6996 // op: Vd 6997 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 6998 Value |= (op & UINT64_C(16)) << 18; 6999 Value |= (op & UINT64_C(15)) << 12; 7000 // op: Vn 7001 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7002 Value |= (op & UINT64_C(15)) << 16; 7003 Value |= (op & UINT64_C(16)) << 3; 7004 // op: Vm 7005 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7006 Value |= (op & UINT64_C(16)) << 1; 7007 Value |= op & UINT64_C(15); 7008 Value = NEONThumb2V8PostEncoder(MI, Value, STI); 7009 break; 7010 } 7011 case ARM::VMULLslsv2i32: 7012 case ARM::VMULLsluv2i32: 7013 case ARM::VMULslfd: 7014 case ARM::VMULslfq: 7015 case ARM::VMULslv2i32: 7016 case ARM::VMULslv4i32: 7017 case ARM::VQDMULHslv2i32: 7018 case ARM::VQDMULHslv4i32: 7019 case ARM::VQDMULLslv2i32: 7020 case ARM::VQRDMULHslv2i32: 7021 case ARM::VQRDMULHslv4i32: { 7022 // op: Vd 7023 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7024 Value |= (op & UINT64_C(16)) << 18; 7025 Value |= (op & UINT64_C(15)) << 12; 7026 // op: Vn 7027 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7028 Value |= (op & UINT64_C(15)) << 16; 7029 Value |= (op & UINT64_C(16)) << 3; 7030 // op: Vm 7031 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7032 Value |= op & UINT64_C(15); 7033 // op: lane 7034 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 7035 Value |= (op & UINT64_C(1)) << 5; 7036 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 7037 break; 7038 } 7039 case ARM::VMULLslsv4i16: 7040 case ARM::VMULLsluv4i16: 7041 case ARM::VMULslhd: 7042 case ARM::VMULslhq: 7043 case ARM::VMULslv4i16: 7044 case ARM::VMULslv8i16: 7045 case ARM::VQDMULHslv4i16: 7046 case ARM::VQDMULHslv8i16: 7047 case ARM::VQDMULLslv4i16: 7048 case ARM::VQRDMULHslv4i16: 7049 case ARM::VQRDMULHslv8i16: { 7050 // op: Vd 7051 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7052 Value |= (op & UINT64_C(16)) << 18; 7053 Value |= (op & UINT64_C(15)) << 12; 7054 // op: Vn 7055 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7056 Value |= (op & UINT64_C(15)) << 16; 7057 Value |= (op & UINT64_C(16)) << 3; 7058 // op: Vm 7059 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7060 Value |= op & UINT64_C(7); 7061 // op: lane 7062 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 7063 Value |= (op & UINT64_C(2)) << 4; 7064 Value |= (op & UINT64_C(1)) << 3; 7065 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 7066 break; 7067 } 7068 case ARM::VQRSHLsv16i8: 7069 case ARM::VQRSHLsv1i64: 7070 case ARM::VQRSHLsv2i32: 7071 case ARM::VQRSHLsv2i64: 7072 case ARM::VQRSHLsv4i16: 7073 case ARM::VQRSHLsv4i32: 7074 case ARM::VQRSHLsv8i16: 7075 case ARM::VQRSHLsv8i8: 7076 case ARM::VQRSHLuv16i8: 7077 case ARM::VQRSHLuv1i64: 7078 case ARM::VQRSHLuv2i32: 7079 case ARM::VQRSHLuv2i64: 7080 case ARM::VQRSHLuv4i16: 7081 case ARM::VQRSHLuv4i32: 7082 case ARM::VQRSHLuv8i16: 7083 case ARM::VQRSHLuv8i8: 7084 case ARM::VQSHLsv16i8: 7085 case ARM::VQSHLsv1i64: 7086 case ARM::VQSHLsv2i32: 7087 case ARM::VQSHLsv2i64: 7088 case ARM::VQSHLsv4i16: 7089 case ARM::VQSHLsv4i32: 7090 case ARM::VQSHLsv8i16: 7091 case ARM::VQSHLsv8i8: 7092 case ARM::VQSHLuv16i8: 7093 case ARM::VQSHLuv1i64: 7094 case ARM::VQSHLuv2i32: 7095 case ARM::VQSHLuv2i64: 7096 case ARM::VQSHLuv4i16: 7097 case ARM::VQSHLuv4i32: 7098 case ARM::VQSHLuv8i16: 7099 case ARM::VQSHLuv8i8: 7100 case ARM::VRSHLsv16i8: 7101 case ARM::VRSHLsv1i64: 7102 case ARM::VRSHLsv2i32: 7103 case ARM::VRSHLsv2i64: 7104 case ARM::VRSHLsv4i16: 7105 case ARM::VRSHLsv4i32: 7106 case ARM::VRSHLsv8i16: 7107 case ARM::VRSHLsv8i8: 7108 case ARM::VRSHLuv16i8: 7109 case ARM::VRSHLuv1i64: 7110 case ARM::VRSHLuv2i32: 7111 case ARM::VRSHLuv2i64: 7112 case ARM::VRSHLuv4i16: 7113 case ARM::VRSHLuv4i32: 7114 case ARM::VRSHLuv8i16: 7115 case ARM::VRSHLuv8i8: 7116 case ARM::VSHLsv16i8: 7117 case ARM::VSHLsv1i64: 7118 case ARM::VSHLsv2i32: 7119 case ARM::VSHLsv2i64: 7120 case ARM::VSHLsv4i16: 7121 case ARM::VSHLsv4i32: 7122 case ARM::VSHLsv8i16: 7123 case ARM::VSHLsv8i8: 7124 case ARM::VSHLuv16i8: 7125 case ARM::VSHLuv1i64: 7126 case ARM::VSHLuv2i32: 7127 case ARM::VSHLuv2i64: 7128 case ARM::VSHLuv4i16: 7129 case ARM::VSHLuv4i32: 7130 case ARM::VSHLuv8i16: 7131 case ARM::VSHLuv8i8: { 7132 // op: Vd 7133 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7134 Value |= (op & UINT64_C(16)) << 18; 7135 Value |= (op & UINT64_C(15)) << 12; 7136 // op: Vn 7137 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7138 Value |= (op & UINT64_C(15)) << 16; 7139 Value |= (op & UINT64_C(16)) << 3; 7140 // op: Vm 7141 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7142 Value |= (op & UINT64_C(16)) << 1; 7143 Value |= op & UINT64_C(15); 7144 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 7145 break; 7146 } 7147 case ARM::VCMLAv2f32: 7148 case ARM::VCMLAv4f16: 7149 case ARM::VCMLAv4f32: 7150 case ARM::VCMLAv8f16: { 7151 // op: Vd 7152 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7153 Value |= (op & UINT64_C(16)) << 18; 7154 Value |= (op & UINT64_C(15)) << 12; 7155 // op: Vn 7156 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7157 Value |= (op & UINT64_C(15)) << 16; 7158 Value |= (op & UINT64_C(16)) << 3; 7159 // op: Vm 7160 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 7161 Value |= (op & UINT64_C(16)) << 1; 7162 Value |= op & UINT64_C(15); 7163 // op: rot 7164 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7165 Value |= (op & UINT64_C(3)) << 23; 7166 break; 7167 } 7168 case ARM::VCMLAv2f32_indexed: 7169 case ARM::VCMLAv4f32_indexed: { 7170 // op: Vd 7171 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7172 Value |= (op & UINT64_C(16)) << 18; 7173 Value |= (op & UINT64_C(15)) << 12; 7174 // op: Vn 7175 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7176 Value |= (op & UINT64_C(15)) << 16; 7177 Value |= (op & UINT64_C(16)) << 3; 7178 // op: Vm 7179 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 7180 Value |= (op & UINT64_C(16)) << 1; 7181 Value |= op & UINT64_C(15); 7182 // op: rot 7183 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 7184 Value |= (op & UINT64_C(3)) << 20; 7185 break; 7186 } 7187 case ARM::SHA1C: 7188 case ARM::SHA1M: 7189 case ARM::SHA1P: 7190 case ARM::SHA1SU0: 7191 case ARM::SHA256H: 7192 case ARM::SHA256H2: 7193 case ARM::SHA256SU1: 7194 case ARM::VABALsv2i64: 7195 case ARM::VABALsv4i32: 7196 case ARM::VABALsv8i16: 7197 case ARM::VABALuv2i64: 7198 case ARM::VABALuv4i32: 7199 case ARM::VABALuv8i16: 7200 case ARM::VABAsv16i8: 7201 case ARM::VABAsv2i32: 7202 case ARM::VABAsv4i16: 7203 case ARM::VABAsv4i32: 7204 case ARM::VABAsv8i16: 7205 case ARM::VABAsv8i8: 7206 case ARM::VABAuv16i8: 7207 case ARM::VABAuv2i32: 7208 case ARM::VABAuv4i16: 7209 case ARM::VABAuv4i32: 7210 case ARM::VABAuv8i16: 7211 case ARM::VABAuv8i8: 7212 case ARM::VBIFd: 7213 case ARM::VBIFq: 7214 case ARM::VBITd: 7215 case ARM::VBITq: 7216 case ARM::VBSLd: 7217 case ARM::VBSLq: 7218 case ARM::VFMAfd: 7219 case ARM::VFMAfq: 7220 case ARM::VFMAhd: 7221 case ARM::VFMAhq: 7222 case ARM::VFMSfd: 7223 case ARM::VFMSfq: 7224 case ARM::VFMShd: 7225 case ARM::VFMShq: 7226 case ARM::VMLALsv2i64: 7227 case ARM::VMLALsv4i32: 7228 case ARM::VMLALsv8i16: 7229 case ARM::VMLALuv2i64: 7230 case ARM::VMLALuv4i32: 7231 case ARM::VMLALuv8i16: 7232 case ARM::VMLAfd: 7233 case ARM::VMLAfq: 7234 case ARM::VMLAhd: 7235 case ARM::VMLAhq: 7236 case ARM::VMLAv16i8: 7237 case ARM::VMLAv2i32: 7238 case ARM::VMLAv4i16: 7239 case ARM::VMLAv4i32: 7240 case ARM::VMLAv8i16: 7241 case ARM::VMLAv8i8: 7242 case ARM::VMLSLsv2i64: 7243 case ARM::VMLSLsv4i32: 7244 case ARM::VMLSLsv8i16: 7245 case ARM::VMLSLuv2i64: 7246 case ARM::VMLSLuv4i32: 7247 case ARM::VMLSLuv8i16: 7248 case ARM::VMLSfd: 7249 case ARM::VMLSfq: 7250 case ARM::VMLShd: 7251 case ARM::VMLShq: 7252 case ARM::VMLSv16i8: 7253 case ARM::VMLSv2i32: 7254 case ARM::VMLSv4i16: 7255 case ARM::VMLSv4i32: 7256 case ARM::VMLSv8i16: 7257 case ARM::VMLSv8i8: 7258 case ARM::VQDMLALv2i64: 7259 case ARM::VQDMLALv4i32: 7260 case ARM::VQDMLSLv2i64: 7261 case ARM::VQDMLSLv4i32: 7262 case ARM::VQRDMLAHv2i32: 7263 case ARM::VQRDMLAHv4i16: 7264 case ARM::VQRDMLAHv4i32: 7265 case ARM::VQRDMLAHv8i16: 7266 case ARM::VQRDMLSHv2i32: 7267 case ARM::VQRDMLSHv4i16: 7268 case ARM::VQRDMLSHv4i32: 7269 case ARM::VQRDMLSHv8i16: 7270 case ARM::VTBX1: 7271 case ARM::VTBX2: 7272 case ARM::VTBX3: 7273 case ARM::VTBX4: { 7274 // op: Vd 7275 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7276 Value |= (op & UINT64_C(16)) << 18; 7277 Value |= (op & UINT64_C(15)) << 12; 7278 // op: Vn 7279 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7280 Value |= (op & UINT64_C(15)) << 16; 7281 Value |= (op & UINT64_C(16)) << 3; 7282 // op: Vm 7283 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 7284 Value |= (op & UINT64_C(16)) << 1; 7285 Value |= op & UINT64_C(15); 7286 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 7287 break; 7288 } 7289 case ARM::VMLALslsv2i32: 7290 case ARM::VMLALsluv2i32: 7291 case ARM::VMLAslfd: 7292 case ARM::VMLAslfq: 7293 case ARM::VMLAslv2i32: 7294 case ARM::VMLAslv4i32: 7295 case ARM::VMLSLslsv2i32: 7296 case ARM::VMLSLsluv2i32: 7297 case ARM::VMLSslfd: 7298 case ARM::VMLSslfq: 7299 case ARM::VMLSslv2i32: 7300 case ARM::VMLSslv4i32: 7301 case ARM::VQDMLALslv2i32: 7302 case ARM::VQDMLSLslv2i32: 7303 case ARM::VQRDMLAHslv2i32: 7304 case ARM::VQRDMLAHslv4i32: 7305 case ARM::VQRDMLSHslv2i32: 7306 case ARM::VQRDMLSHslv4i32: { 7307 // op: Vd 7308 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7309 Value |= (op & UINT64_C(16)) << 18; 7310 Value |= (op & UINT64_C(15)) << 12; 7311 // op: Vn 7312 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7313 Value |= (op & UINT64_C(15)) << 16; 7314 Value |= (op & UINT64_C(16)) << 3; 7315 // op: Vm 7316 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 7317 Value |= op & UINT64_C(15); 7318 // op: lane 7319 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7320 Value |= (op & UINT64_C(1)) << 5; 7321 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 7322 break; 7323 } 7324 case ARM::VCMLAv4f16_indexed: 7325 case ARM::VCMLAv8f16_indexed: { 7326 // op: Vd 7327 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7328 Value |= (op & UINT64_C(16)) << 18; 7329 Value |= (op & UINT64_C(15)) << 12; 7330 // op: Vn 7331 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7332 Value |= (op & UINT64_C(15)) << 16; 7333 Value |= (op & UINT64_C(16)) << 3; 7334 // op: Vm 7335 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 7336 Value |= op & UINT64_C(15); 7337 // op: rot 7338 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 7339 Value |= (op & UINT64_C(3)) << 20; 7340 // op: lane 7341 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7342 Value |= (op & UINT64_C(1)) << 5; 7343 break; 7344 } 7345 case ARM::VMLALslsv4i16: 7346 case ARM::VMLALsluv4i16: 7347 case ARM::VMLAslhd: 7348 case ARM::VMLAslhq: 7349 case ARM::VMLAslv4i16: 7350 case ARM::VMLAslv8i16: 7351 case ARM::VMLSLslsv4i16: 7352 case ARM::VMLSLsluv4i16: 7353 case ARM::VMLSslhd: 7354 case ARM::VMLSslhq: 7355 case ARM::VMLSslv4i16: 7356 case ARM::VMLSslv8i16: 7357 case ARM::VQDMLALslv4i16: 7358 case ARM::VQDMLSLslv4i16: 7359 case ARM::VQRDMLAHslv4i16: 7360 case ARM::VQRDMLAHslv8i16: 7361 case ARM::VQRDMLSHslv4i16: 7362 case ARM::VQRDMLSHslv8i16: { 7363 // op: Vd 7364 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 7365 Value |= (op & UINT64_C(16)) << 18; 7366 Value |= (op & UINT64_C(15)) << 12; 7367 // op: Vn 7368 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7369 Value |= (op & UINT64_C(15)) << 16; 7370 Value |= (op & UINT64_C(16)) << 3; 7371 // op: Vm 7372 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 7373 Value |= op & UINT64_C(7); 7374 // op: lane 7375 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7376 Value |= (op & UINT64_C(2)) << 4; 7377 Value |= (op & UINT64_C(1)) << 3; 7378 Value = NEONThumb2DataIPostEncoder(MI, Value, STI); 7379 break; 7380 } 7381 case ARM::VSDOTD: 7382 case ARM::VSDOTQ: 7383 case ARM::VUDOTD: 7384 case ARM::VUDOTQ: { 7385 // op: Vd 7386 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7387 Value |= (op & UINT64_C(16)) << 18; 7388 Value |= (op & UINT64_C(15)) << 12; 7389 // op: Vn 7390 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7391 Value |= (op & UINT64_C(15)) << 16; 7392 Value |= (op & UINT64_C(16)) << 3; 7393 // op: Vm 7394 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 7395 Value |= (op & UINT64_C(16)) << 1; 7396 Value |= op & UINT64_C(15); 7397 break; 7398 } 7399 case ARM::VSDOTDI: 7400 case ARM::VSDOTQI: 7401 case ARM::VUDOTDI: 7402 case ARM::VUDOTQI: { 7403 // op: Vd 7404 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 7405 Value |= (op & UINT64_C(16)) << 18; 7406 Value |= (op & UINT64_C(15)) << 12; 7407 // op: Vn 7408 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7409 Value |= (op & UINT64_C(15)) << 16; 7410 Value |= (op & UINT64_C(16)) << 3; 7411 // op: Vm 7412 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 7413 Value |= op & UINT64_C(15); 7414 // op: lane 7415 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7416 Value |= (op & UINT64_C(1)) << 5; 7417 break; 7418 } 7419 case ARM::VST1LNd8: { 7420 // op: Vd 7421 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7422 Value |= (op & UINT64_C(16)) << 18; 7423 Value |= (op & UINT64_C(15)) << 12; 7424 // op: Rn 7425 op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI); 7426 Value |= (op & UINT64_C(15)) << 16; 7427 // op: lane 7428 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 7429 Value |= (op & UINT64_C(7)) << 5; 7430 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7431 break; 7432 } 7433 case ARM::VST3LNd32: 7434 case ARM::VST3LNq32: { 7435 // op: Vd 7436 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7437 Value |= (op & UINT64_C(16)) << 18; 7438 Value |= (op & UINT64_C(15)) << 12; 7439 // op: Rn 7440 op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI); 7441 Value |= (op & UINT64_C(15)) << 16; 7442 // op: lane 7443 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 7444 Value |= (op & UINT64_C(1)) << 7; 7445 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7446 break; 7447 } 7448 case ARM::VST3LNd16: 7449 case ARM::VST3LNq16: { 7450 // op: Vd 7451 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7452 Value |= (op & UINT64_C(16)) << 18; 7453 Value |= (op & UINT64_C(15)) << 12; 7454 // op: Rn 7455 op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI); 7456 Value |= (op & UINT64_C(15)) << 16; 7457 // op: lane 7458 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 7459 Value |= (op & UINT64_C(3)) << 6; 7460 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7461 break; 7462 } 7463 case ARM::VST3LNd8: { 7464 // op: Vd 7465 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7466 Value |= (op & UINT64_C(16)) << 18; 7467 Value |= (op & UINT64_C(15)) << 12; 7468 // op: Rn 7469 op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI); 7470 Value |= (op & UINT64_C(15)) << 16; 7471 // op: lane 7472 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 7473 Value |= (op & UINT64_C(7)) << 5; 7474 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7475 break; 7476 } 7477 case ARM::VST1LNd16: { 7478 // op: Vd 7479 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7480 Value |= (op & UINT64_C(16)) << 18; 7481 Value |= (op & UINT64_C(15)) << 12; 7482 // op: Rn 7483 op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI); 7484 Value |= (op & UINT64_C(15)) << 16; 7485 Value |= op & UINT64_C(16); 7486 // op: lane 7487 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 7488 Value |= (op & UINT64_C(3)) << 6; 7489 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7490 break; 7491 } 7492 case ARM::VST2LNd32: 7493 case ARM::VST2LNq32: { 7494 // op: Vd 7495 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7496 Value |= (op & UINT64_C(16)) << 18; 7497 Value |= (op & UINT64_C(15)) << 12; 7498 // op: Rn 7499 op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI); 7500 Value |= (op & UINT64_C(15)) << 16; 7501 Value |= op & UINT64_C(16); 7502 // op: lane 7503 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7504 Value |= (op & UINT64_C(1)) << 7; 7505 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7506 break; 7507 } 7508 case ARM::VST2LNd16: 7509 case ARM::VST2LNq16: { 7510 // op: Vd 7511 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7512 Value |= (op & UINT64_C(16)) << 18; 7513 Value |= (op & UINT64_C(15)) << 12; 7514 // op: Rn 7515 op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI); 7516 Value |= (op & UINT64_C(15)) << 16; 7517 Value |= op & UINT64_C(16); 7518 // op: lane 7519 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7520 Value |= (op & UINT64_C(3)) << 6; 7521 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7522 break; 7523 } 7524 case ARM::VST2LNd8: { 7525 // op: Vd 7526 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7527 Value |= (op & UINT64_C(16)) << 18; 7528 Value |= (op & UINT64_C(15)) << 12; 7529 // op: Rn 7530 op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI); 7531 Value |= (op & UINT64_C(15)) << 16; 7532 Value |= op & UINT64_C(16); 7533 // op: lane 7534 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7535 Value |= (op & UINT64_C(7)) << 5; 7536 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7537 break; 7538 } 7539 case ARM::VST4LNd16: 7540 case ARM::VST4LNq16: { 7541 // op: Vd 7542 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7543 Value |= (op & UINT64_C(16)) << 18; 7544 Value |= (op & UINT64_C(15)) << 12; 7545 // op: Rn 7546 op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI); 7547 Value |= (op & UINT64_C(15)) << 16; 7548 Value |= op & UINT64_C(16); 7549 // op: lane 7550 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 7551 Value |= (op & UINT64_C(3)) << 6; 7552 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7553 break; 7554 } 7555 case ARM::VST4LNd8: { 7556 // op: Vd 7557 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7558 Value |= (op & UINT64_C(16)) << 18; 7559 Value |= (op & UINT64_C(15)) << 12; 7560 // op: Rn 7561 op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI); 7562 Value |= (op & UINT64_C(15)) << 16; 7563 Value |= op & UINT64_C(16); 7564 // op: lane 7565 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 7566 Value |= (op & UINT64_C(7)) << 5; 7567 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7568 break; 7569 } 7570 case ARM::VST1d16: 7571 case ARM::VST1d16T: 7572 case ARM::VST1d32: 7573 case ARM::VST1d32T: 7574 case ARM::VST1d64: 7575 case ARM::VST1d64T: 7576 case ARM::VST1d8: 7577 case ARM::VST1d8T: 7578 case ARM::VST3d16: 7579 case ARM::VST3d32: 7580 case ARM::VST3d8: 7581 case ARM::VST3q16: 7582 case ARM::VST3q32: 7583 case ARM::VST3q8: { 7584 // op: Vd 7585 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7586 Value |= (op & UINT64_C(16)) << 18; 7587 Value |= (op & UINT64_C(15)) << 12; 7588 // op: Rn 7589 op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI); 7590 Value |= (op & UINT64_C(15)) << 16; 7591 Value |= op & UINT64_C(16); 7592 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7593 break; 7594 } 7595 case ARM::VST4LNd32: 7596 case ARM::VST4LNq32: { 7597 // op: Vd 7598 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7599 Value |= (op & UINT64_C(16)) << 18; 7600 Value |= (op & UINT64_C(15)) << 12; 7601 // op: Rn 7602 op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI); 7603 Value |= (op & UINT64_C(15)) << 16; 7604 Value |= op & UINT64_C(48); 7605 // op: lane 7606 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 7607 Value |= (op & UINT64_C(1)) << 7; 7608 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7609 break; 7610 } 7611 case ARM::VST1d16Q: 7612 case ARM::VST1d32Q: 7613 case ARM::VST1d64Q: 7614 case ARM::VST1d8Q: 7615 case ARM::VST1q16: 7616 case ARM::VST1q32: 7617 case ARM::VST1q64: 7618 case ARM::VST1q8: 7619 case ARM::VST2b16: 7620 case ARM::VST2b32: 7621 case ARM::VST2b8: 7622 case ARM::VST2d16: 7623 case ARM::VST2d32: 7624 case ARM::VST2d8: 7625 case ARM::VST2q16: 7626 case ARM::VST2q32: 7627 case ARM::VST2q8: 7628 case ARM::VST4d16: 7629 case ARM::VST4d32: 7630 case ARM::VST4d8: 7631 case ARM::VST4q16: 7632 case ARM::VST4q32: 7633 case ARM::VST4q8: { 7634 // op: Vd 7635 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7636 Value |= (op & UINT64_C(16)) << 18; 7637 Value |= (op & UINT64_C(15)) << 12; 7638 // op: Rn 7639 op = getAddrMode6AddressOpValue(MI, 0, Fixups, STI); 7640 Value |= (op & UINT64_C(15)) << 16; 7641 Value |= op & UINT64_C(48); 7642 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7643 break; 7644 } 7645 case ARM::VST1LNd32: { 7646 // op: Vd 7647 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 7648 Value |= (op & UINT64_C(16)) << 18; 7649 Value |= (op & UINT64_C(15)) << 12; 7650 // op: Rn 7651 op = getAddrMode6OneLane32AddressOpValue(MI, 0, Fixups, STI); 7652 Value |= (op & UINT64_C(15)) << 16; 7653 Value |= op & UINT64_C(48); 7654 // op: lane 7655 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 7656 Value |= (op & UINT64_C(1)) << 7; 7657 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7658 break; 7659 } 7660 case ARM::VST1d16wb_fixed: 7661 case ARM::VST1d32wb_fixed: 7662 case ARM::VST1d64wb_fixed: 7663 case ARM::VST1d8wb_fixed: { 7664 // op: Vd 7665 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 7666 Value |= (op & UINT64_C(16)) << 18; 7667 Value |= (op & UINT64_C(15)) << 12; 7668 // op: Rn 7669 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 7670 Value |= (op & UINT64_C(15)) << 16; 7671 Value |= op & UINT64_C(16); 7672 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7673 break; 7674 } 7675 case ARM::VST1d16Qwb_fixed: 7676 case ARM::VST1d16Twb_fixed: 7677 case ARM::VST1d32Qwb_fixed: 7678 case ARM::VST1d32Twb_fixed: 7679 case ARM::VST1d64Qwb_fixed: 7680 case ARM::VST1d64Twb_fixed: 7681 case ARM::VST1d8Qwb_fixed: 7682 case ARM::VST1d8Twb_fixed: 7683 case ARM::VST1q16wb_fixed: 7684 case ARM::VST1q32wb_fixed: 7685 case ARM::VST1q64wb_fixed: 7686 case ARM::VST1q8wb_fixed: 7687 case ARM::VST2b16wb_fixed: 7688 case ARM::VST2b32wb_fixed: 7689 case ARM::VST2b8wb_fixed: 7690 case ARM::VST2d16wb_fixed: 7691 case ARM::VST2d32wb_fixed: 7692 case ARM::VST2d8wb_fixed: 7693 case ARM::VST2q16wb_fixed: 7694 case ARM::VST2q32wb_fixed: 7695 case ARM::VST2q8wb_fixed: { 7696 // op: Vd 7697 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 7698 Value |= (op & UINT64_C(16)) << 18; 7699 Value |= (op & UINT64_C(15)) << 12; 7700 // op: Rn 7701 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 7702 Value |= (op & UINT64_C(15)) << 16; 7703 Value |= op & UINT64_C(48); 7704 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7705 break; 7706 } 7707 case ARM::VST1LNd8_UPD: { 7708 // op: Vd 7709 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7710 Value |= (op & UINT64_C(16)) << 18; 7711 Value |= (op & UINT64_C(15)) << 12; 7712 // op: Rn 7713 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 7714 Value |= (op & UINT64_C(15)) << 16; 7715 // op: Rm 7716 op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 7717 Value |= op & UINT64_C(15); 7718 // op: lane 7719 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 7720 Value |= (op & UINT64_C(7)) << 5; 7721 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7722 break; 7723 } 7724 case ARM::VST3LNd32_UPD: 7725 case ARM::VST3LNq32_UPD: { 7726 // op: Vd 7727 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7728 Value |= (op & UINT64_C(16)) << 18; 7729 Value |= (op & UINT64_C(15)) << 12; 7730 // op: Rn 7731 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 7732 Value |= (op & UINT64_C(15)) << 16; 7733 // op: Rm 7734 op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 7735 Value |= op & UINT64_C(15); 7736 // op: lane 7737 op = getMachineOpValue(MI, MI.getOperand(7), Fixups, STI); 7738 Value |= (op & UINT64_C(1)) << 7; 7739 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7740 break; 7741 } 7742 case ARM::VST3LNd16_UPD: 7743 case ARM::VST3LNq16_UPD: { 7744 // op: Vd 7745 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7746 Value |= (op & UINT64_C(16)) << 18; 7747 Value |= (op & UINT64_C(15)) << 12; 7748 // op: Rn 7749 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 7750 Value |= (op & UINT64_C(15)) << 16; 7751 // op: Rm 7752 op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 7753 Value |= op & UINT64_C(15); 7754 // op: lane 7755 op = getMachineOpValue(MI, MI.getOperand(7), Fixups, STI); 7756 Value |= (op & UINT64_C(3)) << 6; 7757 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7758 break; 7759 } 7760 case ARM::VST3LNd8_UPD: { 7761 // op: Vd 7762 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7763 Value |= (op & UINT64_C(16)) << 18; 7764 Value |= (op & UINT64_C(15)) << 12; 7765 // op: Rn 7766 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 7767 Value |= (op & UINT64_C(15)) << 16; 7768 // op: Rm 7769 op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 7770 Value |= op & UINT64_C(15); 7771 // op: lane 7772 op = getMachineOpValue(MI, MI.getOperand(7), Fixups, STI); 7773 Value |= (op & UINT64_C(7)) << 5; 7774 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7775 break; 7776 } 7777 case ARM::VST1LNd16_UPD: { 7778 // op: Vd 7779 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7780 Value |= (op & UINT64_C(16)) << 18; 7781 Value |= (op & UINT64_C(15)) << 12; 7782 // op: Rn 7783 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 7784 Value |= (op & UINT64_C(15)) << 16; 7785 Value |= op & UINT64_C(16); 7786 // op: Rm 7787 op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 7788 Value |= op & UINT64_C(15); 7789 // op: lane 7790 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 7791 Value |= (op & UINT64_C(3)) << 6; 7792 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7793 break; 7794 } 7795 case ARM::VST2LNd32_UPD: 7796 case ARM::VST2LNq32_UPD: { 7797 // op: Vd 7798 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7799 Value |= (op & UINT64_C(16)) << 18; 7800 Value |= (op & UINT64_C(15)) << 12; 7801 // op: Rn 7802 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 7803 Value |= (op & UINT64_C(15)) << 16; 7804 Value |= op & UINT64_C(16); 7805 // op: Rm 7806 op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 7807 Value |= op & UINT64_C(15); 7808 // op: lane 7809 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 7810 Value |= (op & UINT64_C(1)) << 7; 7811 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7812 break; 7813 } 7814 case ARM::VST2LNd16_UPD: 7815 case ARM::VST2LNq16_UPD: { 7816 // op: Vd 7817 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7818 Value |= (op & UINT64_C(16)) << 18; 7819 Value |= (op & UINT64_C(15)) << 12; 7820 // op: Rn 7821 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 7822 Value |= (op & UINT64_C(15)) << 16; 7823 Value |= op & UINT64_C(16); 7824 // op: Rm 7825 op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 7826 Value |= op & UINT64_C(15); 7827 // op: lane 7828 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 7829 Value |= (op & UINT64_C(3)) << 6; 7830 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7831 break; 7832 } 7833 case ARM::VST2LNd8_UPD: { 7834 // op: Vd 7835 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7836 Value |= (op & UINT64_C(16)) << 18; 7837 Value |= (op & UINT64_C(15)) << 12; 7838 // op: Rn 7839 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 7840 Value |= (op & UINT64_C(15)) << 16; 7841 Value |= op & UINT64_C(16); 7842 // op: Rm 7843 op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 7844 Value |= op & UINT64_C(15); 7845 // op: lane 7846 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 7847 Value |= (op & UINT64_C(7)) << 5; 7848 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7849 break; 7850 } 7851 case ARM::VST4LNd16_UPD: 7852 case ARM::VST4LNq16_UPD: { 7853 // op: Vd 7854 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7855 Value |= (op & UINT64_C(16)) << 18; 7856 Value |= (op & UINT64_C(15)) << 12; 7857 // op: Rn 7858 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 7859 Value |= (op & UINT64_C(15)) << 16; 7860 Value |= op & UINT64_C(16); 7861 // op: Rm 7862 op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 7863 Value |= op & UINT64_C(15); 7864 // op: lane 7865 op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI); 7866 Value |= (op & UINT64_C(3)) << 6; 7867 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7868 break; 7869 } 7870 case ARM::VST4LNd8_UPD: { 7871 // op: Vd 7872 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7873 Value |= (op & UINT64_C(16)) << 18; 7874 Value |= (op & UINT64_C(15)) << 12; 7875 // op: Rn 7876 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 7877 Value |= (op & UINT64_C(15)) << 16; 7878 Value |= op & UINT64_C(16); 7879 // op: Rm 7880 op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 7881 Value |= op & UINT64_C(15); 7882 // op: lane 7883 op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI); 7884 Value |= (op & UINT64_C(7)) << 5; 7885 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7886 break; 7887 } 7888 case ARM::VST3d16_UPD: 7889 case ARM::VST3d32_UPD: 7890 case ARM::VST3d8_UPD: 7891 case ARM::VST3q16_UPD: 7892 case ARM::VST3q32_UPD: 7893 case ARM::VST3q8_UPD: { 7894 // op: Vd 7895 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7896 Value |= (op & UINT64_C(16)) << 18; 7897 Value |= (op & UINT64_C(15)) << 12; 7898 // op: Rn 7899 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 7900 Value |= (op & UINT64_C(15)) << 16; 7901 Value |= op & UINT64_C(16); 7902 // op: Rm 7903 op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 7904 Value |= op & UINT64_C(15); 7905 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7906 break; 7907 } 7908 case ARM::VST1d16wb_register: 7909 case ARM::VST1d32wb_register: 7910 case ARM::VST1d64wb_register: 7911 case ARM::VST1d8wb_register: { 7912 // op: Vd 7913 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7914 Value |= (op & UINT64_C(16)) << 18; 7915 Value |= (op & UINT64_C(15)) << 12; 7916 // op: Rn 7917 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 7918 Value |= (op & UINT64_C(15)) << 16; 7919 Value |= op & UINT64_C(16); 7920 // op: Rm 7921 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 7922 Value |= op & UINT64_C(15); 7923 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7924 break; 7925 } 7926 case ARM::VST4LNd32_UPD: 7927 case ARM::VST4LNq32_UPD: { 7928 // op: Vd 7929 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7930 Value |= (op & UINT64_C(16)) << 18; 7931 Value |= (op & UINT64_C(15)) << 12; 7932 // op: Rn 7933 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 7934 Value |= (op & UINT64_C(15)) << 16; 7935 Value |= op & UINT64_C(48); 7936 // op: Rm 7937 op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 7938 Value |= op & UINT64_C(15); 7939 // op: lane 7940 op = getMachineOpValue(MI, MI.getOperand(8), Fixups, STI); 7941 Value |= (op & UINT64_C(1)) << 7; 7942 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7943 break; 7944 } 7945 case ARM::VST4d16_UPD: 7946 case ARM::VST4d32_UPD: 7947 case ARM::VST4d8_UPD: 7948 case ARM::VST4q16_UPD: 7949 case ARM::VST4q32_UPD: 7950 case ARM::VST4q8_UPD: { 7951 // op: Vd 7952 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7953 Value |= (op & UINT64_C(16)) << 18; 7954 Value |= (op & UINT64_C(15)) << 12; 7955 // op: Rn 7956 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 7957 Value |= (op & UINT64_C(15)) << 16; 7958 Value |= op & UINT64_C(48); 7959 // op: Rm 7960 op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 7961 Value |= op & UINT64_C(15); 7962 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7963 break; 7964 } 7965 case ARM::VST1d16Qwb_register: 7966 case ARM::VST1d16Twb_register: 7967 case ARM::VST1d32Qwb_register: 7968 case ARM::VST1d32Twb_register: 7969 case ARM::VST1d64Qwb_register: 7970 case ARM::VST1d64Twb_register: 7971 case ARM::VST1d8Qwb_register: 7972 case ARM::VST1d8Twb_register: 7973 case ARM::VST1q16wb_register: 7974 case ARM::VST1q32wb_register: 7975 case ARM::VST1q64wb_register: 7976 case ARM::VST1q8wb_register: 7977 case ARM::VST2b16wb_register: 7978 case ARM::VST2b32wb_register: 7979 case ARM::VST2b8wb_register: 7980 case ARM::VST2d16wb_register: 7981 case ARM::VST2d32wb_register: 7982 case ARM::VST2d8wb_register: 7983 case ARM::VST2q16wb_register: 7984 case ARM::VST2q32wb_register: 7985 case ARM::VST2q8wb_register: { 7986 // op: Vd 7987 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 7988 Value |= (op & UINT64_C(16)) << 18; 7989 Value |= (op & UINT64_C(15)) << 12; 7990 // op: Rn 7991 op = getAddrMode6AddressOpValue(MI, 1, Fixups, STI); 7992 Value |= (op & UINT64_C(15)) << 16; 7993 Value |= op & UINT64_C(48); 7994 // op: Rm 7995 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 7996 Value |= op & UINT64_C(15); 7997 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 7998 break; 7999 } 8000 case ARM::VST1LNd32_UPD: { 8001 // op: Vd 8002 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 8003 Value |= (op & UINT64_C(16)) << 18; 8004 Value |= (op & UINT64_C(15)) << 12; 8005 // op: Rn 8006 op = getAddrMode6OneLane32AddressOpValue(MI, 1, Fixups, STI); 8007 Value |= (op & UINT64_C(15)) << 16; 8008 Value |= op & UINT64_C(48); 8009 // op: Rm 8010 op = getAddrMode6OffsetOpValue(MI, 3, Fixups, STI); 8011 Value |= op & UINT64_C(15); 8012 // op: lane 8013 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 8014 Value |= (op & UINT64_C(1)) << 7; 8015 Value = NEONThumb2LoadStorePostEncoder(MI, Value, STI); 8016 break; 8017 } 8018 case ARM::LDC2L_OFFSET: 8019 case ARM::LDC2L_PRE: 8020 case ARM::LDC2_OFFSET: 8021 case ARM::LDC2_PRE: 8022 case ARM::STC2L_OFFSET: 8023 case ARM::STC2L_PRE: 8024 case ARM::STC2_OFFSET: 8025 case ARM::STC2_PRE: 8026 case ARM::t2LDC2L_OFFSET: 8027 case ARM::t2LDC2L_PRE: 8028 case ARM::t2LDC2_OFFSET: 8029 case ARM::t2LDC2_PRE: 8030 case ARM::t2LDCL_OFFSET: 8031 case ARM::t2LDCL_PRE: 8032 case ARM::t2LDC_OFFSET: 8033 case ARM::t2LDC_PRE: 8034 case ARM::t2STC2L_OFFSET: 8035 case ARM::t2STC2L_PRE: 8036 case ARM::t2STC2_OFFSET: 8037 case ARM::t2STC2_PRE: 8038 case ARM::t2STCL_OFFSET: 8039 case ARM::t2STCL_PRE: 8040 case ARM::t2STC_OFFSET: 8041 case ARM::t2STC_PRE: { 8042 // op: addr 8043 op = getAddrMode5OpValue(MI, 2, Fixups, STI); 8044 Value |= (op & UINT64_C(256)) << 15; 8045 Value |= (op & UINT64_C(7680)) << 7; 8046 Value |= op & UINT64_C(255); 8047 // op: cop 8048 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8049 Value |= (op & UINT64_C(15)) << 8; 8050 // op: CRd 8051 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8052 Value |= (op & UINT64_C(15)) << 12; 8053 break; 8054 } 8055 case ARM::t2PLDWi12: 8056 case ARM::t2PLDi12: 8057 case ARM::t2PLIi12: { 8058 // op: addr 8059 op = getAddrModeImm12OpValue(MI, 0, Fixups, STI); 8060 Value |= (op & UINT64_C(122880)) << 3; 8061 Value |= op & UINT64_C(4095); 8062 break; 8063 } 8064 case ARM::PLDWi12: 8065 case ARM::PLDi12: 8066 case ARM::PLIi12: { 8067 // op: addr 8068 op = getAddrModeImm12OpValue(MI, 0, Fixups, STI); 8069 Value |= (op & UINT64_C(4096)) << 11; 8070 Value |= (op & UINT64_C(122880)) << 3; 8071 Value |= op & UINT64_C(4095); 8072 break; 8073 } 8074 case ARM::t2PLDpci: 8075 case ARM::t2PLIpci: { 8076 // op: addr 8077 op = getAddrModeImm12OpValue(MI, 0, Fixups, STI); 8078 Value |= (op & UINT64_C(4096)) << 11; 8079 Value |= op & UINT64_C(4095); 8080 break; 8081 } 8082 case ARM::t2LDAEXB: 8083 case ARM::t2LDAEXH: 8084 case ARM::t2LDREXB: 8085 case ARM::t2LDREXH: { 8086 // op: addr 8087 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8088 Value |= (op & UINT64_C(15)) << 16; 8089 // op: Rt 8090 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8091 Value |= (op & UINT64_C(15)) << 12; 8092 break; 8093 } 8094 case ARM::t2LDAEXD: 8095 case ARM::t2LDREXD: { 8096 // op: addr 8097 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8098 Value |= (op & UINT64_C(15)) << 16; 8099 // op: Rt 8100 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8101 Value |= (op & UINT64_C(15)) << 12; 8102 // op: Rt2 8103 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8104 Value |= (op & UINT64_C(15)) << 8; 8105 break; 8106 } 8107 case ARM::t2PLDWi8: 8108 case ARM::t2PLDi8: 8109 case ARM::t2PLIi8: { 8110 // op: addr 8111 op = getT2AddrModeImm8OpValue(MI, 0, Fixups, STI); 8112 Value |= (op & UINT64_C(7680)) << 7; 8113 Value |= op & UINT64_C(255); 8114 break; 8115 } 8116 case ARM::t2PLDWs: 8117 case ARM::t2PLDs: 8118 case ARM::t2PLIs: { 8119 // op: addr 8120 op = getT2AddrModeSORegOpValue(MI, 0, Fixups, STI); 8121 Value |= (op & UINT64_C(960)) << 10; 8122 Value |= (op & UINT64_C(3)) << 4; 8123 Value |= (op & UINT64_C(60)) >> 2; 8124 break; 8125 } 8126 case ARM::t2MSRbanked: { 8127 // op: banked 8128 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8129 Value |= (op & UINT64_C(32)) << 15; 8130 Value |= (op & UINT64_C(15)) << 8; 8131 Value |= op & UINT64_C(16); 8132 // op: Rn 8133 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8134 Value |= (op & UINT64_C(15)) << 16; 8135 break; 8136 } 8137 case ARM::t2MRSbanked: { 8138 // op: banked 8139 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8140 Value |= (op & UINT64_C(32)) << 15; 8141 Value |= (op & UINT64_C(15)) << 16; 8142 Value |= op & UINT64_C(16); 8143 // op: Rd 8144 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8145 Value |= (op & UINT64_C(15)) << 8; 8146 break; 8147 } 8148 case ARM::t2IT: { 8149 // op: cc 8150 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8151 Value |= (op & UINT64_C(15)) << 4; 8152 // op: mask 8153 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8154 Value |= op & UINT64_C(15); 8155 break; 8156 } 8157 case ARM::tADDrSPi: { 8158 // op: dst 8159 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8160 Value |= (op & UINT64_C(7)) << 8; 8161 // op: imm 8162 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8163 Value |= op & UINT64_C(255); 8164 break; 8165 } 8166 case ARM::BX: { 8167 // op: dst 8168 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8169 Value |= op & UINT64_C(15); 8170 break; 8171 } 8172 case ARM::tPICADD: { 8173 // op: dst 8174 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8175 Value |= op & UINT64_C(7); 8176 break; 8177 } 8178 case ARM::tSETEND: { 8179 // op: end 8180 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8181 Value |= (op & UINT64_C(1)) << 3; 8182 break; 8183 } 8184 case ARM::SETEND: { 8185 // op: end 8186 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8187 Value |= (op & UINT64_C(1)) << 9; 8188 break; 8189 } 8190 case ARM::BL: { 8191 // op: func 8192 op = getARMBLTargetOpValue(MI, 0, Fixups, STI); 8193 Value |= op & UINT64_C(16777215); 8194 break; 8195 } 8196 case ARM::t2BXJ: { 8197 // op: func 8198 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8199 Value |= (op & UINT64_C(15)) << 16; 8200 break; 8201 } 8202 case ARM::BLX: { 8203 // op: func 8204 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8205 Value |= op & UINT64_C(15); 8206 break; 8207 } 8208 case ARM::tBLXNSr: 8209 case ARM::tBLXr: { 8210 // op: func 8211 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8212 Value |= (op & UINT64_C(15)) << 3; 8213 break; 8214 } 8215 case ARM::tBL: { 8216 // op: func 8217 op = getThumbBLTargetOpValue(MI, 2, Fixups, STI); 8218 Value |= (op & UINT64_C(8388608)) << 3; 8219 Value |= (op & UINT64_C(2095104)) << 5; 8220 Value |= (op & UINT64_C(4194304)) >> 9; 8221 Value |= (op & UINT64_C(2097152)) >> 10; 8222 Value |= op & UINT64_C(2047); 8223 break; 8224 } 8225 case ARM::tBLXi: { 8226 // op: func 8227 op = getThumbBLXTargetOpValue(MI, 2, Fixups, STI); 8228 Value |= (op & UINT64_C(8388608)) << 3; 8229 Value |= (op & UINT64_C(2095104)) << 5; 8230 Value |= (op & UINT64_C(4194304)) >> 9; 8231 Value |= (op & UINT64_C(2097152)) >> 10; 8232 Value |= op & UINT64_C(2046); 8233 break; 8234 } 8235 case ARM::t2SETPAN: { 8236 // op: imm 8237 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8238 Value |= (op & UINT64_C(1)) << 3; 8239 break; 8240 } 8241 case ARM::SETPAN: { 8242 // op: imm 8243 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8244 Value |= (op & UINT64_C(1)) << 9; 8245 break; 8246 } 8247 case ARM::tHINT: { 8248 // op: imm 8249 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8250 Value |= (op & UINT64_C(15)) << 4; 8251 break; 8252 } 8253 case ARM::HVC: { 8254 // op: imm 8255 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8256 Value |= (op & UINT64_C(65520)) << 4; 8257 Value |= op & UINT64_C(15); 8258 break; 8259 } 8260 case ARM::t2HINT: 8261 case ARM::t2SUBS_PC_LR: 8262 case ARM::tSVC: { 8263 // op: imm 8264 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8265 Value |= op & UINT64_C(255); 8266 break; 8267 } 8268 case ARM::tADDspi: 8269 case ARM::tSUBspi: { 8270 // op: imm 8271 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8272 Value |= op & UINT64_C(127); 8273 break; 8274 } 8275 case ARM::t2HVC: 8276 case ARM::t2UDF: { 8277 // op: imm16 8278 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8279 Value |= (op & UINT64_C(61440)) << 4; 8280 Value |= op & UINT64_C(4095); 8281 break; 8282 } 8283 case ARM::UDF: { 8284 // op: imm16 8285 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8286 Value |= (op & UINT64_C(65520)) << 4; 8287 Value |= op & UINT64_C(15); 8288 break; 8289 } 8290 case ARM::tUDF: { 8291 // op: imm8 8292 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8293 Value |= op & UINT64_C(255); 8294 break; 8295 } 8296 case ARM::tCPS: { 8297 // op: imod 8298 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8299 Value |= (op & UINT64_C(1)) << 4; 8300 // op: iflags 8301 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8302 Value |= op & UINT64_C(7); 8303 break; 8304 } 8305 case ARM::CPS2p: { 8306 // op: imod 8307 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8308 Value |= (op & UINT64_C(3)) << 18; 8309 // op: iflags 8310 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8311 Value |= (op & UINT64_C(7)) << 6; 8312 break; 8313 } 8314 case ARM::CPS3p: { 8315 // op: imod 8316 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8317 Value |= (op & UINT64_C(3)) << 18; 8318 // op: iflags 8319 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8320 Value |= (op & UINT64_C(7)) << 6; 8321 // op: mode 8322 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8323 Value |= op & UINT64_C(31); 8324 break; 8325 } 8326 case ARM::t2CPS2p: { 8327 // op: imod 8328 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8329 Value |= (op & UINT64_C(3)) << 9; 8330 // op: iflags 8331 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8332 Value |= (op & UINT64_C(7)) << 5; 8333 break; 8334 } 8335 case ARM::t2CPS3p: { 8336 // op: imod 8337 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8338 Value |= (op & UINT64_C(3)) << 9; 8339 // op: iflags 8340 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8341 Value |= (op & UINT64_C(7)) << 5; 8342 // op: mode 8343 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8344 Value |= op & UINT64_C(31); 8345 break; 8346 } 8347 case ARM::t2MSR_AR: { 8348 // op: mask 8349 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8350 Value |= (op & UINT64_C(16)) << 16; 8351 Value |= (op & UINT64_C(15)) << 8; 8352 // op: Rn 8353 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8354 Value |= (op & UINT64_C(15)) << 16; 8355 break; 8356 } 8357 case ARM::CPS1p: 8358 case ARM::SRSDA: 8359 case ARM::SRSDA_UPD: 8360 case ARM::SRSDB: 8361 case ARM::SRSDB_UPD: 8362 case ARM::SRSIA: 8363 case ARM::SRSIA_UPD: 8364 case ARM::SRSIB: 8365 case ARM::SRSIB_UPD: 8366 case ARM::t2CPS1p: 8367 case ARM::t2SRSDB: 8368 case ARM::t2SRSDB_UPD: 8369 case ARM::t2SRSIA: 8370 case ARM::t2SRSIA_UPD: { 8371 // op: mode 8372 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8373 Value |= op & UINT64_C(31); 8374 break; 8375 } 8376 case ARM::LDC2L_POST: 8377 case ARM::LDC2_POST: 8378 case ARM::STC2L_POST: 8379 case ARM::STC2_POST: 8380 case ARM::t2LDC2L_POST: 8381 case ARM::t2LDC2_POST: 8382 case ARM::t2LDCL_POST: 8383 case ARM::t2LDC_POST: 8384 case ARM::t2STC2L_POST: 8385 case ARM::t2STC2_POST: 8386 case ARM::t2STCL_POST: 8387 case ARM::t2STC_POST: { 8388 // op: offset 8389 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 8390 Value |= (op & UINT64_C(256)) << 15; 8391 Value |= op & UINT64_C(255); 8392 // op: addr 8393 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8394 Value |= (op & UINT64_C(15)) << 16; 8395 // op: cop 8396 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8397 Value |= (op & UINT64_C(15)) << 8; 8398 // op: CRd 8399 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8400 Value |= (op & UINT64_C(15)) << 12; 8401 break; 8402 } 8403 case ARM::CDP2: 8404 case ARM::t2CDP: 8405 case ARM::t2CDP2: { 8406 // op: opc1 8407 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8408 Value |= (op & UINT64_C(15)) << 20; 8409 // op: CRn 8410 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 8411 Value |= (op & UINT64_C(15)) << 16; 8412 // op: CRd 8413 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8414 Value |= (op & UINT64_C(15)) << 12; 8415 // op: cop 8416 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8417 Value |= (op & UINT64_C(15)) << 8; 8418 // op: opc2 8419 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 8420 Value |= (op & UINT64_C(7)) << 5; 8421 // op: CRm 8422 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 8423 Value |= op & UINT64_C(15); 8424 break; 8425 } 8426 case ARM::t2SMC: { 8427 // op: opt 8428 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8429 Value |= (op & UINT64_C(15)) << 16; 8430 break; 8431 } 8432 case ARM::DMB: 8433 case ARM::DSB: 8434 case ARM::ISB: 8435 case ARM::t2DBG: 8436 case ARM::t2DMB: 8437 case ARM::t2DSB: 8438 case ARM::t2ISB: { 8439 // op: opt 8440 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8441 Value |= op & UINT64_C(15); 8442 break; 8443 } 8444 case ARM::LDC2L_OPTION: 8445 case ARM::LDC2_OPTION: 8446 case ARM::STC2L_OPTION: 8447 case ARM::STC2_OPTION: 8448 case ARM::t2LDC2L_OPTION: 8449 case ARM::t2LDC2_OPTION: 8450 case ARM::t2LDCL_OPTION: 8451 case ARM::t2LDC_OPTION: 8452 case ARM::t2STC2L_OPTION: 8453 case ARM::t2STC2_OPTION: 8454 case ARM::t2STCL_OPTION: 8455 case ARM::t2STC_OPTION: { 8456 // op: option 8457 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 8458 Value |= op & UINT64_C(255); 8459 // op: addr 8460 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8461 Value |= (op & UINT64_C(15)) << 16; 8462 // op: cop 8463 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8464 Value |= (op & UINT64_C(15)) << 8; 8465 // op: CRd 8466 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8467 Value |= (op & UINT64_C(15)) << 12; 8468 break; 8469 } 8470 case ARM::BX_RET: 8471 case ARM::ERET: 8472 case ARM::MOVPCLR: { 8473 // op: p 8474 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8475 Value |= (op & UINT64_C(15)) << 28; 8476 break; 8477 } 8478 case ARM::FMSTAT: { 8479 // op: p 8480 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8481 Value |= (op & UINT64_C(15)) << 28; 8482 Value = VFPThumb2PostEncoder(MI, Value, STI); 8483 break; 8484 } 8485 case ARM::t2Bcc: { 8486 // op: p 8487 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8488 Value |= (op & UINT64_C(15)) << 22; 8489 // op: target 8490 op = getBranchTargetOpValue(MI, 0, Fixups, STI); 8491 Value |= (op & UINT64_C(1048576)) << 6; 8492 Value |= (op & UINT64_C(258048)) << 4; 8493 Value |= (op & UINT64_C(262144)) >> 5; 8494 Value |= (op & UINT64_C(524288)) >> 8; 8495 Value |= (op & UINT64_C(4094)) >> 1; 8496 break; 8497 } 8498 case ARM::VCMPEZD: 8499 case ARM::VCMPZD: { 8500 // op: p 8501 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8502 Value |= (op & UINT64_C(15)) << 28; 8503 // op: Dd 8504 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8505 Value |= (op & UINT64_C(16)) << 18; 8506 Value |= (op & UINT64_C(15)) << 12; 8507 Value = VFPThumb2PostEncoder(MI, Value, STI); 8508 break; 8509 } 8510 case ARM::MRS: 8511 case ARM::MRSsys: { 8512 // op: p 8513 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8514 Value |= (op & UINT64_C(15)) << 28; 8515 // op: Rd 8516 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8517 Value |= (op & UINT64_C(15)) << 12; 8518 break; 8519 } 8520 case ARM::VLDMSIA: 8521 case ARM::VSTMSIA: { 8522 // op: p 8523 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8524 Value |= (op & UINT64_C(15)) << 28; 8525 // op: Rn 8526 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8527 Value |= (op & UINT64_C(15)) << 16; 8528 // op: regs 8529 op = getRegisterListOpValue(MI, 3, Fixups, STI); 8530 Value |= (op & UINT64_C(256)) << 14; 8531 Value |= (op & UINT64_C(7680)) << 3; 8532 Value |= op & UINT64_C(255); 8533 Value = VFPThumb2PostEncoder(MI, Value, STI); 8534 break; 8535 } 8536 case ARM::FLDMXIA: 8537 case ARM::FSTMXIA: { 8538 // op: p 8539 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8540 Value |= (op & UINT64_C(15)) << 28; 8541 // op: Rn 8542 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8543 Value |= (op & UINT64_C(15)) << 16; 8544 // op: regs 8545 op = getRegisterListOpValue(MI, 3, Fixups, STI); 8546 Value |= (op & UINT64_C(3840)) << 4; 8547 Value |= op & UINT64_C(254); 8548 Value = VFPThumb2PostEncoder(MI, Value, STI); 8549 break; 8550 } 8551 case ARM::VLDMDIA: 8552 case ARM::VSTMDIA: { 8553 // op: p 8554 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8555 Value |= (op & UINT64_C(15)) << 28; 8556 // op: Rn 8557 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8558 Value |= (op & UINT64_C(15)) << 16; 8559 // op: regs 8560 op = getRegisterListOpValue(MI, 3, Fixups, STI); 8561 Value |= (op & UINT64_C(4096)) << 10; 8562 Value |= (op & UINT64_C(3840)) << 4; 8563 Value |= op & UINT64_C(254); 8564 Value = VFPThumb2PostEncoder(MI, Value, STI); 8565 break; 8566 } 8567 case ARM::VLLDM: 8568 case ARM::VLSTM: { 8569 // op: p 8570 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8571 Value |= (op & UINT64_C(15)) << 28; 8572 // op: Rn 8573 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8574 Value |= (op & UINT64_C(15)) << 16; 8575 Value = VFPThumb2PostEncoder(MI, Value, STI); 8576 break; 8577 } 8578 case ARM::VMRS: 8579 case ARM::VMRS_FPEXC: 8580 case ARM::VMRS_FPINST: 8581 case ARM::VMRS_FPINST2: 8582 case ARM::VMRS_FPSID: 8583 case ARM::VMRS_MVFR0: 8584 case ARM::VMRS_MVFR1: 8585 case ARM::VMRS_MVFR2: { 8586 // op: p 8587 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8588 Value |= (op & UINT64_C(15)) << 28; 8589 // op: Rt 8590 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8591 Value |= (op & UINT64_C(15)) << 12; 8592 Value = VFPThumb2PostEncoder(MI, Value, STI); 8593 break; 8594 } 8595 case ARM::VCMPEZH: 8596 case ARM::VCMPEZS: 8597 case ARM::VCMPZH: 8598 case ARM::VCMPZS: { 8599 // op: p 8600 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8601 Value |= (op & UINT64_C(15)) << 28; 8602 // op: Sd 8603 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8604 Value |= (op & UINT64_C(1)) << 22; 8605 Value |= (op & UINT64_C(30)) << 11; 8606 Value = VFPThumb2PostEncoder(MI, Value, STI); 8607 break; 8608 } 8609 case ARM::BX_pred: { 8610 // op: p 8611 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8612 Value |= (op & UINT64_C(15)) << 28; 8613 // op: dst 8614 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8615 Value |= op & UINT64_C(15); 8616 break; 8617 } 8618 case ARM::BL_pred: { 8619 // op: p 8620 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8621 Value |= (op & UINT64_C(15)) << 28; 8622 // op: func 8623 op = getARMBLTargetOpValue(MI, 0, Fixups, STI); 8624 Value |= op & UINT64_C(16777215); 8625 break; 8626 } 8627 case ARM::BLX_pred: 8628 case ARM::BXJ: { 8629 // op: p 8630 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8631 Value |= (op & UINT64_C(15)) << 28; 8632 // op: func 8633 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8634 Value |= op & UINT64_C(15); 8635 break; 8636 } 8637 case ARM::HINT: { 8638 // op: p 8639 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8640 Value |= (op & UINT64_C(15)) << 28; 8641 // op: imm 8642 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8643 Value |= op & UINT64_C(255); 8644 break; 8645 } 8646 case ARM::DBG: 8647 case ARM::SMC: { 8648 // op: p 8649 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8650 Value |= (op & UINT64_C(15)) << 28; 8651 // op: opt 8652 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8653 Value |= op & UINT64_C(15); 8654 break; 8655 } 8656 case ARM::LDMDA: 8657 case ARM::LDMDB: 8658 case ARM::LDMIA: 8659 case ARM::LDMIB: 8660 case ARM::STMDA: 8661 case ARM::STMDB: 8662 case ARM::STMIA: 8663 case ARM::STMIB: 8664 case ARM::sysLDMDA: 8665 case ARM::sysLDMDB: 8666 case ARM::sysLDMIA: 8667 case ARM::sysLDMIB: 8668 case ARM::sysSTMDA: 8669 case ARM::sysSTMDB: 8670 case ARM::sysSTMIA: 8671 case ARM::sysSTMIB: { 8672 // op: p 8673 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8674 Value |= (op & UINT64_C(15)) << 28; 8675 // op: regs 8676 op = getRegisterListOpValue(MI, 3, Fixups, STI); 8677 Value |= op & UINT64_C(65535); 8678 // op: Rn 8679 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8680 Value |= (op & UINT64_C(15)) << 16; 8681 break; 8682 } 8683 case ARM::VMSR: 8684 case ARM::VMSR_FPEXC: 8685 case ARM::VMSR_FPINST: 8686 case ARM::VMSR_FPINST2: 8687 case ARM::VMSR_FPSID: { 8688 // op: p 8689 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8690 Value |= (op & UINT64_C(15)) << 28; 8691 // op: src 8692 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8693 Value |= (op & UINT64_C(15)) << 12; 8694 Value = VFPThumb2PostEncoder(MI, Value, STI); 8695 break; 8696 } 8697 case ARM::SVC: { 8698 // op: p 8699 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8700 Value |= (op & UINT64_C(15)) << 28; 8701 // op: svc 8702 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8703 Value |= op & UINT64_C(16777215); 8704 break; 8705 } 8706 case ARM::Bcc: { 8707 // op: p 8708 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8709 Value |= (op & UINT64_C(15)) << 28; 8710 // op: target 8711 op = getARMBranchTargetOpValue(MI, 0, Fixups, STI); 8712 Value |= op & UINT64_C(16777215); 8713 break; 8714 } 8715 case ARM::tBcc: { 8716 // op: p 8717 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8718 Value |= (op & UINT64_C(15)) << 8; 8719 // op: target 8720 op = getThumbBCCTargetOpValue(MI, 0, Fixups, STI); 8721 Value |= op & UINT64_C(255); 8722 break; 8723 } 8724 case ARM::VABSD: 8725 case ARM::VCMPD: 8726 case ARM::VCMPED: 8727 case ARM::VMOVD: 8728 case ARM::VNEGD: 8729 case ARM::VRINTRD: 8730 case ARM::VRINTXD: 8731 case ARM::VRINTZD: 8732 case ARM::VSQRTD: { 8733 // op: p 8734 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8735 Value |= (op & UINT64_C(15)) << 28; 8736 // op: Dd 8737 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8738 Value |= (op & UINT64_C(16)) << 18; 8739 Value |= (op & UINT64_C(15)) << 12; 8740 // op: Dm 8741 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8742 Value |= (op & UINT64_C(16)) << 1; 8743 Value |= op & UINT64_C(15); 8744 Value = VFPThumb2PostEncoder(MI, Value, STI); 8745 break; 8746 } 8747 case ARM::VCVTBHD: 8748 case ARM::VCVTTHD: 8749 case ARM::VSITOD: 8750 case ARM::VUITOD: { 8751 // op: p 8752 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8753 Value |= (op & UINT64_C(15)) << 28; 8754 // op: Dd 8755 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8756 Value |= (op & UINT64_C(16)) << 18; 8757 Value |= (op & UINT64_C(15)) << 12; 8758 // op: Sm 8759 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8760 Value |= (op & UINT64_C(1)) << 5; 8761 Value |= (op & UINT64_C(30)) >> 1; 8762 Value = VFPThumb2PostEncoder(MI, Value, STI); 8763 break; 8764 } 8765 case ARM::FCONSTD: { 8766 // op: p 8767 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8768 Value |= (op & UINT64_C(15)) << 28; 8769 // op: Dd 8770 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8771 Value |= (op & UINT64_C(16)) << 18; 8772 Value |= (op & UINT64_C(15)) << 12; 8773 // op: imm 8774 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8775 Value |= (op & UINT64_C(240)) << 12; 8776 Value |= op & UINT64_C(15); 8777 Value = VFPThumb2PostEncoder(MI, Value, STI); 8778 break; 8779 } 8780 case ARM::VCVTBDH: 8781 case ARM::VCVTTDH: { 8782 // op: p 8783 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8784 Value |= (op & UINT64_C(15)) << 28; 8785 // op: Dm 8786 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8787 Value |= (op & UINT64_C(16)) << 1; 8788 Value |= op & UINT64_C(15); 8789 // op: Sd 8790 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8791 Value |= (op & UINT64_C(1)) << 22; 8792 Value |= (op & UINT64_C(30)) << 11; 8793 Value = VFPThumb2PostEncoder(MI, Value, STI); 8794 break; 8795 } 8796 case ARM::CLZ: 8797 case ARM::RBIT: 8798 case ARM::REV: 8799 case ARM::REV16: 8800 case ARM::REVSH: { 8801 // op: p 8802 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8803 Value |= (op & UINT64_C(15)) << 28; 8804 // op: Rd 8805 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8806 Value |= (op & UINT64_C(15)) << 12; 8807 // op: Rm 8808 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8809 Value |= op & UINT64_C(15); 8810 break; 8811 } 8812 case ARM::MOVi16: { 8813 // op: p 8814 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8815 Value |= (op & UINT64_C(15)) << 28; 8816 // op: Rd 8817 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8818 Value |= (op & UINT64_C(15)) << 12; 8819 // op: imm 8820 op = getHiLo16ImmOpValue(MI, 1, Fixups, STI); 8821 Value |= (op & UINT64_C(61440)) << 4; 8822 Value |= op & UINT64_C(4095); 8823 break; 8824 } 8825 case ARM::ADR: { 8826 // op: p 8827 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8828 Value |= (op & UINT64_C(15)) << 28; 8829 // op: Rd 8830 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8831 Value |= (op & UINT64_C(15)) << 12; 8832 // op: label 8833 op = getAdrLabelOpValue(MI, 1, Fixups, STI); 8834 Value |= (op & UINT64_C(12288)) << 10; 8835 Value |= op & UINT64_C(4095); 8836 break; 8837 } 8838 case ARM::CMNzrr: 8839 case ARM::CMPrr: 8840 case ARM::TEQrr: 8841 case ARM::TSTrr: { 8842 // op: p 8843 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8844 Value |= (op & UINT64_C(15)) << 28; 8845 // op: Rn 8846 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8847 Value |= (op & UINT64_C(15)) << 16; 8848 // op: Rm 8849 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8850 Value |= op & UINT64_C(15); 8851 break; 8852 } 8853 case ARM::CMNri: 8854 case ARM::CMPri: 8855 case ARM::TEQri: 8856 case ARM::TSTri: { 8857 // op: p 8858 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8859 Value |= (op & UINT64_C(15)) << 28; 8860 // op: Rn 8861 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8862 Value |= (op & UINT64_C(15)) << 16; 8863 // op: imm 8864 op = getModImmOpValue(MI, 1, Fixups, STI); 8865 Value |= op & UINT64_C(4095); 8866 break; 8867 } 8868 case ARM::VLDMSDB_UPD: 8869 case ARM::VLDMSIA_UPD: 8870 case ARM::VSTMSDB_UPD: 8871 case ARM::VSTMSIA_UPD: { 8872 // op: p 8873 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8874 Value |= (op & UINT64_C(15)) << 28; 8875 // op: Rn 8876 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8877 Value |= (op & UINT64_C(15)) << 16; 8878 // op: regs 8879 op = getRegisterListOpValue(MI, 4, Fixups, STI); 8880 Value |= (op & UINT64_C(256)) << 14; 8881 Value |= (op & UINT64_C(7680)) << 3; 8882 Value |= op & UINT64_C(255); 8883 Value = VFPThumb2PostEncoder(MI, Value, STI); 8884 break; 8885 } 8886 case ARM::FLDMXDB_UPD: 8887 case ARM::FLDMXIA_UPD: 8888 case ARM::FSTMXDB_UPD: 8889 case ARM::FSTMXIA_UPD: { 8890 // op: p 8891 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8892 Value |= (op & UINT64_C(15)) << 28; 8893 // op: Rn 8894 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8895 Value |= (op & UINT64_C(15)) << 16; 8896 // op: regs 8897 op = getRegisterListOpValue(MI, 4, Fixups, STI); 8898 Value |= (op & UINT64_C(3840)) << 4; 8899 Value |= op & UINT64_C(254); 8900 Value = VFPThumb2PostEncoder(MI, Value, STI); 8901 break; 8902 } 8903 case ARM::VLDMDDB_UPD: 8904 case ARM::VLDMDIA_UPD: 8905 case ARM::VSTMDDB_UPD: 8906 case ARM::VSTMDIA_UPD: { 8907 // op: p 8908 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8909 Value |= (op & UINT64_C(15)) << 28; 8910 // op: Rn 8911 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8912 Value |= (op & UINT64_C(15)) << 16; 8913 // op: regs 8914 op = getRegisterListOpValue(MI, 4, Fixups, STI); 8915 Value |= (op & UINT64_C(4096)) << 10; 8916 Value |= (op & UINT64_C(3840)) << 4; 8917 Value |= op & UINT64_C(254); 8918 Value = VFPThumb2PostEncoder(MI, Value, STI); 8919 break; 8920 } 8921 case ARM::VMOVRH: 8922 case ARM::VMOVRS: { 8923 // op: p 8924 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8925 Value |= (op & UINT64_C(15)) << 28; 8926 // op: Rt 8927 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8928 Value |= (op & UINT64_C(15)) << 12; 8929 // op: Sn 8930 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8931 Value |= (op & UINT64_C(30)) << 15; 8932 Value |= (op & UINT64_C(1)) << 7; 8933 Value = VFPThumb2PostEncoder(MI, Value, STI); 8934 break; 8935 } 8936 case ARM::LDA: 8937 case ARM::LDAB: 8938 case ARM::LDAEX: 8939 case ARM::LDAEXB: 8940 case ARM::LDAEXD: 8941 case ARM::LDAEXH: 8942 case ARM::LDAH: 8943 case ARM::LDREX: 8944 case ARM::LDREXB: 8945 case ARM::LDREXD: 8946 case ARM::LDREXH: { 8947 // op: p 8948 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8949 Value |= (op & UINT64_C(15)) << 28; 8950 // op: Rt 8951 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8952 Value |= (op & UINT64_C(15)) << 12; 8953 // op: addr 8954 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8955 Value |= (op & UINT64_C(15)) << 16; 8956 break; 8957 } 8958 case ARM::STL: 8959 case ARM::STLB: 8960 case ARM::STLH: { 8961 // op: p 8962 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8963 Value |= (op & UINT64_C(15)) << 28; 8964 // op: Rt 8965 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8966 Value |= op & UINT64_C(15); 8967 // op: addr 8968 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8969 Value |= (op & UINT64_C(15)) << 16; 8970 break; 8971 } 8972 case ARM::VCVTSD: 8973 case ARM::VJCVT: 8974 case ARM::VTOSIRD: 8975 case ARM::VTOSIZD: 8976 case ARM::VTOUIRD: 8977 case ARM::VTOUIZD: { 8978 // op: p 8979 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 8980 Value |= (op & UINT64_C(15)) << 28; 8981 // op: Sd 8982 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 8983 Value |= (op & UINT64_C(1)) << 22; 8984 Value |= (op & UINT64_C(30)) << 11; 8985 // op: Dm 8986 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 8987 Value |= (op & UINT64_C(16)) << 1; 8988 Value |= op & UINT64_C(15); 8989 Value = VFPThumb2PostEncoder(MI, Value, STI); 8990 break; 8991 } 8992 case ARM::VABSH: 8993 case ARM::VABSS: 8994 case ARM::VCMPEH: 8995 case ARM::VCMPES: 8996 case ARM::VCMPH: 8997 case ARM::VCMPS: 8998 case ARM::VCVTBHS: 8999 case ARM::VCVTBSH: 9000 case ARM::VCVTTHS: 9001 case ARM::VCVTTSH: 9002 case ARM::VMOVS: 9003 case ARM::VNEGH: 9004 case ARM::VNEGS: 9005 case ARM::VRINTRH: 9006 case ARM::VRINTRS: 9007 case ARM::VRINTXH: 9008 case ARM::VRINTXS: 9009 case ARM::VRINTZH: 9010 case ARM::VRINTZS: 9011 case ARM::VSITOH: 9012 case ARM::VSITOS: 9013 case ARM::VSQRTH: 9014 case ARM::VSQRTS: 9015 case ARM::VTOSIRH: 9016 case ARM::VTOSIRS: 9017 case ARM::VTOSIZH: 9018 case ARM::VTOSIZS: 9019 case ARM::VTOUIRH: 9020 case ARM::VTOUIRS: 9021 case ARM::VTOUIZH: 9022 case ARM::VTOUIZS: 9023 case ARM::VUITOH: 9024 case ARM::VUITOS: { 9025 // op: p 9026 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9027 Value |= (op & UINT64_C(15)) << 28; 9028 // op: Sd 9029 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9030 Value |= (op & UINT64_C(1)) << 22; 9031 Value |= (op & UINT64_C(30)) << 11; 9032 // op: Sm 9033 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9034 Value |= (op & UINT64_C(1)) << 5; 9035 Value |= (op & UINT64_C(30)) >> 1; 9036 Value = VFPThumb2PostEncoder(MI, Value, STI); 9037 break; 9038 } 9039 case ARM::FCONSTH: 9040 case ARM::FCONSTS: { 9041 // op: p 9042 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9043 Value |= (op & UINT64_C(15)) << 28; 9044 // op: Sd 9045 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9046 Value |= (op & UINT64_C(1)) << 22; 9047 Value |= (op & UINT64_C(30)) << 11; 9048 // op: imm 9049 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9050 Value |= (op & UINT64_C(240)) << 12; 9051 Value |= op & UINT64_C(15); 9052 Value = VFPThumb2PostEncoder(MI, Value, STI); 9053 break; 9054 } 9055 case ARM::VCVTDS: { 9056 // op: p 9057 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9058 Value |= (op & UINT64_C(15)) << 28; 9059 // op: Sm 9060 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9061 Value |= (op & UINT64_C(1)) << 5; 9062 Value |= (op & UINT64_C(30)) >> 1; 9063 // op: Dd 9064 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9065 Value |= (op & UINT64_C(16)) << 18; 9066 Value |= (op & UINT64_C(15)) << 12; 9067 Value = VFPThumb2PostEncoder(MI, Value, STI); 9068 break; 9069 } 9070 case ARM::VMOVHR: 9071 case ARM::VMOVSR: { 9072 // op: p 9073 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9074 Value |= (op & UINT64_C(15)) << 28; 9075 // op: Sn 9076 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9077 Value |= (op & UINT64_C(30)) << 15; 9078 Value |= (op & UINT64_C(1)) << 7; 9079 // op: Rt 9080 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9081 Value |= (op & UINT64_C(15)) << 12; 9082 Value = VFPThumb2PostEncoder(MI, Value, STI); 9083 break; 9084 } 9085 case ARM::MSRbanked: { 9086 // op: p 9087 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9088 Value |= (op & UINT64_C(15)) << 28; 9089 // op: banked 9090 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9091 Value |= (op & UINT64_C(32)) << 17; 9092 Value |= (op & UINT64_C(15)) << 16; 9093 Value |= (op & UINT64_C(16)) << 4; 9094 // op: Rn 9095 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9096 Value |= op & UINT64_C(15); 9097 break; 9098 } 9099 case ARM::MRSbanked: { 9100 // op: p 9101 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9102 Value |= (op & UINT64_C(15)) << 28; 9103 // op: banked 9104 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9105 Value |= (op & UINT64_C(32)) << 17; 9106 Value |= (op & UINT64_C(15)) << 16; 9107 Value |= (op & UINT64_C(16)) << 4; 9108 // op: Rd 9109 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9110 Value |= (op & UINT64_C(15)) << 12; 9111 break; 9112 } 9113 case ARM::MSR: { 9114 // op: p 9115 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9116 Value |= (op & UINT64_C(15)) << 28; 9117 // op: mask 9118 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9119 Value |= (op & UINT64_C(16)) << 18; 9120 Value |= (op & UINT64_C(15)) << 16; 9121 // op: Rn 9122 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9123 Value |= op & UINT64_C(15); 9124 break; 9125 } 9126 case ARM::MSRi: { 9127 // op: p 9128 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9129 Value |= (op & UINT64_C(15)) << 28; 9130 // op: mask 9131 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9132 Value |= (op & UINT64_C(16)) << 18; 9133 Value |= (op & UINT64_C(15)) << 16; 9134 // op: imm 9135 op = getModImmOpValue(MI, 1, Fixups, STI); 9136 Value |= op & UINT64_C(4095); 9137 break; 9138 } 9139 case ARM::LDMDA_UPD: 9140 case ARM::LDMDB_UPD: 9141 case ARM::LDMIA_UPD: 9142 case ARM::LDMIB_UPD: 9143 case ARM::STMDA_UPD: 9144 case ARM::STMDB_UPD: 9145 case ARM::STMIA_UPD: 9146 case ARM::STMIB_UPD: 9147 case ARM::sysLDMDA_UPD: 9148 case ARM::sysLDMDB_UPD: 9149 case ARM::sysLDMIA_UPD: 9150 case ARM::sysLDMIB_UPD: 9151 case ARM::sysSTMDA_UPD: 9152 case ARM::sysSTMDB_UPD: 9153 case ARM::sysSTMIA_UPD: 9154 case ARM::sysSTMIB_UPD: { 9155 // op: p 9156 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9157 Value |= (op & UINT64_C(15)) << 28; 9158 // op: regs 9159 op = getRegisterListOpValue(MI, 4, Fixups, STI); 9160 Value |= op & UINT64_C(65535); 9161 // op: Rn 9162 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9163 Value |= (op & UINT64_C(15)) << 16; 9164 break; 9165 } 9166 case ARM::MOVr: 9167 case ARM::MOVr_TC: 9168 case ARM::MVNr: { 9169 // op: p 9170 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9171 Value |= (op & UINT64_C(15)) << 28; 9172 // op: s 9173 op = getCCOutOpValue(MI, 4, Fixups, STI); 9174 Value |= (op & UINT64_C(1)) << 20; 9175 // op: Rd 9176 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9177 Value |= (op & UINT64_C(15)) << 12; 9178 // op: Rm 9179 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9180 Value |= op & UINT64_C(15); 9181 break; 9182 } 9183 case ARM::MOVi: 9184 case ARM::MVNi: { 9185 // op: p 9186 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9187 Value |= (op & UINT64_C(15)) << 28; 9188 // op: s 9189 op = getCCOutOpValue(MI, 4, Fixups, STI); 9190 Value |= (op & UINT64_C(1)) << 20; 9191 // op: Rd 9192 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9193 Value |= (op & UINT64_C(15)) << 12; 9194 // op: imm 9195 op = getModImmOpValue(MI, 1, Fixups, STI); 9196 Value |= op & UINT64_C(4095); 9197 break; 9198 } 9199 case ARM::VADDD: 9200 case ARM::VDIVD: 9201 case ARM::VMULD: 9202 case ARM::VNMULD: 9203 case ARM::VSUBD: { 9204 // op: p 9205 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9206 Value |= (op & UINT64_C(15)) << 28; 9207 // op: Dd 9208 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9209 Value |= (op & UINT64_C(16)) << 18; 9210 Value |= (op & UINT64_C(15)) << 12; 9211 // op: Dn 9212 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9213 Value |= (op & UINT64_C(15)) << 16; 9214 Value |= (op & UINT64_C(16)) << 3; 9215 // op: Dm 9216 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9217 Value |= (op & UINT64_C(16)) << 1; 9218 Value |= op & UINT64_C(15); 9219 Value = VFPThumb2PostEncoder(MI, Value, STI); 9220 break; 9221 } 9222 case ARM::VLDRD: 9223 case ARM::VSTRD: { 9224 // op: p 9225 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9226 Value |= (op & UINT64_C(15)) << 28; 9227 // op: Dd 9228 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9229 Value |= (op & UINT64_C(16)) << 18; 9230 Value |= (op & UINT64_C(15)) << 12; 9231 // op: addr 9232 op = getAddrMode5OpValue(MI, 1, Fixups, STI); 9233 Value |= (op & UINT64_C(256)) << 15; 9234 Value |= (op & UINT64_C(7680)) << 7; 9235 Value |= op & UINT64_C(255); 9236 Value = VFPThumb2PostEncoder(MI, Value, STI); 9237 break; 9238 } 9239 case ARM::VMOVDRR: { 9240 // op: p 9241 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9242 Value |= (op & UINT64_C(15)) << 28; 9243 // op: Dm 9244 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9245 Value |= (op & UINT64_C(16)) << 1; 9246 Value |= op & UINT64_C(15); 9247 // op: Rt 9248 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9249 Value |= (op & UINT64_C(15)) << 12; 9250 // op: Rt2 9251 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9252 Value |= (op & UINT64_C(15)) << 16; 9253 Value = VFPThumb2PostEncoder(MI, Value, STI); 9254 break; 9255 } 9256 case ARM::VMOVRRD: { 9257 // op: p 9258 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9259 Value |= (op & UINT64_C(15)) << 28; 9260 // op: Dm 9261 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9262 Value |= (op & UINT64_C(16)) << 1; 9263 Value |= op & UINT64_C(15); 9264 // op: Rt 9265 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9266 Value |= (op & UINT64_C(15)) << 12; 9267 // op: Rt2 9268 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9269 Value |= (op & UINT64_C(15)) << 16; 9270 Value = VFPThumb2PostEncoder(MI, Value, STI); 9271 break; 9272 } 9273 case ARM::SXTB: 9274 case ARM::SXTB16: 9275 case ARM::SXTH: 9276 case ARM::UXTB: 9277 case ARM::UXTB16: 9278 case ARM::UXTH: { 9279 // op: p 9280 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9281 Value |= (op & UINT64_C(15)) << 28; 9282 // op: Rd 9283 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9284 Value |= (op & UINT64_C(15)) << 12; 9285 // op: Rm 9286 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9287 Value |= op & UINT64_C(15); 9288 // op: rot 9289 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9290 Value |= (op & UINT64_C(3)) << 10; 9291 break; 9292 } 9293 case ARM::SEL: { 9294 // op: p 9295 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9296 Value |= (op & UINT64_C(15)) << 28; 9297 // op: Rd 9298 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9299 Value |= (op & UINT64_C(15)) << 12; 9300 // op: Rn 9301 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9302 Value |= (op & UINT64_C(15)) << 16; 9303 // op: Rm 9304 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9305 Value |= op & UINT64_C(15); 9306 break; 9307 } 9308 case ARM::BFC: { 9309 // op: p 9310 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9311 Value |= (op & UINT64_C(15)) << 28; 9312 // op: Rd 9313 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9314 Value |= (op & UINT64_C(15)) << 12; 9315 // op: imm 9316 op = getBitfieldInvertedMaskOpValue(MI, 2, Fixups, STI); 9317 Value |= (op & UINT64_C(992)) << 11; 9318 Value |= (op & UINT64_C(31)) << 7; 9319 break; 9320 } 9321 case ARM::MOVTi16: { 9322 // op: p 9323 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9324 Value |= (op & UINT64_C(15)) << 28; 9325 // op: Rd 9326 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9327 Value |= (op & UINT64_C(15)) << 12; 9328 // op: imm 9329 op = getHiLo16ImmOpValue(MI, 2, Fixups, STI); 9330 Value |= (op & UINT64_C(61440)) << 4; 9331 Value |= op & UINT64_C(4095); 9332 break; 9333 } 9334 case ARM::SSAT16: 9335 case ARM::USAT16: { 9336 // op: p 9337 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9338 Value |= (op & UINT64_C(15)) << 28; 9339 // op: Rd 9340 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9341 Value |= (op & UINT64_C(15)) << 12; 9342 // op: sat_imm 9343 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9344 Value |= (op & UINT64_C(15)) << 16; 9345 // op: Rn 9346 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9347 Value |= op & UINT64_C(15); 9348 break; 9349 } 9350 case ARM::SDIV: 9351 case ARM::SMMUL: 9352 case ARM::SMMULR: 9353 case ARM::UDIV: 9354 case ARM::USAD8: { 9355 // op: p 9356 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9357 Value |= (op & UINT64_C(15)) << 28; 9358 // op: Rd 9359 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9360 Value |= (op & UINT64_C(15)) << 16; 9361 // op: Rn 9362 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9363 Value |= op & UINT64_C(15); 9364 // op: Rm 9365 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9366 Value |= (op & UINT64_C(15)) << 8; 9367 break; 9368 } 9369 case ARM::CMNzrsi: 9370 case ARM::CMPrsi: 9371 case ARM::TEQrsi: 9372 case ARM::TSTrsi: { 9373 // op: p 9374 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9375 Value |= (op & UINT64_C(15)) << 28; 9376 // op: Rn 9377 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9378 Value |= (op & UINT64_C(15)) << 16; 9379 // op: shift 9380 op = getSORegImmOpValue(MI, 1, Fixups, STI); 9381 Value |= op & UINT64_C(4064); 9382 Value |= op & UINT64_C(15); 9383 break; 9384 } 9385 case ARM::QADD16: 9386 case ARM::QADD8: 9387 case ARM::QASX: 9388 case ARM::QSAX: 9389 case ARM::QSUB16: 9390 case ARM::QSUB8: 9391 case ARM::SADD16: 9392 case ARM::SADD8: 9393 case ARM::SASX: 9394 case ARM::SHADD16: 9395 case ARM::SHADD8: 9396 case ARM::SHASX: 9397 case ARM::SHSAX: 9398 case ARM::SHSUB16: 9399 case ARM::SHSUB8: 9400 case ARM::SSAX: 9401 case ARM::SSUB16: 9402 case ARM::SSUB8: 9403 case ARM::UADD16: 9404 case ARM::UADD8: 9405 case ARM::UASX: 9406 case ARM::UHADD16: 9407 case ARM::UHADD8: 9408 case ARM::UHASX: 9409 case ARM::UHSAX: 9410 case ARM::UHSUB16: 9411 case ARM::UHSUB8: 9412 case ARM::UQADD16: 9413 case ARM::UQADD8: 9414 case ARM::UQASX: 9415 case ARM::UQSAX: 9416 case ARM::UQSUB16: 9417 case ARM::UQSUB8: 9418 case ARM::USAX: 9419 case ARM::USUB16: 9420 case ARM::USUB8: { 9421 // op: p 9422 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9423 Value |= (op & UINT64_C(15)) << 28; 9424 // op: Rn 9425 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9426 Value |= (op & UINT64_C(15)) << 16; 9427 // op: Rd 9428 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9429 Value |= (op & UINT64_C(15)) << 12; 9430 // op: Rm 9431 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9432 Value |= op & UINT64_C(15); 9433 break; 9434 } 9435 case ARM::SMUAD: 9436 case ARM::SMUADX: 9437 case ARM::SMULBB: 9438 case ARM::SMULBT: 9439 case ARM::SMULTB: 9440 case ARM::SMULTT: 9441 case ARM::SMULWB: 9442 case ARM::SMULWT: 9443 case ARM::SMUSD: 9444 case ARM::SMUSDX: { 9445 // op: p 9446 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9447 Value |= (op & UINT64_C(15)) << 28; 9448 // op: Rn 9449 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9450 Value |= op & UINT64_C(15); 9451 // op: Rm 9452 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9453 Value |= (op & UINT64_C(15)) << 8; 9454 // op: Rd 9455 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9456 Value |= (op & UINT64_C(15)) << 16; 9457 break; 9458 } 9459 case ARM::QADD: 9460 case ARM::QDADD: 9461 case ARM::QDSUB: 9462 case ARM::QSUB: { 9463 // op: p 9464 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9465 Value |= (op & UINT64_C(15)) << 28; 9466 // op: Rn 9467 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9468 Value |= (op & UINT64_C(15)) << 16; 9469 // op: Rd 9470 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9471 Value |= (op & UINT64_C(15)) << 12; 9472 // op: Rm 9473 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9474 Value |= op & UINT64_C(15); 9475 break; 9476 } 9477 case ARM::SWP: 9478 case ARM::SWPB: { 9479 // op: p 9480 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9481 Value |= (op & UINT64_C(15)) << 28; 9482 // op: Rt 9483 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9484 Value |= (op & UINT64_C(15)) << 12; 9485 // op: Rt2 9486 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9487 Value |= op & UINT64_C(15); 9488 // op: addr 9489 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9490 Value |= (op & UINT64_C(15)) << 16; 9491 break; 9492 } 9493 case ARM::LDRBi12: 9494 case ARM::LDRi12: 9495 case ARM::STRBi12: 9496 case ARM::STRi12: { 9497 // op: p 9498 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9499 Value |= (op & UINT64_C(15)) << 28; 9500 // op: Rt 9501 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9502 Value |= (op & UINT64_C(15)) << 12; 9503 // op: addr 9504 op = getAddrModeImm12OpValue(MI, 1, Fixups, STI); 9505 Value |= (op & UINT64_C(4096)) << 11; 9506 Value |= (op & UINT64_C(122880)) << 3; 9507 Value |= op & UINT64_C(4095); 9508 break; 9509 } 9510 case ARM::LDRcp: { 9511 // op: p 9512 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9513 Value |= (op & UINT64_C(15)) << 28; 9514 // op: Rt 9515 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9516 Value |= (op & UINT64_C(15)) << 12; 9517 // op: addr 9518 op = getAddrModeImm12OpValue(MI, 1, Fixups, STI); 9519 Value |= (op & UINT64_C(4096)) << 11; 9520 Value |= op & UINT64_C(4095); 9521 break; 9522 } 9523 case ARM::STLEX: 9524 case ARM::STLEXB: 9525 case ARM::STLEXD: 9526 case ARM::STLEXH: 9527 case ARM::STREX: 9528 case ARM::STREXB: 9529 case ARM::STREXD: 9530 case ARM::STREXH: { 9531 // op: p 9532 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9533 Value |= (op & UINT64_C(15)) << 28; 9534 // op: Rt 9535 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9536 Value |= op & UINT64_C(15); 9537 // op: addr 9538 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9539 Value |= (op & UINT64_C(15)) << 16; 9540 // op: Rd 9541 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9542 Value |= (op & UINT64_C(15)) << 12; 9543 break; 9544 } 9545 case ARM::VADDH: 9546 case ARM::VADDS: 9547 case ARM::VDIVH: 9548 case ARM::VDIVS: 9549 case ARM::VMULH: 9550 case ARM::VMULS: 9551 case ARM::VNMULH: 9552 case ARM::VNMULS: 9553 case ARM::VSUBH: 9554 case ARM::VSUBS: { 9555 // op: p 9556 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9557 Value |= (op & UINT64_C(15)) << 28; 9558 // op: Sd 9559 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9560 Value |= (op & UINT64_C(1)) << 22; 9561 Value |= (op & UINT64_C(30)) << 11; 9562 // op: Sn 9563 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9564 Value |= (op & UINT64_C(30)) << 15; 9565 Value |= (op & UINT64_C(1)) << 7; 9566 // op: Sm 9567 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9568 Value |= (op & UINT64_C(1)) << 5; 9569 Value |= (op & UINT64_C(30)) >> 1; 9570 Value = VFPThumb2PostEncoder(MI, Value, STI); 9571 break; 9572 } 9573 case ARM::VLDRH: 9574 case ARM::VSTRH: { 9575 // op: p 9576 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9577 Value |= (op & UINT64_C(15)) << 28; 9578 // op: Sd 9579 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9580 Value |= (op & UINT64_C(1)) << 22; 9581 Value |= (op & UINT64_C(30)) << 11; 9582 // op: addr 9583 op = getAddrMode5FP16OpValue(MI, 1, Fixups, STI); 9584 Value |= (op & UINT64_C(256)) << 15; 9585 Value |= (op & UINT64_C(7680)) << 7; 9586 Value |= op & UINT64_C(255); 9587 Value = VFPThumb2PostEncoder(MI, Value, STI); 9588 break; 9589 } 9590 case ARM::VLDRS: 9591 case ARM::VSTRS: { 9592 // op: p 9593 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9594 Value |= (op & UINT64_C(15)) << 28; 9595 // op: Sd 9596 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9597 Value |= (op & UINT64_C(1)) << 22; 9598 Value |= (op & UINT64_C(30)) << 11; 9599 // op: addr 9600 op = getAddrMode5OpValue(MI, 1, Fixups, STI); 9601 Value |= (op & UINT64_C(256)) << 15; 9602 Value |= (op & UINT64_C(7680)) << 7; 9603 Value |= op & UINT64_C(255); 9604 Value = VFPThumb2PostEncoder(MI, Value, STI); 9605 break; 9606 } 9607 case ARM::VSHTOH: 9608 case ARM::VSHTOS: 9609 case ARM::VSLTOH: 9610 case ARM::VSLTOS: 9611 case ARM::VTOSHH: 9612 case ARM::VTOSHS: 9613 case ARM::VTOSLH: 9614 case ARM::VTOSLS: 9615 case ARM::VTOUHH: 9616 case ARM::VTOUHS: 9617 case ARM::VTOULH: 9618 case ARM::VTOULS: 9619 case ARM::VUHTOH: 9620 case ARM::VUHTOS: 9621 case ARM::VULTOH: 9622 case ARM::VULTOS: { 9623 // op: p 9624 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9625 Value |= (op & UINT64_C(15)) << 28; 9626 // op: fbits 9627 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9628 Value |= (op & UINT64_C(1)) << 5; 9629 Value |= (op & UINT64_C(30)) >> 1; 9630 // op: dst 9631 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9632 Value |= (op & UINT64_C(1)) << 22; 9633 Value |= (op & UINT64_C(30)) << 11; 9634 Value = VFPThumb2PostEncoder(MI, Value, STI); 9635 break; 9636 } 9637 case ARM::VSHTOD: 9638 case ARM::VSLTOD: 9639 case ARM::VTOSHD: 9640 case ARM::VTOSLD: 9641 case ARM::VTOUHD: 9642 case ARM::VTOULD: 9643 case ARM::VUHTOD: 9644 case ARM::VULTOD: { 9645 // op: p 9646 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9647 Value |= (op & UINT64_C(15)) << 28; 9648 // op: fbits 9649 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9650 Value |= (op & UINT64_C(1)) << 5; 9651 Value |= (op & UINT64_C(30)) >> 1; 9652 // op: dst 9653 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9654 Value |= (op & UINT64_C(16)) << 18; 9655 Value |= (op & UINT64_C(15)) << 12; 9656 Value = VFPThumb2PostEncoder(MI, Value, STI); 9657 break; 9658 } 9659 case ARM::ADCrr: 9660 case ARM::ADDrr: 9661 case ARM::ANDrr: 9662 case ARM::BICrr: 9663 case ARM::EORrr: 9664 case ARM::ORRrr: 9665 case ARM::RSBrr: 9666 case ARM::RSCrr: 9667 case ARM::SBCrr: 9668 case ARM::SUBrr: { 9669 // op: p 9670 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9671 Value |= (op & UINT64_C(15)) << 28; 9672 // op: s 9673 op = getCCOutOpValue(MI, 5, Fixups, STI); 9674 Value |= (op & UINT64_C(1)) << 20; 9675 // op: Rd 9676 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9677 Value |= (op & UINT64_C(15)) << 12; 9678 // op: Rn 9679 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9680 Value |= (op & UINT64_C(15)) << 16; 9681 // op: Rm 9682 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9683 Value |= op & UINT64_C(15); 9684 break; 9685 } 9686 case ARM::ADCri: 9687 case ARM::ADDri: 9688 case ARM::ANDri: 9689 case ARM::BICri: 9690 case ARM::EORri: 9691 case ARM::ORRri: 9692 case ARM::RSBri: 9693 case ARM::RSCri: 9694 case ARM::SBCri: 9695 case ARM::SUBri: { 9696 // op: p 9697 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9698 Value |= (op & UINT64_C(15)) << 28; 9699 // op: s 9700 op = getCCOutOpValue(MI, 5, Fixups, STI); 9701 Value |= (op & UINT64_C(1)) << 20; 9702 // op: Rd 9703 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9704 Value |= (op & UINT64_C(15)) << 12; 9705 // op: Rn 9706 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9707 Value |= (op & UINT64_C(15)) << 16; 9708 // op: imm 9709 op = getModImmOpValue(MI, 2, Fixups, STI); 9710 Value |= op & UINT64_C(4095); 9711 break; 9712 } 9713 case ARM::MVNsi: { 9714 // op: p 9715 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9716 Value |= (op & UINT64_C(15)) << 28; 9717 // op: s 9718 op = getCCOutOpValue(MI, 5, Fixups, STI); 9719 Value |= (op & UINT64_C(1)) << 20; 9720 // op: Rd 9721 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9722 Value |= (op & UINT64_C(15)) << 12; 9723 // op: shift 9724 op = getSORegImmOpValue(MI, 1, Fixups, STI); 9725 Value |= op & UINT64_C(4064); 9726 Value |= op & UINT64_C(15); 9727 break; 9728 } 9729 case ARM::MOVsi: { 9730 // op: p 9731 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9732 Value |= (op & UINT64_C(15)) << 28; 9733 // op: s 9734 op = getCCOutOpValue(MI, 5, Fixups, STI); 9735 Value |= (op & UINT64_C(1)) << 20; 9736 // op: Rd 9737 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9738 Value |= (op & UINT64_C(15)) << 12; 9739 // op: src 9740 op = getSORegImmOpValue(MI, 1, Fixups, STI); 9741 Value |= op & UINT64_C(4064); 9742 Value |= op & UINT64_C(15); 9743 break; 9744 } 9745 case ARM::MUL: { 9746 // op: p 9747 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9748 Value |= (op & UINT64_C(15)) << 28; 9749 // op: s 9750 op = getCCOutOpValue(MI, 5, Fixups, STI); 9751 Value |= (op & UINT64_C(1)) << 20; 9752 // op: Rd 9753 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9754 Value |= (op & UINT64_C(15)) << 16; 9755 // op: Rm 9756 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9757 Value |= (op & UINT64_C(15)) << 8; 9758 // op: Rn 9759 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9760 Value |= op & UINT64_C(15); 9761 break; 9762 } 9763 case ARM::VFMAD: 9764 case ARM::VFMSD: 9765 case ARM::VFNMAD: 9766 case ARM::VFNMSD: 9767 case ARM::VMLAD: 9768 case ARM::VMLSD: 9769 case ARM::VNMLAD: 9770 case ARM::VNMLSD: { 9771 // op: p 9772 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9773 Value |= (op & UINT64_C(15)) << 28; 9774 // op: Dd 9775 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9776 Value |= (op & UINT64_C(16)) << 18; 9777 Value |= (op & UINT64_C(15)) << 12; 9778 // op: Dn 9779 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9780 Value |= (op & UINT64_C(15)) << 16; 9781 Value |= (op & UINT64_C(16)) << 3; 9782 // op: Dm 9783 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9784 Value |= (op & UINT64_C(16)) << 1; 9785 Value |= op & UINT64_C(15); 9786 Value = VFPThumb2PostEncoder(MI, Value, STI); 9787 break; 9788 } 9789 case ARM::SXTAB: 9790 case ARM::SXTAB16: 9791 case ARM::SXTAH: 9792 case ARM::UXTAB: 9793 case ARM::UXTAB16: 9794 case ARM::UXTAH: { 9795 // op: p 9796 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9797 Value |= (op & UINT64_C(15)) << 28; 9798 // op: Rd 9799 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9800 Value |= (op & UINT64_C(15)) << 12; 9801 // op: Rm 9802 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9803 Value |= op & UINT64_C(15); 9804 // op: Rn 9805 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9806 Value |= (op & UINT64_C(15)) << 16; 9807 // op: rot 9808 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9809 Value |= (op & UINT64_C(3)) << 10; 9810 break; 9811 } 9812 case ARM::PKHBT: 9813 case ARM::PKHTB: { 9814 // op: p 9815 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9816 Value |= (op & UINT64_C(15)) << 28; 9817 // op: Rd 9818 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9819 Value |= (op & UINT64_C(15)) << 12; 9820 // op: Rn 9821 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9822 Value |= (op & UINT64_C(15)) << 16; 9823 // op: Rm 9824 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9825 Value |= op & UINT64_C(15); 9826 // op: sh 9827 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9828 Value |= (op & UINT64_C(31)) << 7; 9829 break; 9830 } 9831 case ARM::SBFX: 9832 case ARM::UBFX: { 9833 // op: p 9834 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9835 Value |= (op & UINT64_C(15)) << 28; 9836 // op: Rd 9837 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9838 Value |= (op & UINT64_C(15)) << 12; 9839 // op: Rn 9840 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9841 Value |= op & UINT64_C(15); 9842 // op: lsb 9843 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9844 Value |= (op & UINT64_C(31)) << 7; 9845 // op: width 9846 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9847 Value |= (op & UINT64_C(31)) << 16; 9848 break; 9849 } 9850 case ARM::BFI: { 9851 // op: p 9852 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9853 Value |= (op & UINT64_C(15)) << 28; 9854 // op: Rd 9855 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9856 Value |= (op & UINT64_C(15)) << 12; 9857 // op: Rn 9858 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9859 Value |= op & UINT64_C(15); 9860 // op: imm 9861 op = getBitfieldInvertedMaskOpValue(MI, 3, Fixups, STI); 9862 Value |= (op & UINT64_C(992)) << 11; 9863 Value |= (op & UINT64_C(31)) << 7; 9864 break; 9865 } 9866 case ARM::SSAT: 9867 case ARM::USAT: { 9868 // op: p 9869 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9870 Value |= (op & UINT64_C(15)) << 28; 9871 // op: Rd 9872 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9873 Value |= (op & UINT64_C(15)) << 12; 9874 // op: sat_imm 9875 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9876 Value |= (op & UINT64_C(31)) << 16; 9877 // op: Rn 9878 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9879 Value |= op & UINT64_C(15); 9880 // op: sh 9881 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9882 Value |= (op & UINT64_C(31)) << 7; 9883 Value |= (op & UINT64_C(32)) << 1; 9884 break; 9885 } 9886 case ARM::MLS: { 9887 // op: p 9888 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9889 Value |= (op & UINT64_C(15)) << 28; 9890 // op: Rd 9891 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9892 Value |= (op & UINT64_C(15)) << 16; 9893 // op: Rm 9894 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9895 Value |= (op & UINT64_C(15)) << 8; 9896 // op: Rn 9897 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9898 Value |= op & UINT64_C(15); 9899 // op: Ra 9900 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9901 Value |= (op & UINT64_C(15)) << 12; 9902 break; 9903 } 9904 case ARM::SMMLA: 9905 case ARM::SMMLAR: 9906 case ARM::SMMLS: 9907 case ARM::SMMLSR: 9908 case ARM::USADA8: { 9909 // op: p 9910 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9911 Value |= (op & UINT64_C(15)) << 28; 9912 // op: Rd 9913 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9914 Value |= (op & UINT64_C(15)) << 16; 9915 // op: Rn 9916 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9917 Value |= op & UINT64_C(15); 9918 // op: Rm 9919 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9920 Value |= (op & UINT64_C(15)) << 8; 9921 // op: Ra 9922 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9923 Value |= (op & UINT64_C(15)) << 12; 9924 break; 9925 } 9926 case ARM::CMNzrsr: 9927 case ARM::CMPrsr: 9928 case ARM::TEQrsr: 9929 case ARM::TSTrsr: { 9930 // op: p 9931 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9932 Value |= (op & UINT64_C(15)) << 28; 9933 // op: Rn 9934 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9935 Value |= (op & UINT64_C(15)) << 16; 9936 // op: shift 9937 op = getSORegRegOpValue(MI, 1, Fixups, STI); 9938 Value |= op & UINT64_C(3840); 9939 Value |= op & UINT64_C(96); 9940 Value |= op & UINT64_C(15); 9941 break; 9942 } 9943 case ARM::SMLAD: 9944 case ARM::SMLADX: 9945 case ARM::SMLSD: 9946 case ARM::SMLSDX: { 9947 // op: p 9948 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9949 Value |= (op & UINT64_C(15)) << 28; 9950 // op: Rn 9951 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9952 Value |= op & UINT64_C(15); 9953 // op: Rm 9954 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9955 Value |= (op & UINT64_C(15)) << 8; 9956 // op: Ra 9957 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9958 Value |= (op & UINT64_C(15)) << 12; 9959 // op: Rd 9960 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9961 Value |= (op & UINT64_C(15)) << 16; 9962 break; 9963 } 9964 case ARM::SMLABB: 9965 case ARM::SMLABT: 9966 case ARM::SMLATB: 9967 case ARM::SMLATT: 9968 case ARM::SMLAWB: 9969 case ARM::SMLAWT: { 9970 // op: p 9971 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9972 Value |= (op & UINT64_C(15)) << 28; 9973 // op: Rn 9974 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 9975 Value |= op & UINT64_C(15); 9976 // op: Rm 9977 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 9978 Value |= (op & UINT64_C(15)) << 8; 9979 // op: Rd 9980 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9981 Value |= (op & UINT64_C(15)) << 16; 9982 // op: Ra 9983 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 9984 Value |= (op & UINT64_C(15)) << 12; 9985 break; 9986 } 9987 case ARM::LDRB_PRE_IMM: 9988 case ARM::LDR_PRE_IMM: { 9989 // op: p 9990 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 9991 Value |= (op & UINT64_C(15)) << 28; 9992 // op: Rt 9993 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 9994 Value |= (op & UINT64_C(15)) << 12; 9995 // op: addr 9996 op = getAddrModeImm12OpValue(MI, 2, Fixups, STI); 9997 Value |= (op & UINT64_C(4096)) << 11; 9998 Value |= (op & UINT64_C(122880)) << 3; 9999 Value |= op & UINT64_C(4095); 10000 break; 10001 } 10002 case ARM::LDRBrs: 10003 case ARM::LDRrs: 10004 case ARM::STRBrs: 10005 case ARM::STRrs: { 10006 // op: p 10007 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 10008 Value |= (op & UINT64_C(15)) << 28; 10009 // op: Rt 10010 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10011 Value |= (op & UINT64_C(15)) << 12; 10012 // op: shift 10013 op = getLdStSORegOpValue(MI, 1, Fixups, STI); 10014 Value |= (op & UINT64_C(4096)) << 11; 10015 Value |= (op & UINT64_C(122880)) << 3; 10016 Value |= op & UINT64_C(4064); 10017 Value |= op & UINT64_C(15); 10018 break; 10019 } 10020 case ARM::STRB_PRE_IMM: 10021 case ARM::STR_PRE_IMM: { 10022 // op: p 10023 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 10024 Value |= (op & UINT64_C(15)) << 28; 10025 // op: Rt 10026 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10027 Value |= (op & UINT64_C(15)) << 12; 10028 // op: addr 10029 op = getAddrModeImm12OpValue(MI, 2, Fixups, STI); 10030 Value |= (op & UINT64_C(4096)) << 11; 10031 Value |= (op & UINT64_C(122880)) << 3; 10032 Value |= op & UINT64_C(4095); 10033 break; 10034 } 10035 case ARM::VFMAH: 10036 case ARM::VFMAS: 10037 case ARM::VFMSH: 10038 case ARM::VFMSS: 10039 case ARM::VFNMAH: 10040 case ARM::VFNMAS: 10041 case ARM::VFNMSH: 10042 case ARM::VFNMSS: 10043 case ARM::VMLAH: 10044 case ARM::VMLAS: 10045 case ARM::VMLSH: 10046 case ARM::VMLSS: 10047 case ARM::VNMLAH: 10048 case ARM::VNMLAS: 10049 case ARM::VNMLSH: 10050 case ARM::VNMLSS: { 10051 // op: p 10052 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 10053 Value |= (op & UINT64_C(15)) << 28; 10054 // op: Sd 10055 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10056 Value |= (op & UINT64_C(1)) << 22; 10057 Value |= (op & UINT64_C(30)) << 11; 10058 // op: Sn 10059 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10060 Value |= (op & UINT64_C(30)) << 15; 10061 Value |= (op & UINT64_C(1)) << 7; 10062 // op: Sm 10063 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10064 Value |= (op & UINT64_C(1)) << 5; 10065 Value |= (op & UINT64_C(30)) >> 1; 10066 Value = VFPThumb2PostEncoder(MI, Value, STI); 10067 break; 10068 } 10069 case ARM::LDRH: 10070 case ARM::LDRSB: 10071 case ARM::LDRSH: 10072 case ARM::STRH: { 10073 // op: p 10074 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 10075 Value |= (op & UINT64_C(15)) << 28; 10076 // op: addr 10077 op = getAddrMode3OpValue(MI, 1, Fixups, STI); 10078 Value |= (op & UINT64_C(256)) << 15; 10079 Value |= (op & UINT64_C(8192)) << 9; 10080 Value |= (op & UINT64_C(7680)) << 7; 10081 Value |= (op & UINT64_C(240)) << 4; 10082 Value |= op & UINT64_C(15); 10083 // op: Rt 10084 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10085 Value |= (op & UINT64_C(15)) << 12; 10086 break; 10087 } 10088 case ARM::LDCL_OFFSET: 10089 case ARM::LDCL_PRE: 10090 case ARM::LDC_OFFSET: 10091 case ARM::LDC_PRE: 10092 case ARM::STCL_OFFSET: 10093 case ARM::STCL_PRE: 10094 case ARM::STC_OFFSET: 10095 case ARM::STC_PRE: { 10096 // op: p 10097 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 10098 Value |= (op & UINT64_C(15)) << 28; 10099 // op: addr 10100 op = getAddrMode5OpValue(MI, 2, Fixups, STI); 10101 Value |= (op & UINT64_C(256)) << 15; 10102 Value |= (op & UINT64_C(7680)) << 7; 10103 Value |= op & UINT64_C(255); 10104 // op: cop 10105 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10106 Value |= (op & UINT64_C(15)) << 8; 10107 // op: CRd 10108 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10109 Value |= (op & UINT64_C(15)) << 12; 10110 break; 10111 } 10112 case ARM::LDRHTi: 10113 case ARM::LDRSBTi: 10114 case ARM::LDRSHTi: { 10115 // op: p 10116 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 10117 Value |= (op & UINT64_C(15)) << 28; 10118 // op: addr 10119 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10120 Value |= (op & UINT64_C(15)) << 16; 10121 // op: Rt 10122 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10123 Value |= (op & UINT64_C(15)) << 12; 10124 // op: offset 10125 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10126 Value |= (op & UINT64_C(256)) << 15; 10127 Value |= (op & UINT64_C(240)) << 4; 10128 Value |= op & UINT64_C(15); 10129 break; 10130 } 10131 case ARM::STRHTi: { 10132 // op: p 10133 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 10134 Value |= (op & UINT64_C(15)) << 28; 10135 // op: addr 10136 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10137 Value |= (op & UINT64_C(15)) << 16; 10138 // op: Rt 10139 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10140 Value |= (op & UINT64_C(15)) << 12; 10141 // op: offset 10142 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10143 Value |= (op & UINT64_C(256)) << 15; 10144 Value |= (op & UINT64_C(240)) << 4; 10145 Value |= op & UINT64_C(15); 10146 break; 10147 } 10148 case ARM::VMOVSRR: { 10149 // op: p 10150 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 10151 Value |= (op & UINT64_C(15)) << 28; 10152 // op: dst1 10153 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10154 Value |= (op & UINT64_C(1)) << 5; 10155 Value |= (op & UINT64_C(30)) >> 1; 10156 // op: src1 10157 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10158 Value |= (op & UINT64_C(15)) << 12; 10159 // op: src2 10160 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10161 Value |= (op & UINT64_C(15)) << 16; 10162 Value = VFPThumb2PostEncoder(MI, Value, STI); 10163 break; 10164 } 10165 case ARM::LDCL_POST: 10166 case ARM::LDC_POST: 10167 case ARM::STCL_POST: 10168 case ARM::STC_POST: { 10169 // op: p 10170 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 10171 Value |= (op & UINT64_C(15)) << 28; 10172 // op: offset 10173 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10174 Value |= (op & UINT64_C(256)) << 15; 10175 Value |= op & UINT64_C(255); 10176 // op: addr 10177 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10178 Value |= (op & UINT64_C(15)) << 16; 10179 // op: cop 10180 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10181 Value |= (op & UINT64_C(15)) << 8; 10182 // op: CRd 10183 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10184 Value |= (op & UINT64_C(15)) << 12; 10185 break; 10186 } 10187 case ARM::LDCL_OPTION: 10188 case ARM::LDC_OPTION: 10189 case ARM::STCL_OPTION: 10190 case ARM::STC_OPTION: { 10191 // op: p 10192 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 10193 Value |= (op & UINT64_C(15)) << 28; 10194 // op: option 10195 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10196 Value |= op & UINT64_C(255); 10197 // op: addr 10198 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10199 Value |= (op & UINT64_C(15)) << 16; 10200 // op: cop 10201 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10202 Value |= (op & UINT64_C(15)) << 8; 10203 // op: CRd 10204 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10205 Value |= (op & UINT64_C(15)) << 12; 10206 break; 10207 } 10208 case ARM::ADCrsi: 10209 case ARM::ADDrsi: 10210 case ARM::ANDrsi: 10211 case ARM::BICrsi: 10212 case ARM::EORrsi: 10213 case ARM::ORRrsi: 10214 case ARM::RSBrsi: 10215 case ARM::RSCrsi: 10216 case ARM::SBCrsi: 10217 case ARM::SUBrsi: { 10218 // op: p 10219 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 10220 Value |= (op & UINT64_C(15)) << 28; 10221 // op: s 10222 op = getCCOutOpValue(MI, 6, Fixups, STI); 10223 Value |= (op & UINT64_C(1)) << 20; 10224 // op: Rd 10225 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10226 Value |= (op & UINT64_C(15)) << 12; 10227 // op: Rn 10228 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10229 Value |= (op & UINT64_C(15)) << 16; 10230 // op: shift 10231 op = getSORegImmOpValue(MI, 2, Fixups, STI); 10232 Value |= op & UINT64_C(4064); 10233 Value |= op & UINT64_C(15); 10234 break; 10235 } 10236 case ARM::MVNsr: { 10237 // op: p 10238 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 10239 Value |= (op & UINT64_C(15)) << 28; 10240 // op: s 10241 op = getCCOutOpValue(MI, 6, Fixups, STI); 10242 Value |= (op & UINT64_C(1)) << 20; 10243 // op: Rd 10244 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10245 Value |= (op & UINT64_C(15)) << 12; 10246 // op: shift 10247 op = getSORegRegOpValue(MI, 1, Fixups, STI); 10248 Value |= op & UINT64_C(3840); 10249 Value |= op & UINT64_C(96); 10250 Value |= op & UINT64_C(15); 10251 break; 10252 } 10253 case ARM::MOVsr: { 10254 // op: p 10255 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 10256 Value |= (op & UINT64_C(15)) << 28; 10257 // op: s 10258 op = getCCOutOpValue(MI, 6, Fixups, STI); 10259 Value |= (op & UINT64_C(1)) << 20; 10260 // op: Rd 10261 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10262 Value |= (op & UINT64_C(15)) << 12; 10263 // op: src 10264 op = getSORegRegOpValue(MI, 1, Fixups, STI); 10265 Value |= op & UINT64_C(3840); 10266 Value |= op & UINT64_C(96); 10267 Value |= op & UINT64_C(15); 10268 break; 10269 } 10270 case ARM::MLA: { 10271 // op: p 10272 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 10273 Value |= (op & UINT64_C(15)) << 28; 10274 // op: s 10275 op = getCCOutOpValue(MI, 6, Fixups, STI); 10276 Value |= (op & UINT64_C(1)) << 20; 10277 // op: Rd 10278 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10279 Value |= (op & UINT64_C(15)) << 16; 10280 // op: Rm 10281 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10282 Value |= (op & UINT64_C(15)) << 8; 10283 // op: Rn 10284 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10285 Value |= op & UINT64_C(15); 10286 // op: Ra 10287 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10288 Value |= (op & UINT64_C(15)) << 12; 10289 break; 10290 } 10291 case ARM::SMULL: 10292 case ARM::UMULL: { 10293 // op: p 10294 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 10295 Value |= (op & UINT64_C(15)) << 28; 10296 // op: s 10297 op = getCCOutOpValue(MI, 6, Fixups, STI); 10298 Value |= (op & UINT64_C(1)) << 20; 10299 // op: RdLo 10300 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10301 Value |= (op & UINT64_C(15)) << 12; 10302 // op: RdHi 10303 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10304 Value |= (op & UINT64_C(15)) << 16; 10305 // op: Rm 10306 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10307 Value |= (op & UINT64_C(15)) << 8; 10308 // op: Rn 10309 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10310 Value |= op & UINT64_C(15); 10311 break; 10312 } 10313 case ARM::VMOVRRS: { 10314 // op: p 10315 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 10316 Value |= (op & UINT64_C(15)) << 28; 10317 // op: src1 10318 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10319 Value |= (op & UINT64_C(1)) << 5; 10320 Value |= (op & UINT64_C(30)) >> 1; 10321 // op: Rt 10322 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10323 Value |= (op & UINT64_C(15)) << 12; 10324 // op: Rt2 10325 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10326 Value |= (op & UINT64_C(15)) << 16; 10327 Value = VFPThumb2PostEncoder(MI, Value, STI); 10328 break; 10329 } 10330 case ARM::MRRC: { 10331 // op: p 10332 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 10333 Value |= (op & UINT64_C(15)) << 28; 10334 // op: Rt 10335 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10336 Value |= (op & UINT64_C(15)) << 12; 10337 // op: Rt2 10338 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10339 Value |= (op & UINT64_C(15)) << 16; 10340 // op: cop 10341 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10342 Value |= (op & UINT64_C(15)) << 8; 10343 // op: opc1 10344 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10345 Value |= (op & UINT64_C(15)) << 4; 10346 // op: CRm 10347 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 10348 Value |= op & UINT64_C(15); 10349 break; 10350 } 10351 case ARM::LDRH_PRE: 10352 case ARM::LDRSB_PRE: 10353 case ARM::LDRSH_PRE: { 10354 // op: p 10355 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 10356 Value |= (op & UINT64_C(15)) << 28; 10357 // op: Rt 10358 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10359 Value |= (op & UINT64_C(15)) << 12; 10360 // op: addr 10361 op = getAddrMode3OpValue(MI, 2, Fixups, STI); 10362 Value |= (op & UINT64_C(256)) << 15; 10363 Value |= (op & UINT64_C(8192)) << 9; 10364 Value |= (op & UINT64_C(7680)) << 7; 10365 Value |= (op & UINT64_C(240)) << 4; 10366 Value |= op & UINT64_C(15); 10367 break; 10368 } 10369 case ARM::LDRB_PRE_REG: 10370 case ARM::LDR_PRE_REG: { 10371 // op: p 10372 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 10373 Value |= (op & UINT64_C(15)) << 28; 10374 // op: Rt 10375 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10376 Value |= (op & UINT64_C(15)) << 12; 10377 // op: addr 10378 op = getLdStSORegOpValue(MI, 2, Fixups, STI); 10379 Value |= (op & UINT64_C(4096)) << 11; 10380 Value |= (op & UINT64_C(122880)) << 3; 10381 Value |= op & UINT64_C(4064); 10382 Value |= op & UINT64_C(15); 10383 break; 10384 } 10385 case ARM::LDRBT_POST_REG: 10386 case ARM::LDRB_POST_REG: 10387 case ARM::LDRT_POST_REG: 10388 case ARM::LDR_POST_REG: { 10389 // op: p 10390 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 10391 Value |= (op & UINT64_C(15)) << 28; 10392 // op: Rt 10393 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10394 Value |= (op & UINT64_C(15)) << 12; 10395 // op: offset 10396 op = getAddrMode2OffsetOpValue(MI, 3, Fixups, STI); 10397 Value |= (op & UINT64_C(4096)) << 11; 10398 Value |= op & UINT64_C(4064); 10399 Value |= op & UINT64_C(15); 10400 // op: addr 10401 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10402 Value |= (op & UINT64_C(15)) << 16; 10403 break; 10404 } 10405 case ARM::LDRBT_POST_IMM: 10406 case ARM::LDRB_POST_IMM: 10407 case ARM::LDRT_POST_IMM: 10408 case ARM::LDR_POST_IMM: { 10409 // op: p 10410 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 10411 Value |= (op & UINT64_C(15)) << 28; 10412 // op: Rt 10413 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10414 Value |= (op & UINT64_C(15)) << 12; 10415 // op: offset 10416 op = getAddrMode2OffsetOpValue(MI, 3, Fixups, STI); 10417 Value |= (op & UINT64_C(4096)) << 11; 10418 Value |= op & UINT64_C(4095); 10419 // op: addr 10420 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10421 Value |= (op & UINT64_C(15)) << 16; 10422 break; 10423 } 10424 case ARM::LDRH_POST: 10425 case ARM::LDRSB_POST: 10426 case ARM::LDRSH_POST: { 10427 // op: p 10428 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 10429 Value |= (op & UINT64_C(15)) << 28; 10430 // op: Rt 10431 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10432 Value |= (op & UINT64_C(15)) << 12; 10433 // op: offset 10434 op = getAddrMode3OffsetOpValue(MI, 3, Fixups, STI); 10435 Value |= (op & UINT64_C(256)) << 15; 10436 Value |= (op & UINT64_C(512)) << 13; 10437 Value |= (op & UINT64_C(240)) << 4; 10438 Value |= op & UINT64_C(15); 10439 // op: addr 10440 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10441 Value |= (op & UINT64_C(15)) << 16; 10442 break; 10443 } 10444 case ARM::STRH_PRE: { 10445 // op: p 10446 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 10447 Value |= (op & UINT64_C(15)) << 28; 10448 // op: Rt 10449 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10450 Value |= (op & UINT64_C(15)) << 12; 10451 // op: addr 10452 op = getAddrMode3OpValue(MI, 2, Fixups, STI); 10453 Value |= (op & UINT64_C(256)) << 15; 10454 Value |= (op & UINT64_C(8192)) << 9; 10455 Value |= (op & UINT64_C(7680)) << 7; 10456 Value |= (op & UINT64_C(240)) << 4; 10457 Value |= op & UINT64_C(15); 10458 break; 10459 } 10460 case ARM::STRB_PRE_REG: 10461 case ARM::STR_PRE_REG: { 10462 // op: p 10463 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 10464 Value |= (op & UINT64_C(15)) << 28; 10465 // op: Rt 10466 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10467 Value |= (op & UINT64_C(15)) << 12; 10468 // op: addr 10469 op = getLdStSORegOpValue(MI, 2, Fixups, STI); 10470 Value |= (op & UINT64_C(4096)) << 11; 10471 Value |= (op & UINT64_C(122880)) << 3; 10472 Value |= op & UINT64_C(4064); 10473 Value |= op & UINT64_C(15); 10474 break; 10475 } 10476 case ARM::STRBT_POST_REG: 10477 case ARM::STRB_POST_REG: 10478 case ARM::STRT_POST_REG: 10479 case ARM::STR_POST_REG: { 10480 // op: p 10481 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 10482 Value |= (op & UINT64_C(15)) << 28; 10483 // op: Rt 10484 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10485 Value |= (op & UINT64_C(15)) << 12; 10486 // op: offset 10487 op = getAddrMode2OffsetOpValue(MI, 3, Fixups, STI); 10488 Value |= (op & UINT64_C(4096)) << 11; 10489 Value |= op & UINT64_C(4064); 10490 Value |= op & UINT64_C(15); 10491 // op: addr 10492 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10493 Value |= (op & UINT64_C(15)) << 16; 10494 break; 10495 } 10496 case ARM::STRBT_POST_IMM: 10497 case ARM::STRB_POST_IMM: 10498 case ARM::STRT_POST_IMM: 10499 case ARM::STR_POST_IMM: { 10500 // op: p 10501 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 10502 Value |= (op & UINT64_C(15)) << 28; 10503 // op: Rt 10504 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10505 Value |= (op & UINT64_C(15)) << 12; 10506 // op: offset 10507 op = getAddrMode2OffsetOpValue(MI, 3, Fixups, STI); 10508 Value |= (op & UINT64_C(4096)) << 11; 10509 Value |= op & UINT64_C(4095); 10510 // op: addr 10511 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10512 Value |= (op & UINT64_C(15)) << 16; 10513 break; 10514 } 10515 case ARM::STRH_POST: { 10516 // op: p 10517 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 10518 Value |= (op & UINT64_C(15)) << 28; 10519 // op: Rt 10520 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10521 Value |= (op & UINT64_C(15)) << 12; 10522 // op: offset 10523 op = getAddrMode3OffsetOpValue(MI, 3, Fixups, STI); 10524 Value |= (op & UINT64_C(256)) << 15; 10525 Value |= (op & UINT64_C(512)) << 13; 10526 Value |= (op & UINT64_C(240)) << 4; 10527 Value |= op & UINT64_C(15); 10528 // op: addr 10529 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10530 Value |= (op & UINT64_C(15)) << 16; 10531 break; 10532 } 10533 case ARM::MCRR: { 10534 // op: p 10535 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 10536 Value |= (op & UINT64_C(15)) << 28; 10537 // op: Rt 10538 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10539 Value |= (op & UINT64_C(15)) << 12; 10540 // op: Rt2 10541 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10542 Value |= (op & UINT64_C(15)) << 16; 10543 // op: cop 10544 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10545 Value |= (op & UINT64_C(15)) << 8; 10546 // op: opc1 10547 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10548 Value |= (op & UINT64_C(15)) << 4; 10549 // op: CRm 10550 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 10551 Value |= op & UINT64_C(15); 10552 break; 10553 } 10554 case ARM::LDRD: 10555 case ARM::STRD: { 10556 // op: p 10557 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 10558 Value |= (op & UINT64_C(15)) << 28; 10559 // op: addr 10560 op = getAddrMode3OpValue(MI, 2, Fixups, STI); 10561 Value |= (op & UINT64_C(256)) << 15; 10562 Value |= (op & UINT64_C(8192)) << 9; 10563 Value |= (op & UINT64_C(7680)) << 7; 10564 Value |= (op & UINT64_C(240)) << 4; 10565 Value |= op & UINT64_C(15); 10566 // op: Rt 10567 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10568 Value |= (op & UINT64_C(15)) << 12; 10569 break; 10570 } 10571 case ARM::LDRHTr: 10572 case ARM::LDRSBTr: 10573 case ARM::LDRSHTr: { 10574 // op: p 10575 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 10576 Value |= (op & UINT64_C(15)) << 28; 10577 // op: addr 10578 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10579 Value |= (op & UINT64_C(15)) << 16; 10580 // op: Rt 10581 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10582 Value |= (op & UINT64_C(15)) << 12; 10583 // op: Rm 10584 op = getPostIdxRegOpValue(MI, 3, Fixups, STI); 10585 Value |= (op & UINT64_C(16)) << 19; 10586 Value |= op & UINT64_C(15); 10587 break; 10588 } 10589 case ARM::STRHTr: { 10590 // op: p 10591 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 10592 Value |= (op & UINT64_C(15)) << 28; 10593 // op: addr 10594 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10595 Value |= (op & UINT64_C(15)) << 16; 10596 // op: Rt 10597 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10598 Value |= (op & UINT64_C(15)) << 12; 10599 // op: Rm 10600 op = getPostIdxRegOpValue(MI, 3, Fixups, STI); 10601 Value |= (op & UINT64_C(16)) << 19; 10602 Value |= op & UINT64_C(15); 10603 break; 10604 } 10605 case ARM::ADCrsr: 10606 case ARM::ADDrsr: 10607 case ARM::ANDrsr: 10608 case ARM::BICrsr: 10609 case ARM::EORrsr: 10610 case ARM::ORRrsr: 10611 case ARM::RSBrsr: 10612 case ARM::RSCrsr: 10613 case ARM::SBCrsr: 10614 case ARM::SUBrsr: { 10615 // op: p 10616 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 10617 Value |= (op & UINT64_C(15)) << 28; 10618 // op: s 10619 op = getCCOutOpValue(MI, 7, Fixups, STI); 10620 Value |= (op & UINT64_C(1)) << 20; 10621 // op: Rd 10622 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10623 Value |= (op & UINT64_C(15)) << 12; 10624 // op: Rn 10625 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10626 Value |= (op & UINT64_C(15)) << 16; 10627 // op: shift 10628 op = getSORegRegOpValue(MI, 2, Fixups, STI); 10629 Value |= op & UINT64_C(3840); 10630 Value |= op & UINT64_C(96); 10631 Value |= op & UINT64_C(15); 10632 break; 10633 } 10634 case ARM::UMAAL: { 10635 // op: p 10636 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 10637 Value |= (op & UINT64_C(15)) << 28; 10638 // op: RdLo 10639 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10640 Value |= (op & UINT64_C(15)) << 12; 10641 // op: RdHi 10642 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10643 Value |= (op & UINT64_C(15)) << 16; 10644 // op: Rm 10645 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10646 Value |= (op & UINT64_C(15)) << 8; 10647 // op: Rn 10648 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10649 Value |= op & UINT64_C(15); 10650 break; 10651 } 10652 case ARM::SMLALBB: 10653 case ARM::SMLALBT: 10654 case ARM::SMLALD: 10655 case ARM::SMLALDX: 10656 case ARM::SMLALTB: 10657 case ARM::SMLALTT: 10658 case ARM::SMLSLD: 10659 case ARM::SMLSLDX: { 10660 // op: p 10661 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 10662 Value |= (op & UINT64_C(15)) << 28; 10663 // op: Rn 10664 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10665 Value |= op & UINT64_C(15); 10666 // op: Rm 10667 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10668 Value |= (op & UINT64_C(15)) << 8; 10669 // op: RdLo 10670 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10671 Value |= (op & UINT64_C(15)) << 12; 10672 // op: RdHi 10673 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10674 Value |= (op & UINT64_C(15)) << 16; 10675 break; 10676 } 10677 case ARM::LDRD_PRE: { 10678 // op: p 10679 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 10680 Value |= (op & UINT64_C(15)) << 28; 10681 // op: Rt 10682 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10683 Value |= (op & UINT64_C(15)) << 12; 10684 // op: addr 10685 op = getAddrMode3OpValue(MI, 3, Fixups, STI); 10686 Value |= (op & UINT64_C(256)) << 15; 10687 Value |= (op & UINT64_C(8192)) << 9; 10688 Value |= (op & UINT64_C(7680)) << 7; 10689 Value |= (op & UINT64_C(240)) << 4; 10690 Value |= op & UINT64_C(15); 10691 break; 10692 } 10693 case ARM::MRC: { 10694 // op: p 10695 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 10696 Value |= (op & UINT64_C(15)) << 28; 10697 // op: Rt 10698 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10699 Value |= (op & UINT64_C(15)) << 12; 10700 // op: cop 10701 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10702 Value |= (op & UINT64_C(15)) << 8; 10703 // op: opc1 10704 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10705 Value |= (op & UINT64_C(7)) << 21; 10706 // op: opc2 10707 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 10708 Value |= (op & UINT64_C(7)) << 5; 10709 // op: CRm 10710 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 10711 Value |= op & UINT64_C(15); 10712 // op: CRn 10713 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10714 Value |= (op & UINT64_C(15)) << 16; 10715 break; 10716 } 10717 case ARM::LDRD_POST: { 10718 // op: p 10719 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 10720 Value |= (op & UINT64_C(15)) << 28; 10721 // op: Rt 10722 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10723 Value |= (op & UINT64_C(15)) << 12; 10724 // op: offset 10725 op = getAddrMode3OffsetOpValue(MI, 4, Fixups, STI); 10726 Value |= (op & UINT64_C(256)) << 15; 10727 Value |= (op & UINT64_C(512)) << 13; 10728 Value |= (op & UINT64_C(240)) << 4; 10729 Value |= op & UINT64_C(15); 10730 // op: addr 10731 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10732 Value |= (op & UINT64_C(15)) << 16; 10733 break; 10734 } 10735 case ARM::STRD_PRE: { 10736 // op: p 10737 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 10738 Value |= (op & UINT64_C(15)) << 28; 10739 // op: Rt 10740 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10741 Value |= (op & UINT64_C(15)) << 12; 10742 // op: addr 10743 op = getAddrMode3OpValue(MI, 3, Fixups, STI); 10744 Value |= (op & UINT64_C(256)) << 15; 10745 Value |= (op & UINT64_C(8192)) << 9; 10746 Value |= (op & UINT64_C(7680)) << 7; 10747 Value |= (op & UINT64_C(240)) << 4; 10748 Value |= op & UINT64_C(15); 10749 break; 10750 } 10751 case ARM::STRD_POST: { 10752 // op: p 10753 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 10754 Value |= (op & UINT64_C(15)) << 28; 10755 // op: Rt 10756 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10757 Value |= (op & UINT64_C(15)) << 12; 10758 // op: offset 10759 op = getAddrMode3OffsetOpValue(MI, 4, Fixups, STI); 10760 Value |= (op & UINT64_C(256)) << 15; 10761 Value |= (op & UINT64_C(512)) << 13; 10762 Value |= (op & UINT64_C(240)) << 4; 10763 Value |= op & UINT64_C(15); 10764 // op: addr 10765 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10766 Value |= (op & UINT64_C(15)) << 16; 10767 break; 10768 } 10769 case ARM::MCR: { 10770 // op: p 10771 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 10772 Value |= (op & UINT64_C(15)) << 28; 10773 // op: Rt 10774 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10775 Value |= (op & UINT64_C(15)) << 12; 10776 // op: cop 10777 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10778 Value |= (op & UINT64_C(15)) << 8; 10779 // op: opc1 10780 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10781 Value |= (op & UINT64_C(7)) << 21; 10782 // op: opc2 10783 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 10784 Value |= (op & UINT64_C(7)) << 5; 10785 // op: CRm 10786 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 10787 Value |= op & UINT64_C(15); 10788 // op: CRn 10789 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10790 Value |= (op & UINT64_C(15)) << 16; 10791 break; 10792 } 10793 case ARM::CDP: { 10794 // op: p 10795 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 10796 Value |= (op & UINT64_C(15)) << 28; 10797 // op: opc1 10798 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10799 Value |= (op & UINT64_C(15)) << 20; 10800 // op: CRn 10801 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10802 Value |= (op & UINT64_C(15)) << 16; 10803 // op: CRd 10804 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10805 Value |= (op & UINT64_C(15)) << 12; 10806 // op: cop 10807 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10808 Value |= (op & UINT64_C(15)) << 8; 10809 // op: opc2 10810 op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); 10811 Value |= (op & UINT64_C(7)) << 5; 10812 // op: CRm 10813 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 10814 Value |= op & UINT64_C(15); 10815 break; 10816 } 10817 case ARM::SMLAL: 10818 case ARM::UMLAL: { 10819 // op: p 10820 op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); 10821 Value |= (op & UINT64_C(15)) << 28; 10822 // op: s 10823 op = getCCOutOpValue(MI, 8, Fixups, STI); 10824 Value |= (op & UINT64_C(1)) << 20; 10825 // op: RdLo 10826 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10827 Value |= (op & UINT64_C(15)) << 12; 10828 // op: RdHi 10829 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10830 Value |= (op & UINT64_C(15)) << 16; 10831 // op: Rm 10832 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 10833 Value |= (op & UINT64_C(15)) << 8; 10834 // op: Rn 10835 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10836 Value |= op & UINT64_C(15); 10837 break; 10838 } 10839 case ARM::tPUSH: { 10840 // op: regs 10841 op = getRegisterListOpValue(MI, 2, Fixups, STI); 10842 Value |= (op & UINT64_C(16384)) >> 6; 10843 Value |= op & UINT64_C(255); 10844 break; 10845 } 10846 case ARM::tPOP: { 10847 // op: regs 10848 op = getRegisterListOpValue(MI, 2, Fixups, STI); 10849 Value |= (op & UINT64_C(32768)) >> 7; 10850 Value |= op & UINT64_C(255); 10851 break; 10852 } 10853 case ARM::t2MOVr: 10854 case ARM::t2MVNr: 10855 case ARM::t2RRX: { 10856 // op: s 10857 op = getCCOutOpValue(MI, 4, Fixups, STI); 10858 Value |= (op & UINT64_C(1)) << 20; 10859 // op: Rd 10860 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10861 Value |= (op & UINT64_C(15)) << 8; 10862 // op: Rm 10863 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10864 Value |= op & UINT64_C(15); 10865 break; 10866 } 10867 case ARM::t2MOVi: 10868 case ARM::t2MVNi: { 10869 // op: s 10870 op = getCCOutOpValue(MI, 4, Fixups, STI); 10871 Value |= (op & UINT64_C(1)) << 20; 10872 // op: Rd 10873 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10874 Value |= (op & UINT64_C(15)) << 8; 10875 // op: imm 10876 op = getT2SOImmOpValue(MI, 1, Fixups, STI); 10877 Value |= (op & UINT64_C(2048)) << 15; 10878 Value |= (op & UINT64_C(1792)) << 4; 10879 Value |= op & UINT64_C(255); 10880 break; 10881 } 10882 case ARM::t2ASRri: 10883 case ARM::t2LSLri: 10884 case ARM::t2LSRri: 10885 case ARM::t2RORri: { 10886 // op: s 10887 op = getCCOutOpValue(MI, 5, Fixups, STI); 10888 Value |= (op & UINT64_C(1)) << 20; 10889 // op: Rd 10890 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10891 Value |= (op & UINT64_C(15)) << 8; 10892 // op: Rm 10893 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10894 Value |= op & UINT64_C(15); 10895 // op: imm 10896 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10897 Value |= (op & UINT64_C(28)) << 10; 10898 Value |= (op & UINT64_C(3)) << 6; 10899 break; 10900 } 10901 case ARM::t2ADCrr: 10902 case ARM::t2ADDrr: 10903 case ARM::t2ANDrr: 10904 case ARM::t2ASRrr: 10905 case ARM::t2BICrr: 10906 case ARM::t2EORrr: 10907 case ARM::t2LSLrr: 10908 case ARM::t2LSRrr: 10909 case ARM::t2ORNrr: 10910 case ARM::t2ORRrr: 10911 case ARM::t2RORrr: 10912 case ARM::t2RSBrr: 10913 case ARM::t2SBCrr: 10914 case ARM::t2SUBrr: { 10915 // op: s 10916 op = getCCOutOpValue(MI, 5, Fixups, STI); 10917 Value |= (op & UINT64_C(1)) << 20; 10918 // op: Rd 10919 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10920 Value |= (op & UINT64_C(15)) << 8; 10921 // op: Rn 10922 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10923 Value |= (op & UINT64_C(15)) << 16; 10924 // op: Rm 10925 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 10926 Value |= op & UINT64_C(15); 10927 break; 10928 } 10929 case ARM::t2ADCri: 10930 case ARM::t2ADDri: 10931 case ARM::t2ANDri: 10932 case ARM::t2BICri: 10933 case ARM::t2EORri: 10934 case ARM::t2ORNri: 10935 case ARM::t2ORRri: 10936 case ARM::t2RSBri: 10937 case ARM::t2SBCri: 10938 case ARM::t2SUBri: { 10939 // op: s 10940 op = getCCOutOpValue(MI, 5, Fixups, STI); 10941 Value |= (op & UINT64_C(1)) << 20; 10942 // op: Rd 10943 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10944 Value |= (op & UINT64_C(15)) << 8; 10945 // op: Rn 10946 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10947 Value |= (op & UINT64_C(15)) << 16; 10948 // op: imm 10949 op = getT2SOImmOpValue(MI, 2, Fixups, STI); 10950 Value |= (op & UINT64_C(2048)) << 15; 10951 Value |= (op & UINT64_C(1792)) << 4; 10952 Value |= op & UINT64_C(255); 10953 break; 10954 } 10955 case ARM::t2MVNs: { 10956 // op: s 10957 op = getCCOutOpValue(MI, 5, Fixups, STI); 10958 Value |= (op & UINT64_C(1)) << 20; 10959 // op: Rd 10960 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10961 Value |= (op & UINT64_C(15)) << 8; 10962 // op: ShiftedRm 10963 op = getT2SORegOpValue(MI, 1, Fixups, STI); 10964 Value |= (op & UINT64_C(3584)) << 3; 10965 Value |= (op & UINT64_C(480)) >> 1; 10966 Value |= op & UINT64_C(15); 10967 break; 10968 } 10969 case ARM::t2ADCrs: 10970 case ARM::t2ADDrs: 10971 case ARM::t2ANDrs: 10972 case ARM::t2BICrs: 10973 case ARM::t2EORrs: 10974 case ARM::t2ORNrs: 10975 case ARM::t2ORRrs: 10976 case ARM::t2RSBrs: 10977 case ARM::t2SBCrs: 10978 case ARM::t2SUBrs: { 10979 // op: s 10980 op = getCCOutOpValue(MI, 6, Fixups, STI); 10981 Value |= (op & UINT64_C(1)) << 20; 10982 // op: Rd 10983 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 10984 Value |= (op & UINT64_C(15)) << 8; 10985 // op: Rn 10986 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 10987 Value |= (op & UINT64_C(15)) << 16; 10988 // op: ShiftedRm 10989 op = getT2SORegOpValue(MI, 2, Fixups, STI); 10990 Value |= (op & UINT64_C(3584)) << 3; 10991 Value |= (op & UINT64_C(480)) >> 1; 10992 Value |= op & UINT64_C(15); 10993 break; 10994 } 10995 case ARM::PLDWrs: 10996 case ARM::PLDrs: 10997 case ARM::PLIrs: { 10998 // op: shift 10999 op = getLdStSORegOpValue(MI, 0, Fixups, STI); 11000 Value |= (op & UINT64_C(4096)) << 11; 11001 Value |= (op & UINT64_C(122880)) << 3; 11002 Value |= op & UINT64_C(4064); 11003 Value |= op & UINT64_C(15); 11004 break; 11005 } 11006 case ARM::BLXi: { 11007 // op: target 11008 op = getARMBLXTargetOpValue(MI, 0, Fixups, STI); 11009 Value |= (op & UINT64_C(1)) << 24; 11010 Value |= (op & UINT64_C(33554430)) >> 1; 11011 break; 11012 } 11013 case ARM::tB: { 11014 // op: target 11015 op = getThumbBRTargetOpValue(MI, 0, Fixups, STI); 11016 Value |= op & UINT64_C(2047); 11017 break; 11018 } 11019 case ARM::t2B: { 11020 // op: target 11021 op = getThumbBranchTargetOpValue(MI, 0, Fixups, STI); 11022 Value |= (op & UINT64_C(8388608)) << 3; 11023 Value |= (op & UINT64_C(2095104)) << 5; 11024 Value |= (op & UINT64_C(4194304)) >> 9; 11025 Value |= (op & UINT64_C(2097152)) >> 10; 11026 Value |= op & UINT64_C(2047); 11027 break; 11028 } 11029 case ARM::tCBNZ: 11030 case ARM::tCBZ: { 11031 // op: target 11032 op = getThumbCBTargetOpValue(MI, 1, Fixups, STI); 11033 Value |= (op & UINT64_C(32)) << 4; 11034 Value |= (op & UINT64_C(31)) << 3; 11035 // op: Rn 11036 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 11037 Value |= op & UINT64_C(7); 11038 break; 11039 } 11040 case ARM::BKPT: 11041 case ARM::HLT: { 11042 // op: val 11043 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 11044 Value |= (op & UINT64_C(65520)) << 4; 11045 Value |= op & UINT64_C(15); 11046 break; 11047 } 11048 case ARM::tBKPT: { 11049 // op: val 11050 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 11051 Value |= op & UINT64_C(255); 11052 break; 11053 } 11054 case ARM::tHLT: { 11055 // op: val 11056 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 11057 Value |= op & UINT64_C(63); 11058 break; 11059 } 11060 default: 11061 std::string msg; 11062 raw_string_ostream Msg(msg); 11063 Msg << "Not supported instr: " << MI; 11064 report_fatal_error(Msg.str()); 11065 } 11066 return Value; 11067} 11068 11069#ifdef ENABLE_INSTR_PREDICATE_VERIFIER 11070#undef ENABLE_INSTR_PREDICATE_VERIFIER 11071#include <sstream> 11072 11073// Flags for subtarget features that participate in instruction matching. 11074enum SubtargetFeatureFlag : uint64_t { 11075 Feature_HasV4T = (1ULL << 20), 11076 Feature_HasV5T = (1ULL << 21), 11077 Feature_HasV5TE = (1ULL << 22), 11078 Feature_HasV6 = (1ULL << 23), 11079 Feature_HasV6M = (1ULL << 25), 11080 Feature_HasV8MBaseline = (1ULL << 30), 11081 Feature_HasV8MMainline = (1ULL << 31), 11082 Feature_HasV6T2 = (1ULL << 26), 11083 Feature_HasV6K = (1ULL << 24), 11084 Feature_HasV7 = (1ULL << 27), 11085 Feature_HasV8 = (1ULL << 29), 11086 Feature_PreV8 = (1ULL << 45), 11087 Feature_HasV8_1a = (1ULL << 32), 11088 Feature_HasV8_2a = (1ULL << 33), 11089 Feature_HasV8_3a = (1ULL << 34), 11090 Feature_HasV8_4a = (1ULL << 35), 11091 Feature_HasVFP2 = (1ULL << 36), 11092 Feature_HasVFP3 = (1ULL << 37), 11093 Feature_HasVFP4 = (1ULL << 38), 11094 Feature_HasDPVFP = (1ULL << 7), 11095 Feature_HasFPARMv8 = (1ULL << 13), 11096 Feature_HasNEON = (1ULL << 16), 11097 Feature_HasSHA2 = (1ULL << 18), 11098 Feature_HasAES = (1ULL << 1), 11099 Feature_HasCrypto = (1ULL << 4), 11100 Feature_HasDotProd = (1ULL << 11), 11101 Feature_HasCRC = (1ULL << 3), 11102 Feature_HasRAS = (1ULL << 17), 11103 Feature_HasFP16 = (1ULL << 12), 11104 Feature_HasFullFP16 = (1ULL << 14), 11105 Feature_HasDivideInThumb = (1ULL << 10), 11106 Feature_HasDivideInARM = (1ULL << 9), 11107 Feature_HasDSP = (1ULL << 8), 11108 Feature_HasDB = (1ULL << 5), 11109 Feature_HasDFB = (1ULL << 6), 11110 Feature_HasV7Clrex = (1ULL << 28), 11111 Feature_HasAcquireRelease = (1ULL << 2), 11112 Feature_HasMP = (1ULL << 15), 11113 Feature_HasVirtualization = (1ULL << 39), 11114 Feature_HasTrustZone = (1ULL << 19), 11115 Feature_Has8MSecExt = (1ULL << 0), 11116 Feature_IsThumb = (1ULL << 43), 11117 Feature_IsThumb2 = (1ULL << 44), 11118 Feature_IsMClass = (1ULL << 41), 11119 Feature_IsNotMClass = (1ULL << 42), 11120 Feature_IsARM = (1ULL << 40), 11121 Feature_UseNaClTrap = (1ULL << 46), 11122 Feature_UseNegativeImmediates = (1ULL << 47), 11123 Feature_None = 0 11124}; 11125 11126#ifndef NDEBUG 11127static const char *SubtargetFeatureNames[] = { 11128 "Feature_Has8MSecExt", 11129 "Feature_HasAES", 11130 "Feature_HasAcquireRelease", 11131 "Feature_HasCRC", 11132 "Feature_HasCrypto", 11133 "Feature_HasDB", 11134 "Feature_HasDFB", 11135 "Feature_HasDPVFP", 11136 "Feature_HasDSP", 11137 "Feature_HasDivideInARM", 11138 "Feature_HasDivideInThumb", 11139 "Feature_HasDotProd", 11140 "Feature_HasFP16", 11141 "Feature_HasFPARMv8", 11142 "Feature_HasFullFP16", 11143 "Feature_HasMP", 11144 "Feature_HasNEON", 11145 "Feature_HasRAS", 11146 "Feature_HasSHA2", 11147 "Feature_HasTrustZone", 11148 "Feature_HasV4T", 11149 "Feature_HasV5T", 11150 "Feature_HasV5TE", 11151 "Feature_HasV6", 11152 "Feature_HasV6K", 11153 "Feature_HasV6M", 11154 "Feature_HasV6T2", 11155 "Feature_HasV7", 11156 "Feature_HasV7Clrex", 11157 "Feature_HasV8", 11158 "Feature_HasV8MBaseline", 11159 "Feature_HasV8MMainline", 11160 "Feature_HasV8_1a", 11161 "Feature_HasV8_2a", 11162 "Feature_HasV8_3a", 11163 "Feature_HasV8_4a", 11164 "Feature_HasVFP2", 11165 "Feature_HasVFP3", 11166 "Feature_HasVFP4", 11167 "Feature_HasVirtualization", 11168 "Feature_IsARM", 11169 "Feature_IsMClass", 11170 "Feature_IsNotMClass", 11171 "Feature_IsThumb", 11172 "Feature_IsThumb2", 11173 "Feature_PreV8", 11174 "Feature_UseNaClTrap", 11175 "Feature_UseNegativeImmediates", 11176 nullptr 11177}; 11178 11179#endif // NDEBUG 11180uint64_t ARMMCCodeEmitter:: 11181computeAvailableFeatures(const FeatureBitset& FB) const { 11182 uint64_t Features = 0; 11183 if ((FB[ARM::HasV4TOps])) 11184 Features |= Feature_HasV4T; 11185 if ((FB[ARM::HasV5TOps])) 11186 Features |= Feature_HasV5T; 11187 if ((FB[ARM::HasV5TEOps])) 11188 Features |= Feature_HasV5TE; 11189 if ((FB[ARM::HasV6Ops])) 11190 Features |= Feature_HasV6; 11191 if ((FB[ARM::HasV6MOps])) 11192 Features |= Feature_HasV6M; 11193 if ((FB[ARM::HasV8MBaselineOps])) 11194 Features |= Feature_HasV8MBaseline; 11195 if ((FB[ARM::HasV8MMainlineOps])) 11196 Features |= Feature_HasV8MMainline; 11197 if ((FB[ARM::HasV6T2Ops])) 11198 Features |= Feature_HasV6T2; 11199 if ((FB[ARM::HasV6KOps])) 11200 Features |= Feature_HasV6K; 11201 if ((FB[ARM::HasV7Ops])) 11202 Features |= Feature_HasV7; 11203 if ((FB[ARM::HasV8Ops])) 11204 Features |= Feature_HasV8; 11205 if ((!FB[ARM::HasV8Ops])) 11206 Features |= Feature_PreV8; 11207 if ((FB[ARM::HasV8_1aOps])) 11208 Features |= Feature_HasV8_1a; 11209 if ((FB[ARM::HasV8_2aOps])) 11210 Features |= Feature_HasV8_2a; 11211 if ((FB[ARM::HasV8_3aOps])) 11212 Features |= Feature_HasV8_3a; 11213 if ((FB[ARM::HasV8_4aOps])) 11214 Features |= Feature_HasV8_4a; 11215 if ((FB[ARM::FeatureVFP2])) 11216 Features |= Feature_HasVFP2; 11217 if ((FB[ARM::FeatureVFP3])) 11218 Features |= Feature_HasVFP3; 11219 if ((FB[ARM::FeatureVFP4])) 11220 Features |= Feature_HasVFP4; 11221 if ((!FB[ARM::FeatureVFPOnlySP])) 11222 Features |= Feature_HasDPVFP; 11223 if ((FB[ARM::FeatureFPARMv8])) 11224 Features |= Feature_HasFPARMv8; 11225 if ((FB[ARM::FeatureNEON])) 11226 Features |= Feature_HasNEON; 11227 if ((FB[ARM::FeatureSHA2])) 11228 Features |= Feature_HasSHA2; 11229 if ((FB[ARM::FeatureAES])) 11230 Features |= Feature_HasAES; 11231 if ((FB[ARM::FeatureCrypto])) 11232 Features |= Feature_HasCrypto; 11233 if ((FB[ARM::FeatureDotProd])) 11234 Features |= Feature_HasDotProd; 11235 if ((FB[ARM::FeatureCRC])) 11236 Features |= Feature_HasCRC; 11237 if ((FB[ARM::FeatureRAS])) 11238 Features |= Feature_HasRAS; 11239 if ((FB[ARM::FeatureFP16])) 11240 Features |= Feature_HasFP16; 11241 if ((FB[ARM::FeatureFullFP16])) 11242 Features |= Feature_HasFullFP16; 11243 if ((FB[ARM::FeatureHWDivThumb])) 11244 Features |= Feature_HasDivideInThumb; 11245 if ((FB[ARM::FeatureHWDivARM])) 11246 Features |= Feature_HasDivideInARM; 11247 if ((FB[ARM::FeatureDSP])) 11248 Features |= Feature_HasDSP; 11249 if ((FB[ARM::FeatureDB])) 11250 Features |= Feature_HasDB; 11251 if ((FB[ARM::FeatureDFB])) 11252 Features |= Feature_HasDFB; 11253 if ((FB[ARM::FeatureV7Clrex])) 11254 Features |= Feature_HasV7Clrex; 11255 if ((FB[ARM::FeatureAcquireRelease])) 11256 Features |= Feature_HasAcquireRelease; 11257 if ((FB[ARM::FeatureMP])) 11258 Features |= Feature_HasMP; 11259 if ((FB[ARM::FeatureVirtualization])) 11260 Features |= Feature_HasVirtualization; 11261 if ((FB[ARM::FeatureTrustZone])) 11262 Features |= Feature_HasTrustZone; 11263 if ((FB[ARM::Feature8MSecExt])) 11264 Features |= Feature_Has8MSecExt; 11265 if ((FB[ARM::ModeThumb])) 11266 Features |= Feature_IsThumb; 11267 if ((FB[ARM::ModeThumb]) && (FB[ARM::FeatureThumb2])) 11268 Features |= Feature_IsThumb2; 11269 if ((FB[ARM::FeatureMClass])) 11270 Features |= Feature_IsMClass; 11271 if ((!FB[ARM::FeatureMClass])) 11272 Features |= Feature_IsNotMClass; 11273 if ((!FB[ARM::ModeThumb])) 11274 Features |= Feature_IsARM; 11275 if ((FB[ARM::FeatureNaClTrap])) 11276 Features |= Feature_UseNaClTrap; 11277 if ((!FB[ARM::FeatureNoNegativeImmediates])) 11278 Features |= Feature_UseNegativeImmediates; 11279 return Features; 11280} 11281 11282void ARMMCCodeEmitter::verifyInstructionPredicates( 11283 const MCInst &Inst, uint64_t AvailableFeatures) const { 11284#ifndef NDEBUG 11285 static uint64_t RequiredFeatures[] = { 11286 0, // PHI = 0 11287 0, // INLINEASM = 1 11288 0, // CFI_INSTRUCTION = 2 11289 0, // EH_LABEL = 3 11290 0, // GC_LABEL = 4 11291 0, // ANNOTATION_LABEL = 5 11292 0, // KILL = 6 11293 0, // EXTRACT_SUBREG = 7 11294 0, // INSERT_SUBREG = 8 11295 0, // IMPLICIT_DEF = 9 11296 0, // SUBREG_TO_REG = 10 11297 0, // COPY_TO_REGCLASS = 11 11298 0, // DBG_VALUE = 12 11299 0, // DBG_LABEL = 13 11300 0, // REG_SEQUENCE = 14 11301 0, // COPY = 15 11302 0, // BUNDLE = 16 11303 0, // LIFETIME_START = 17 11304 0, // LIFETIME_END = 18 11305 0, // STACKMAP = 19 11306 0, // FENTRY_CALL = 20 11307 0, // PATCHPOINT = 21 11308 0, // LOAD_STACK_GUARD = 22 11309 0, // STATEPOINT = 23 11310 0, // LOCAL_ESCAPE = 24 11311 0, // FAULTING_OP = 25 11312 0, // PATCHABLE_OP = 26 11313 0, // PATCHABLE_FUNCTION_ENTER = 27 11314 0, // PATCHABLE_RET = 28 11315 0, // PATCHABLE_FUNCTION_EXIT = 29 11316 0, // PATCHABLE_TAIL_CALL = 30 11317 0, // PATCHABLE_EVENT_CALL = 31 11318 0, // PATCHABLE_TYPED_EVENT_CALL = 32 11319 0, // ICALL_BRANCH_FUNNEL = 33 11320 0, // G_ADD = 34 11321 0, // G_SUB = 35 11322 0, // G_MUL = 36 11323 0, // G_SDIV = 37 11324 0, // G_UDIV = 38 11325 0, // G_SREM = 39 11326 0, // G_UREM = 40 11327 0, // G_AND = 41 11328 0, // G_OR = 42 11329 0, // G_XOR = 43 11330 0, // G_IMPLICIT_DEF = 44 11331 0, // G_PHI = 45 11332 0, // G_FRAME_INDEX = 46 11333 0, // G_GLOBAL_VALUE = 47 11334 0, // G_EXTRACT = 48 11335 0, // G_UNMERGE_VALUES = 49 11336 0, // G_INSERT = 50 11337 0, // G_MERGE_VALUES = 51 11338 0, // G_PTRTOINT = 52 11339 0, // G_INTTOPTR = 53 11340 0, // G_BITCAST = 54 11341 0, // G_LOAD = 55 11342 0, // G_SEXTLOAD = 56 11343 0, // G_ZEXTLOAD = 57 11344 0, // G_STORE = 58 11345 0, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 59 11346 0, // G_ATOMIC_CMPXCHG = 60 11347 0, // G_ATOMICRMW_XCHG = 61 11348 0, // G_ATOMICRMW_ADD = 62 11349 0, // G_ATOMICRMW_SUB = 63 11350 0, // G_ATOMICRMW_AND = 64 11351 0, // G_ATOMICRMW_NAND = 65 11352 0, // G_ATOMICRMW_OR = 66 11353 0, // G_ATOMICRMW_XOR = 67 11354 0, // G_ATOMICRMW_MAX = 68 11355 0, // G_ATOMICRMW_MIN = 69 11356 0, // G_ATOMICRMW_UMAX = 70 11357 0, // G_ATOMICRMW_UMIN = 71 11358 0, // G_BRCOND = 72 11359 0, // G_BRINDIRECT = 73 11360 0, // G_INTRINSIC = 74 11361 0, // G_INTRINSIC_W_SIDE_EFFECTS = 75 11362 0, // G_ANYEXT = 76 11363 0, // G_TRUNC = 77 11364 0, // G_CONSTANT = 78 11365 0, // G_FCONSTANT = 79 11366 0, // G_VASTART = 80 11367 0, // G_VAARG = 81 11368 0, // G_SEXT = 82 11369 0, // G_ZEXT = 83 11370 0, // G_SHL = 84 11371 0, // G_LSHR = 85 11372 0, // G_ASHR = 86 11373 0, // G_ICMP = 87 11374 0, // G_FCMP = 88 11375 0, // G_SELECT = 89 11376 0, // G_UADDE = 90 11377 0, // G_USUBE = 91 11378 0, // G_SADDO = 92 11379 0, // G_SSUBO = 93 11380 0, // G_UMULO = 94 11381 0, // G_SMULO = 95 11382 0, // G_UMULH = 96 11383 0, // G_SMULH = 97 11384 0, // G_FADD = 98 11385 0, // G_FSUB = 99 11386 0, // G_FMUL = 100 11387 0, // G_FMA = 101 11388 0, // G_FDIV = 102 11389 0, // G_FREM = 103 11390 0, // G_FPOW = 104 11391 0, // G_FEXP = 105 11392 0, // G_FEXP2 = 106 11393 0, // G_FLOG = 107 11394 0, // G_FLOG2 = 108 11395 0, // G_FNEG = 109 11396 0, // G_FPEXT = 110 11397 0, // G_FPTRUNC = 111 11398 0, // G_FPTOSI = 112 11399 0, // G_FPTOUI = 113 11400 0, // G_SITOFP = 114 11401 0, // G_UITOFP = 115 11402 0, // G_FABS = 116 11403 0, // G_GEP = 117 11404 0, // G_PTR_MASK = 118 11405 0, // G_BR = 119 11406 0, // G_INSERT_VECTOR_ELT = 120 11407 0, // G_EXTRACT_VECTOR_ELT = 121 11408 0, // G_SHUFFLE_VECTOR = 122 11409 0, // G_BSWAP = 123 11410 0, // G_ADDRSPACE_CAST = 124 11411 0, // G_BLOCK_ADDR = 125 11412 Feature_IsARM | 0, // ABS = 126 11413 Feature_IsARM | 0, // ADDSri = 127 11414 Feature_IsARM | 0, // ADDSrr = 128 11415 Feature_IsARM | 0, // ADDSrsi = 129 11416 Feature_IsARM | 0, // ADDSrsr = 130 11417 0, // ADJCALLSTACKDOWN = 131 11418 0, // ADJCALLSTACKUP = 132 11419 Feature_IsARM | 0, // ASRi = 133 11420 Feature_IsARM | 0, // ASRr = 134 11421 Feature_IsARM | 0, // B = 135 11422 0, // BCCZi64 = 136 11423 0, // BCCi64 = 137 11424 Feature_IsARM | 0, // BMOVPCB_CALL = 138 11425 Feature_IsARM | 0, // BMOVPCRX_CALL = 139 11426 Feature_IsARM | 0, // BR_JTadd = 140 11427 Feature_IsARM | 0, // BR_JTm_i12 = 141 11428 Feature_IsARM | 0, // BR_JTm_rs = 142 11429 Feature_IsARM | 0, // BR_JTr = 143 11430 Feature_IsARM | Feature_HasV4T | 0, // BX_CALL = 144 11431 0, // CMP_SWAP_16 = 145 11432 0, // CMP_SWAP_32 = 146 11433 0, // CMP_SWAP_64 = 147 11434 0, // CMP_SWAP_8 = 148 11435 0, // CONSTPOOL_ENTRY = 149 11436 0, // COPY_STRUCT_BYVAL_I32 = 150 11437 0, // CompilerBarrier = 151 11438 Feature_IsARM | 0, // ITasm = 152 11439 0, // Int_eh_sjlj_dispatchsetup = 153 11440 Feature_IsARM | 0, // Int_eh_sjlj_longjmp = 154 11441 Feature_IsARM | Feature_HasVFP2 | 0, // Int_eh_sjlj_setjmp = 155 11442 Feature_IsARM | 0, // Int_eh_sjlj_setjmp_nofp = 156 11443 0, // Int_eh_sjlj_setup_dispatch = 157 11444 0, // JUMPTABLE_ADDRS = 158 11445 0, // JUMPTABLE_INSTS = 159 11446 0, // JUMPTABLE_TBB = 160 11447 0, // JUMPTABLE_TBH = 161 11448 Feature_IsARM | 0, // LDMIA_RET = 162 11449 Feature_IsARM | 0, // LDRBT_POST = 163 11450 Feature_IsARM | 0, // LDRConstPool = 164 11451 Feature_IsARM | 0, // LDRLIT_ga_abs = 165 11452 Feature_IsARM | 0, // LDRLIT_ga_pcrel = 166 11453 Feature_IsARM | 0, // LDRLIT_ga_pcrel_ldr = 167 11454 Feature_IsARM | 0, // LDRT_POST = 168 11455 Feature_IsARM | 0, // LEApcrel = 169 11456 Feature_IsARM | 0, // LEApcrelJT = 170 11457 Feature_IsARM | 0, // LSLi = 171 11458 Feature_IsARM | 0, // LSLr = 172 11459 Feature_IsARM | 0, // LSRi = 173 11460 Feature_IsARM | 0, // LSRr = 174 11461 0, // MEMCPY = 175 11462 Feature_IsARM | 0, // MLAv5 = 176 11463 Feature_IsARM | 0, // MOVCCi = 177 11464 Feature_IsARM | Feature_HasV6T2 | 0, // MOVCCi16 = 178 11465 Feature_IsARM | Feature_HasV6T2 | 0, // MOVCCi32imm = 179 11466 Feature_IsARM | 0, // MOVCCr = 180 11467 Feature_IsARM | 0, // MOVCCsi = 181 11468 Feature_IsARM | 0, // MOVCCsr = 182 11469 Feature_IsARM | 0, // MOVPCRX = 183 11470 0, // MOVTi16_ga_pcrel = 184 11471 Feature_IsARM | 0, // MOV_ga_pcrel = 185 11472 Feature_IsARM | 0, // MOV_ga_pcrel_ldr = 186 11473 0, // MOVi16_ga_pcrel = 187 11474 Feature_IsARM | 0, // MOVi32imm = 188 11475 Feature_IsARM | 0, // MOVsra_flag = 189 11476 Feature_IsARM | 0, // MOVsrl_flag = 190 11477 Feature_IsARM | 0, // MULv5 = 191 11478 Feature_IsARM | 0, // MVNCCi = 192 11479 Feature_IsARM | 0, // PICADD = 193 11480 Feature_IsARM | 0, // PICLDR = 194 11481 Feature_IsARM | 0, // PICLDRB = 195 11482 Feature_IsARM | 0, // PICLDRH = 196 11483 Feature_IsARM | 0, // PICLDRSB = 197 11484 Feature_IsARM | 0, // PICLDRSH = 198 11485 Feature_IsARM | 0, // PICSTR = 199 11486 Feature_IsARM | 0, // PICSTRB = 200 11487 Feature_IsARM | 0, // PICSTRH = 201 11488 Feature_IsARM | 0, // RORi = 202 11489 Feature_IsARM | 0, // RORr = 203 11490 Feature_IsARM | 0, // RRX = 204 11491 Feature_IsARM | 0, // RRXi = 205 11492 Feature_IsARM | 0, // RSBSri = 206 11493 Feature_IsARM | 0, // RSBSrsi = 207 11494 Feature_IsARM | 0, // RSBSrsr = 208 11495 Feature_IsARM | 0, // SMLALv5 = 209 11496 Feature_IsARM | 0, // SMULLv5 = 210 11497 0, // SPACE = 211 11498 Feature_IsARM | 0, // STRBT_POST = 212 11499 Feature_IsARM | 0, // STRBi_preidx = 213 11500 Feature_IsARM | 0, // STRBr_preidx = 214 11501 Feature_IsARM | 0, // STRH_preidx = 215 11502 Feature_IsARM | 0, // STRT_POST = 216 11503 Feature_IsARM | 0, // STRi_preidx = 217 11504 Feature_IsARM | 0, // STRr_preidx = 218 11505 Feature_IsARM | 0, // SUBS_PC_LR = 219 11506 Feature_IsARM | 0, // SUBSri = 220 11507 Feature_IsARM | 0, // SUBSrr = 221 11508 Feature_IsARM | 0, // SUBSrsi = 222 11509 Feature_IsARM | 0, // SUBSrsr = 223 11510 Feature_IsARM | 0, // TAILJMPd = 224 11511 Feature_IsARM | Feature_HasV4T | 0, // TAILJMPr = 225 11512 Feature_IsARM | 0, // TAILJMPr4 = 226 11513 0, // TCRETURNdi = 227 11514 0, // TCRETURNri = 228 11515 Feature_IsARM | 0, // TPsoft = 229 11516 Feature_IsARM | 0, // UMLALv5 = 230 11517 Feature_IsARM | 0, // UMULLv5 = 231 11518 Feature_HasNEON | 0, // VLD1LNdAsm_16 = 232 11519 Feature_HasNEON | 0, // VLD1LNdAsm_32 = 233 11520 Feature_HasNEON | 0, // VLD1LNdAsm_8 = 234 11521 Feature_HasNEON | 0, // VLD1LNdWB_fixed_Asm_16 = 235 11522 Feature_HasNEON | 0, // VLD1LNdWB_fixed_Asm_32 = 236 11523 Feature_HasNEON | 0, // VLD1LNdWB_fixed_Asm_8 = 237 11524 Feature_HasNEON | 0, // VLD1LNdWB_register_Asm_16 = 238 11525 Feature_HasNEON | 0, // VLD1LNdWB_register_Asm_32 = 239 11526 Feature_HasNEON | 0, // VLD1LNdWB_register_Asm_8 = 240 11527 Feature_HasNEON | 0, // VLD2LNdAsm_16 = 241 11528 Feature_HasNEON | 0, // VLD2LNdAsm_32 = 242 11529 Feature_HasNEON | 0, // VLD2LNdAsm_8 = 243 11530 Feature_HasNEON | 0, // VLD2LNdWB_fixed_Asm_16 = 244 11531 Feature_HasNEON | 0, // VLD2LNdWB_fixed_Asm_32 = 245 11532 Feature_HasNEON | 0, // VLD2LNdWB_fixed_Asm_8 = 246 11533 Feature_HasNEON | 0, // VLD2LNdWB_register_Asm_16 = 247 11534 Feature_HasNEON | 0, // VLD2LNdWB_register_Asm_32 = 248 11535 Feature_HasNEON | 0, // VLD2LNdWB_register_Asm_8 = 249 11536 Feature_HasNEON | 0, // VLD2LNqAsm_16 = 250 11537 Feature_HasNEON | 0, // VLD2LNqAsm_32 = 251 11538 Feature_HasNEON | 0, // VLD2LNqWB_fixed_Asm_16 = 252 11539 Feature_HasNEON | 0, // VLD2LNqWB_fixed_Asm_32 = 253 11540 Feature_HasNEON | 0, // VLD2LNqWB_register_Asm_16 = 254 11541 Feature_HasNEON | 0, // VLD2LNqWB_register_Asm_32 = 255 11542 Feature_HasNEON | 0, // VLD3DUPdAsm_16 = 256 11543 Feature_HasNEON | 0, // VLD3DUPdAsm_32 = 257 11544 Feature_HasNEON | 0, // VLD3DUPdAsm_8 = 258 11545 Feature_HasNEON | 0, // VLD3DUPdWB_fixed_Asm_16 = 259 11546 Feature_HasNEON | 0, // VLD3DUPdWB_fixed_Asm_32 = 260 11547 Feature_HasNEON | 0, // VLD3DUPdWB_fixed_Asm_8 = 261 11548 Feature_HasNEON | 0, // VLD3DUPdWB_register_Asm_16 = 262 11549 Feature_HasNEON | 0, // VLD3DUPdWB_register_Asm_32 = 263 11550 Feature_HasNEON | 0, // VLD3DUPdWB_register_Asm_8 = 264 11551 Feature_HasNEON | 0, // VLD3DUPqAsm_16 = 265 11552 Feature_HasNEON | 0, // VLD3DUPqAsm_32 = 266 11553 Feature_HasNEON | 0, // VLD3DUPqAsm_8 = 267 11554 Feature_HasNEON | 0, // VLD3DUPqWB_fixed_Asm_16 = 268 11555 Feature_HasNEON | 0, // VLD3DUPqWB_fixed_Asm_32 = 269 11556 Feature_HasNEON | 0, // VLD3DUPqWB_fixed_Asm_8 = 270 11557 Feature_HasNEON | 0, // VLD3DUPqWB_register_Asm_16 = 271 11558 Feature_HasNEON | 0, // VLD3DUPqWB_register_Asm_32 = 272 11559 Feature_HasNEON | 0, // VLD3DUPqWB_register_Asm_8 = 273 11560 Feature_HasNEON | 0, // VLD3LNdAsm_16 = 274 11561 Feature_HasNEON | 0, // VLD3LNdAsm_32 = 275 11562 Feature_HasNEON | 0, // VLD3LNdAsm_8 = 276 11563 Feature_HasNEON | 0, // VLD3LNdWB_fixed_Asm_16 = 277 11564 Feature_HasNEON | 0, // VLD3LNdWB_fixed_Asm_32 = 278 11565 Feature_HasNEON | 0, // VLD3LNdWB_fixed_Asm_8 = 279 11566 Feature_HasNEON | 0, // VLD3LNdWB_register_Asm_16 = 280 11567 Feature_HasNEON | 0, // VLD3LNdWB_register_Asm_32 = 281 11568 Feature_HasNEON | 0, // VLD3LNdWB_register_Asm_8 = 282 11569 Feature_HasNEON | 0, // VLD3LNqAsm_16 = 283 11570 Feature_HasNEON | 0, // VLD3LNqAsm_32 = 284 11571 Feature_HasNEON | 0, // VLD3LNqWB_fixed_Asm_16 = 285 11572 Feature_HasNEON | 0, // VLD3LNqWB_fixed_Asm_32 = 286 11573 Feature_HasNEON | 0, // VLD3LNqWB_register_Asm_16 = 287 11574 Feature_HasNEON | 0, // VLD3LNqWB_register_Asm_32 = 288 11575 Feature_HasNEON | 0, // VLD3dAsm_16 = 289 11576 Feature_HasNEON | 0, // VLD3dAsm_32 = 290 11577 Feature_HasNEON | 0, // VLD3dAsm_8 = 291 11578 Feature_HasNEON | 0, // VLD3dWB_fixed_Asm_16 = 292 11579 Feature_HasNEON | 0, // VLD3dWB_fixed_Asm_32 = 293 11580 Feature_HasNEON | 0, // VLD3dWB_fixed_Asm_8 = 294 11581 Feature_HasNEON | 0, // VLD3dWB_register_Asm_16 = 295 11582 Feature_HasNEON | 0, // VLD3dWB_register_Asm_32 = 296 11583 Feature_HasNEON | 0, // VLD3dWB_register_Asm_8 = 297 11584 Feature_HasNEON | 0, // VLD3qAsm_16 = 298 11585 Feature_HasNEON | 0, // VLD3qAsm_32 = 299 11586 Feature_HasNEON | 0, // VLD3qAsm_8 = 300 11587 Feature_HasNEON | 0, // VLD3qWB_fixed_Asm_16 = 301 11588 Feature_HasNEON | 0, // VLD3qWB_fixed_Asm_32 = 302 11589 Feature_HasNEON | 0, // VLD3qWB_fixed_Asm_8 = 303 11590 Feature_HasNEON | 0, // VLD3qWB_register_Asm_16 = 304 11591 Feature_HasNEON | 0, // VLD3qWB_register_Asm_32 = 305 11592 Feature_HasNEON | 0, // VLD3qWB_register_Asm_8 = 306 11593 Feature_HasNEON | 0, // VLD4DUPdAsm_16 = 307 11594 Feature_HasNEON | 0, // VLD4DUPdAsm_32 = 308 11595 Feature_HasNEON | 0, // VLD4DUPdAsm_8 = 309 11596 Feature_HasNEON | 0, // VLD4DUPdWB_fixed_Asm_16 = 310 11597 Feature_HasNEON | 0, // VLD4DUPdWB_fixed_Asm_32 = 311 11598 Feature_HasNEON | 0, // VLD4DUPdWB_fixed_Asm_8 = 312 11599 Feature_HasNEON | 0, // VLD4DUPdWB_register_Asm_16 = 313 11600 Feature_HasNEON | 0, // VLD4DUPdWB_register_Asm_32 = 314 11601 Feature_HasNEON | 0, // VLD4DUPdWB_register_Asm_8 = 315 11602 Feature_HasNEON | 0, // VLD4DUPqAsm_16 = 316 11603 Feature_HasNEON | 0, // VLD4DUPqAsm_32 = 317 11604 Feature_HasNEON | 0, // VLD4DUPqAsm_8 = 318 11605 Feature_HasNEON | 0, // VLD4DUPqWB_fixed_Asm_16 = 319 11606 Feature_HasNEON | 0, // VLD4DUPqWB_fixed_Asm_32 = 320 11607 Feature_HasNEON | 0, // VLD4DUPqWB_fixed_Asm_8 = 321 11608 Feature_HasNEON | 0, // VLD4DUPqWB_register_Asm_16 = 322 11609 Feature_HasNEON | 0, // VLD4DUPqWB_register_Asm_32 = 323 11610 Feature_HasNEON | 0, // VLD4DUPqWB_register_Asm_8 = 324 11611 Feature_HasNEON | 0, // VLD4LNdAsm_16 = 325 11612 Feature_HasNEON | 0, // VLD4LNdAsm_32 = 326 11613 Feature_HasNEON | 0, // VLD4LNdAsm_8 = 327 11614 Feature_HasNEON | 0, // VLD4LNdWB_fixed_Asm_16 = 328 11615 Feature_HasNEON | 0, // VLD4LNdWB_fixed_Asm_32 = 329 11616 Feature_HasNEON | 0, // VLD4LNdWB_fixed_Asm_8 = 330 11617 Feature_HasNEON | 0, // VLD4LNdWB_register_Asm_16 = 331 11618 Feature_HasNEON | 0, // VLD4LNdWB_register_Asm_32 = 332 11619 Feature_HasNEON | 0, // VLD4LNdWB_register_Asm_8 = 333 11620 Feature_HasNEON | 0, // VLD4LNqAsm_16 = 334 11621 Feature_HasNEON | 0, // VLD4LNqAsm_32 = 335 11622 Feature_HasNEON | 0, // VLD4LNqWB_fixed_Asm_16 = 336 11623 Feature_HasNEON | 0, // VLD4LNqWB_fixed_Asm_32 = 337 11624 Feature_HasNEON | 0, // VLD4LNqWB_register_Asm_16 = 338 11625 Feature_HasNEON | 0, // VLD4LNqWB_register_Asm_32 = 339 11626 Feature_HasNEON | 0, // VLD4dAsm_16 = 340 11627 Feature_HasNEON | 0, // VLD4dAsm_32 = 341 11628 Feature_HasNEON | 0, // VLD4dAsm_8 = 342 11629 Feature_HasNEON | 0, // VLD4dWB_fixed_Asm_16 = 343 11630 Feature_HasNEON | 0, // VLD4dWB_fixed_Asm_32 = 344 11631 Feature_HasNEON | 0, // VLD4dWB_fixed_Asm_8 = 345 11632 Feature_HasNEON | 0, // VLD4dWB_register_Asm_16 = 346 11633 Feature_HasNEON | 0, // VLD4dWB_register_Asm_32 = 347 11634 Feature_HasNEON | 0, // VLD4dWB_register_Asm_8 = 348 11635 Feature_HasNEON | 0, // VLD4qAsm_16 = 349 11636 Feature_HasNEON | 0, // VLD4qAsm_32 = 350 11637 Feature_HasNEON | 0, // VLD4qAsm_8 = 351 11638 Feature_HasNEON | 0, // VLD4qWB_fixed_Asm_16 = 352 11639 Feature_HasNEON | 0, // VLD4qWB_fixed_Asm_32 = 353 11640 Feature_HasNEON | 0, // VLD4qWB_fixed_Asm_8 = 354 11641 Feature_HasNEON | 0, // VLD4qWB_register_Asm_16 = 355 11642 Feature_HasNEON | 0, // VLD4qWB_register_Asm_32 = 356 11643 Feature_HasNEON | 0, // VLD4qWB_register_Asm_8 = 357 11644 0, // VMOVD0 = 358 11645 Feature_HasVFP2 | Feature_HasDPVFP | 0, // VMOVDcc = 359 11646 0, // VMOVQ0 = 360 11647 Feature_HasVFP2 | 0, // VMOVScc = 361 11648 Feature_HasNEON | 0, // VST1LNdAsm_16 = 362 11649 Feature_HasNEON | 0, // VST1LNdAsm_32 = 363 11650 Feature_HasNEON | 0, // VST1LNdAsm_8 = 364 11651 Feature_HasNEON | 0, // VST1LNdWB_fixed_Asm_16 = 365 11652 Feature_HasNEON | 0, // VST1LNdWB_fixed_Asm_32 = 366 11653 Feature_HasNEON | 0, // VST1LNdWB_fixed_Asm_8 = 367 11654 Feature_HasNEON | 0, // VST1LNdWB_register_Asm_16 = 368 11655 Feature_HasNEON | 0, // VST1LNdWB_register_Asm_32 = 369 11656 Feature_HasNEON | 0, // VST1LNdWB_register_Asm_8 = 370 11657 Feature_HasNEON | 0, // VST2LNdAsm_16 = 371 11658 Feature_HasNEON | 0, // VST2LNdAsm_32 = 372 11659 Feature_HasNEON | 0, // VST2LNdAsm_8 = 373 11660 Feature_HasNEON | 0, // VST2LNdWB_fixed_Asm_16 = 374 11661 Feature_HasNEON | 0, // VST2LNdWB_fixed_Asm_32 = 375 11662 Feature_HasNEON | 0, // VST2LNdWB_fixed_Asm_8 = 376 11663 Feature_HasNEON | 0, // VST2LNdWB_register_Asm_16 = 377 11664 Feature_HasNEON | 0, // VST2LNdWB_register_Asm_32 = 378 11665 Feature_HasNEON | 0, // VST2LNdWB_register_Asm_8 = 379 11666 Feature_HasNEON | 0, // VST2LNqAsm_16 = 380 11667 Feature_HasNEON | 0, // VST2LNqAsm_32 = 381 11668 Feature_HasNEON | 0, // VST2LNqWB_fixed_Asm_16 = 382 11669 Feature_HasNEON | 0, // VST2LNqWB_fixed_Asm_32 = 383 11670 Feature_HasNEON | 0, // VST2LNqWB_register_Asm_16 = 384 11671 Feature_HasNEON | 0, // VST2LNqWB_register_Asm_32 = 385 11672 Feature_HasNEON | 0, // VST3LNdAsm_16 = 386 11673 Feature_HasNEON | 0, // VST3LNdAsm_32 = 387 11674 Feature_HasNEON | 0, // VST3LNdAsm_8 = 388 11675 Feature_HasNEON | 0, // VST3LNdWB_fixed_Asm_16 = 389 11676 Feature_HasNEON | 0, // VST3LNdWB_fixed_Asm_32 = 390 11677 Feature_HasNEON | 0, // VST3LNdWB_fixed_Asm_8 = 391 11678 Feature_HasNEON | 0, // VST3LNdWB_register_Asm_16 = 392 11679 Feature_HasNEON | 0, // VST3LNdWB_register_Asm_32 = 393 11680 Feature_HasNEON | 0, // VST3LNdWB_register_Asm_8 = 394 11681 Feature_HasNEON | 0, // VST3LNqAsm_16 = 395 11682 Feature_HasNEON | 0, // VST3LNqAsm_32 = 396 11683 Feature_HasNEON | 0, // VST3LNqWB_fixed_Asm_16 = 397 11684 Feature_HasNEON | 0, // VST3LNqWB_fixed_Asm_32 = 398 11685 Feature_HasNEON | 0, // VST3LNqWB_register_Asm_16 = 399 11686 Feature_HasNEON | 0, // VST3LNqWB_register_Asm_32 = 400 11687 Feature_HasNEON | 0, // VST3dAsm_16 = 401 11688 Feature_HasNEON | 0, // VST3dAsm_32 = 402 11689 Feature_HasNEON | 0, // VST3dAsm_8 = 403 11690 Feature_HasNEON | 0, // VST3dWB_fixed_Asm_16 = 404 11691 Feature_HasNEON | 0, // VST3dWB_fixed_Asm_32 = 405 11692 Feature_HasNEON | 0, // VST3dWB_fixed_Asm_8 = 406 11693 Feature_HasNEON | 0, // VST3dWB_register_Asm_16 = 407 11694 Feature_HasNEON | 0, // VST3dWB_register_Asm_32 = 408 11695 Feature_HasNEON | 0, // VST3dWB_register_Asm_8 = 409 11696 Feature_HasNEON | 0, // VST3qAsm_16 = 410 11697 Feature_HasNEON | 0, // VST3qAsm_32 = 411 11698 Feature_HasNEON | 0, // VST3qAsm_8 = 412 11699 Feature_HasNEON | 0, // VST3qWB_fixed_Asm_16 = 413 11700 Feature_HasNEON | 0, // VST3qWB_fixed_Asm_32 = 414 11701 Feature_HasNEON | 0, // VST3qWB_fixed_Asm_8 = 415 11702 Feature_HasNEON | 0, // VST3qWB_register_Asm_16 = 416 11703 Feature_HasNEON | 0, // VST3qWB_register_Asm_32 = 417 11704 Feature_HasNEON | 0, // VST3qWB_register_Asm_8 = 418 11705 Feature_HasNEON | 0, // VST4LNdAsm_16 = 419 11706 Feature_HasNEON | 0, // VST4LNdAsm_32 = 420 11707 Feature_HasNEON | 0, // VST4LNdAsm_8 = 421 11708 Feature_HasNEON | 0, // VST4LNdWB_fixed_Asm_16 = 422 11709 Feature_HasNEON | 0, // VST4LNdWB_fixed_Asm_32 = 423 11710 Feature_HasNEON | 0, // VST4LNdWB_fixed_Asm_8 = 424 11711 Feature_HasNEON | 0, // VST4LNdWB_register_Asm_16 = 425 11712 Feature_HasNEON | 0, // VST4LNdWB_register_Asm_32 = 426 11713 Feature_HasNEON | 0, // VST4LNdWB_register_Asm_8 = 427 11714 Feature_HasNEON | 0, // VST4LNqAsm_16 = 428 11715 Feature_HasNEON | 0, // VST4LNqAsm_32 = 429 11716 Feature_HasNEON | 0, // VST4LNqWB_fixed_Asm_16 = 430 11717 Feature_HasNEON | 0, // VST4LNqWB_fixed_Asm_32 = 431 11718 Feature_HasNEON | 0, // VST4LNqWB_register_Asm_16 = 432 11719 Feature_HasNEON | 0, // VST4LNqWB_register_Asm_32 = 433 11720 Feature_HasNEON | 0, // VST4dAsm_16 = 434 11721 Feature_HasNEON | 0, // VST4dAsm_32 = 435 11722 Feature_HasNEON | 0, // VST4dAsm_8 = 436 11723 Feature_HasNEON | 0, // VST4dWB_fixed_Asm_16 = 437 11724 Feature_HasNEON | 0, // VST4dWB_fixed_Asm_32 = 438 11725 Feature_HasNEON | 0, // VST4dWB_fixed_Asm_8 = 439 11726 Feature_HasNEON | 0, // VST4dWB_register_Asm_16 = 440 11727 Feature_HasNEON | 0, // VST4dWB_register_Asm_32 = 441 11728 Feature_HasNEON | 0, // VST4dWB_register_Asm_8 = 442 11729 Feature_HasNEON | 0, // VST4qAsm_16 = 443 11730 Feature_HasNEON | 0, // VST4qAsm_32 = 444 11731 Feature_HasNEON | 0, // VST4qAsm_8 = 445 11732 Feature_HasNEON | 0, // VST4qWB_fixed_Asm_16 = 446 11733 Feature_HasNEON | 0, // VST4qWB_fixed_Asm_32 = 447 11734 Feature_HasNEON | 0, // VST4qWB_fixed_Asm_8 = 448 11735 Feature_HasNEON | 0, // VST4qWB_register_Asm_16 = 449 11736 Feature_HasNEON | 0, // VST4qWB_register_Asm_32 = 450 11737 Feature_HasNEON | 0, // VST4qWB_register_Asm_8 = 451 11738 0, // WIN__CHKSTK = 452 11739 0, // WIN__DBZCHK = 453 11740 Feature_IsThumb2 | 0, // t2ABS = 454 11741 Feature_IsThumb2 | 0, // t2ADDSri = 455 11742 Feature_IsThumb2 | 0, // t2ADDSrr = 456 11743 Feature_IsThumb2 | 0, // t2ADDSrs = 457 11744 Feature_IsThumb | Feature_HasV8MBaseline | 0, // t2BR_JT = 458 11745 Feature_IsThumb2 | 0, // t2LDMIA_RET = 459 11746 Feature_IsThumb2 | 0, // t2LDRBpcrel = 460 11747 Feature_IsThumb2 | 0, // t2LDRConstPool = 461 11748 Feature_IsThumb2 | 0, // t2LDRHpcrel = 462 11749 Feature_IsThumb2 | 0, // t2LDRSBpcrel = 463 11750 Feature_IsThumb2 | 0, // t2LDRSHpcrel = 464 11751 Feature_IsThumb2 | 0, // t2LDRpci_pic = 465 11752 Feature_IsThumb2 | 0, // t2LDRpcrel = 466 11753 Feature_IsThumb2 | 0, // t2LEApcrel = 467 11754 Feature_IsThumb2 | 0, // t2LEApcrelJT = 468 11755 Feature_IsThumb2 | 0, // t2MOVCCasr = 469 11756 Feature_IsThumb2 | 0, // t2MOVCCi = 470 11757 Feature_IsThumb2 | 0, // t2MOVCCi16 = 471 11758 Feature_IsThumb2 | 0, // t2MOVCCi32imm = 472 11759 Feature_IsThumb2 | 0, // t2MOVCClsl = 473 11760 Feature_IsThumb2 | 0, // t2MOVCClsr = 474 11761 Feature_IsThumb2 | 0, // t2MOVCCr = 475 11762 Feature_IsThumb2 | 0, // t2MOVCCror = 476 11763 Feature_IsThumb2 | 0, // t2MOVSsi = 477 11764 Feature_IsThumb2 | 0, // t2MOVSsr = 478 11765 Feature_IsThumb | Feature_HasV8MBaseline | 0, // t2MOVTi16_ga_pcrel = 479 11766 Feature_IsThumb | Feature_HasV8MBaseline | 0, // t2MOV_ga_pcrel = 480 11767 0, // t2MOVi16_ga_pcrel = 481 11768 Feature_IsThumb | 0, // t2MOVi32imm = 482 11769 Feature_IsThumb2 | 0, // t2MOVsi = 483 11770 Feature_IsThumb2 | 0, // t2MOVsr = 484 11771 Feature_IsThumb2 | 0, // t2MVNCCi = 485 11772 Feature_IsThumb2 | 0, // t2RSBSri = 486 11773 Feature_IsThumb2 | 0, // t2RSBSrs = 487 11774 Feature_IsThumb2 | 0, // t2STRB_preidx = 488 11775 Feature_IsThumb2 | 0, // t2STRH_preidx = 489 11776 Feature_IsThumb2 | 0, // t2STR_preidx = 490 11777 Feature_IsThumb2 | 0, // t2SUBSri = 491 11778 Feature_IsThumb2 | 0, // t2SUBSrr = 492 11779 Feature_IsThumb2 | 0, // t2SUBSrs = 493 11780 Feature_IsThumb2 | 0, // t2TBB_JT = 494 11781 Feature_IsThumb2 | 0, // t2TBH_JT = 495 11782 0, // tADCS = 496 11783 0, // tADDSi3 = 497 11784 0, // tADDSi8 = 498 11785 0, // tADDSrr = 499 11786 Feature_IsThumb | 0, // tADDframe = 500 11787 Feature_IsThumb | 0, // tADJCALLSTACKDOWN = 501 11788 Feature_IsThumb | 0, // tADJCALLSTACKUP = 502 11789 Feature_IsThumb | 0, // tBRIND = 503 11790 Feature_IsThumb | 0, // tBR_JTr = 504 11791 Feature_IsThumb | 0, // tBX_CALL = 505 11792 Feature_IsThumb | 0, // tBX_RET = 506 11793 Feature_IsThumb | 0, // tBX_RET_vararg = 507 11794 Feature_IsThumb | 0, // tBfar = 508 11795 Feature_IsThumb | 0, // tLDMIA_UPD = 509 11796 Feature_IsThumb | 0, // tLDRConstPool = 510 11797 Feature_IsThumb | 0, // tLDRLIT_ga_abs = 511 11798 Feature_IsThumb | 0, // tLDRLIT_ga_pcrel = 512 11799 Feature_IsThumb | 0, // tLDR_postidx = 513 11800 Feature_IsThumb | 0, // tLDRpci_pic = 514 11801 Feature_IsThumb | 0, // tLEApcrel = 515 11802 Feature_IsThumb | 0, // tLEApcrelJT = 516 11803 0, // tMOVCCr_pseudo = 517 11804 Feature_IsThumb | 0, // tPOP_RET = 518 11805 0, // tSBCS = 519 11806 0, // tSUBSi3 = 520 11807 0, // tSUBSi8 = 521 11808 0, // tSUBSrr = 522 11809 Feature_IsThumb2 | 0, // tTAILJMPd = 523 11810 Feature_IsThumb | 0, // tTAILJMPdND = 524 11811 Feature_IsThumb | 0, // tTAILJMPr = 525 11812 Feature_IsThumb | 0, // tTBB_JT = 526 11813 Feature_IsThumb | 0, // tTBH_JT = 527 11814 Feature_IsThumb | 0, // tTPsoft = 528 11815 Feature_IsARM | 0, // ADCri = 529 11816 Feature_IsARM | 0, // ADCrr = 530 11817 Feature_IsARM | 0, // ADCrsi = 531 11818 Feature_IsARM | 0, // ADCrsr = 532 11819 Feature_IsARM | 0, // ADDri = 533 11820 Feature_IsARM | 0, // ADDrr = 534 11821 Feature_IsARM | 0, // ADDrsi = 535 11822 Feature_IsARM | 0, // ADDrsr = 536 11823 Feature_IsARM | 0, // ADR = 537 11824 Feature_HasV8 | Feature_HasCrypto | 0, // AESD = 538 11825 Feature_HasV8 | Feature_HasCrypto | 0, // AESE = 539 11826 Feature_HasV8 | Feature_HasCrypto | 0, // AESIMC = 540 11827 Feature_HasV8 | Feature_HasCrypto | 0, // AESMC = 541 11828 Feature_IsARM | 0, // ANDri = 542 11829 Feature_IsARM | 0, // ANDrr = 543 11830 Feature_IsARM | 0, // ANDrsi = 544 11831 Feature_IsARM | 0, // ANDrsr = 545 11832 Feature_IsARM | Feature_HasV6T2 | 0, // BFC = 546 11833 Feature_IsARM | Feature_HasV6T2 | 0, // BFI = 547 11834 Feature_IsARM | 0, // BICri = 548 11835 Feature_IsARM | 0, // BICrr = 549 11836 Feature_IsARM | 0, // BICrsi = 550 11837 Feature_IsARM | 0, // BICrsr = 551 11838 Feature_IsARM | 0, // BKPT = 552 11839 Feature_IsARM | 0, // BL = 553 11840 Feature_IsARM | Feature_HasV5T | 0, // BLX = 554 11841 Feature_IsARM | Feature_HasV5T | 0, // BLX_pred = 555 11842 Feature_IsARM | Feature_HasV5T | 0, // BLXi = 556 11843 Feature_IsARM | 0, // BL_pred = 557 11844 Feature_IsARM | Feature_HasV4T | 0, // BX = 558 11845 Feature_IsARM | 0, // BXJ = 559 11846 Feature_IsARM | Feature_HasV4T | 0, // BX_RET = 560 11847 Feature_IsARM | Feature_HasV4T | 0, // BX_pred = 561 11848 Feature_IsARM | 0, // Bcc = 562 11849 Feature_IsARM | Feature_PreV8 | 0, // CDP = 563 11850 Feature_IsARM | Feature_PreV8 | 0, // CDP2 = 564 11851 Feature_IsARM | Feature_HasV6K | 0, // CLREX = 565 11852 Feature_IsARM | Feature_HasV5T | 0, // CLZ = 566 11853 Feature_IsARM | 0, // CMNri = 567 11854 Feature_IsARM | 0, // CMNzrr = 568 11855 Feature_IsARM | 0, // CMNzrsi = 569 11856 Feature_IsARM | 0, // CMNzrsr = 570 11857 Feature_IsARM | 0, // CMPri = 571 11858 Feature_IsARM | 0, // CMPrr = 572 11859 Feature_IsARM | 0, // CMPrsi = 573 11860 Feature_IsARM | 0, // CMPrsr = 574 11861 Feature_IsARM | 0, // CPS1p = 575 11862 Feature_IsARM | 0, // CPS2p = 576 11863 Feature_IsARM | 0, // CPS3p = 577 11864 Feature_IsARM | Feature_HasV8 | Feature_HasCRC | 0, // CRC32B = 578 11865 Feature_IsARM | Feature_HasV8 | Feature_HasCRC | 0, // CRC32CB = 579 11866 Feature_IsARM | Feature_HasV8 | Feature_HasCRC | 0, // CRC32CH = 580 11867 Feature_IsARM | Feature_HasV8 | Feature_HasCRC | 0, // CRC32CW = 581 11868 Feature_IsARM | Feature_HasV8 | Feature_HasCRC | 0, // CRC32H = 582 11869 Feature_IsARM | Feature_HasV8 | Feature_HasCRC | 0, // CRC32W = 583 11870 Feature_IsARM | Feature_HasV7 | 0, // DBG = 584 11871 Feature_IsARM | Feature_HasDB | 0, // DMB = 585 11872 Feature_IsARM | Feature_HasDB | 0, // DSB = 586 11873 Feature_IsARM | 0, // EORri = 587 11874 Feature_IsARM | 0, // EORrr = 588 11875 Feature_IsARM | 0, // EORrsi = 589 11876 Feature_IsARM | 0, // EORrsr = 590 11877 Feature_IsARM | Feature_HasVirtualization | 0, // ERET = 591 11878 Feature_HasVFP3 | Feature_HasDPVFP | 0, // FCONSTD = 592 11879 Feature_HasFullFP16 | 0, // FCONSTH = 593 11880 Feature_HasVFP3 | 0, // FCONSTS = 594 11881 Feature_HasVFP2 | 0, // FLDMXDB_UPD = 595 11882 Feature_HasVFP2 | 0, // FLDMXIA = 596 11883 Feature_HasVFP2 | 0, // FLDMXIA_UPD = 597 11884 Feature_HasVFP2 | 0, // FMSTAT = 598 11885 Feature_HasVFP2 | 0, // FSTMXDB_UPD = 599 11886 Feature_HasVFP2 | 0, // FSTMXIA = 600 11887 Feature_HasVFP2 | 0, // FSTMXIA_UPD = 601 11888 Feature_IsARM | Feature_HasV6 | 0, // HINT = 602 11889 Feature_IsARM | Feature_HasV8 | 0, // HLT = 603 11890 Feature_IsARM | Feature_HasVirtualization | 0, // HVC = 604 11891 Feature_IsARM | Feature_HasDB | 0, // ISB = 605 11892 Feature_IsARM | Feature_HasAcquireRelease | 0, // LDA = 606 11893 Feature_IsARM | Feature_HasAcquireRelease | 0, // LDAB = 607 11894 Feature_IsARM | Feature_HasAcquireRelease | Feature_HasV7Clrex | 0, // LDAEX = 608 11895 Feature_IsARM | Feature_HasAcquireRelease | Feature_HasV7Clrex | 0, // LDAEXB = 609 11896 Feature_IsARM | Feature_HasAcquireRelease | Feature_HasV7Clrex | 0, // LDAEXD = 610 11897 Feature_IsARM | Feature_HasAcquireRelease | Feature_HasV7Clrex | 0, // LDAEXH = 611 11898 Feature_IsARM | Feature_HasAcquireRelease | 0, // LDAH = 612 11899 Feature_IsARM | Feature_PreV8 | 0, // LDC2L_OFFSET = 613 11900 Feature_IsARM | Feature_PreV8 | 0, // LDC2L_OPTION = 614 11901 Feature_IsARM | Feature_PreV8 | 0, // LDC2L_POST = 615 11902 Feature_IsARM | Feature_PreV8 | 0, // LDC2L_PRE = 616 11903 Feature_IsARM | Feature_PreV8 | 0, // LDC2_OFFSET = 617 11904 Feature_IsARM | Feature_PreV8 | 0, // LDC2_OPTION = 618 11905 Feature_IsARM | Feature_PreV8 | 0, // LDC2_POST = 619 11906 Feature_IsARM | Feature_PreV8 | 0, // LDC2_PRE = 620 11907 Feature_IsARM | 0, // LDCL_OFFSET = 621 11908 Feature_IsARM | 0, // LDCL_OPTION = 622 11909 Feature_IsARM | 0, // LDCL_POST = 623 11910 Feature_IsARM | 0, // LDCL_PRE = 624 11911 Feature_IsARM | 0, // LDC_OFFSET = 625 11912 Feature_IsARM | 0, // LDC_OPTION = 626 11913 Feature_IsARM | 0, // LDC_POST = 627 11914 Feature_IsARM | 0, // LDC_PRE = 628 11915 Feature_IsARM | 0, // LDMDA = 629 11916 Feature_IsARM | 0, // LDMDA_UPD = 630 11917 Feature_IsARM | 0, // LDMDB = 631 11918 Feature_IsARM | 0, // LDMDB_UPD = 632 11919 Feature_IsARM | 0, // LDMIA = 633 11920 Feature_IsARM | 0, // LDMIA_UPD = 634 11921 Feature_IsARM | 0, // LDMIB = 635 11922 Feature_IsARM | 0, // LDMIB_UPD = 636 11923 Feature_IsARM | 0, // LDRBT_POST_IMM = 637 11924 Feature_IsARM | 0, // LDRBT_POST_REG = 638 11925 Feature_IsARM | 0, // LDRB_POST_IMM = 639 11926 Feature_IsARM | 0, // LDRB_POST_REG = 640 11927 Feature_IsARM | 0, // LDRB_PRE_IMM = 641 11928 Feature_IsARM | 0, // LDRB_PRE_REG = 642 11929 Feature_IsARM | 0, // LDRBi12 = 643 11930 Feature_IsARM | 0, // LDRBrs = 644 11931 Feature_IsARM | Feature_HasV5TE | 0, // LDRD = 645 11932 Feature_IsARM | 0, // LDRD_POST = 646 11933 Feature_IsARM | 0, // LDRD_PRE = 647 11934 Feature_IsARM | 0, // LDREX = 648 11935 Feature_IsARM | 0, // LDREXB = 649 11936 Feature_IsARM | 0, // LDREXD = 650 11937 Feature_IsARM | 0, // LDREXH = 651 11938 Feature_IsARM | 0, // LDRH = 652 11939 Feature_IsARM | 0, // LDRHTi = 653 11940 Feature_IsARM | 0, // LDRHTr = 654 11941 Feature_IsARM | 0, // LDRH_POST = 655 11942 Feature_IsARM | 0, // LDRH_PRE = 656 11943 Feature_IsARM | 0, // LDRSB = 657 11944 Feature_IsARM | 0, // LDRSBTi = 658 11945 Feature_IsARM | 0, // LDRSBTr = 659 11946 Feature_IsARM | 0, // LDRSB_POST = 660 11947 Feature_IsARM | 0, // LDRSB_PRE = 661 11948 Feature_IsARM | 0, // LDRSH = 662 11949 Feature_IsARM | 0, // LDRSHTi = 663 11950 Feature_IsARM | 0, // LDRSHTr = 664 11951 Feature_IsARM | 0, // LDRSH_POST = 665 11952 Feature_IsARM | 0, // LDRSH_PRE = 666 11953 Feature_IsARM | 0, // LDRT_POST_IMM = 667 11954 Feature_IsARM | 0, // LDRT_POST_REG = 668 11955 Feature_IsARM | 0, // LDR_POST_IMM = 669 11956 Feature_IsARM | 0, // LDR_POST_REG = 670 11957 Feature_IsARM | 0, // LDR_PRE_IMM = 671 11958 Feature_IsARM | 0, // LDR_PRE_REG = 672 11959 Feature_IsARM | 0, // LDRcp = 673 11960 Feature_IsARM | 0, // LDRi12 = 674 11961 Feature_IsARM | 0, // LDRrs = 675 11962 Feature_IsARM | 0, // MCR = 676 11963 Feature_IsARM | Feature_PreV8 | 0, // MCR2 = 677 11964 Feature_IsARM | 0, // MCRR = 678 11965 Feature_IsARM | Feature_PreV8 | 0, // MCRR2 = 679 11966 Feature_IsARM | Feature_HasV6 | 0, // MLA = 680 11967 Feature_IsARM | Feature_HasV6T2 | 0, // MLS = 681 11968 Feature_IsARM | 0, // MOVPCLR = 682 11969 Feature_IsARM | Feature_HasV6T2 | 0, // MOVTi16 = 683 11970 Feature_IsARM | 0, // MOVi = 684 11971 Feature_IsARM | Feature_HasV6T2 | 0, // MOVi16 = 685 11972 Feature_IsARM | 0, // MOVr = 686 11973 Feature_IsARM | 0, // MOVr_TC = 687 11974 Feature_IsARM | 0, // MOVsi = 688 11975 Feature_IsARM | 0, // MOVsr = 689 11976 Feature_IsARM | 0, // MRC = 690 11977 Feature_IsARM | Feature_PreV8 | 0, // MRC2 = 691 11978 Feature_IsARM | 0, // MRRC = 692 11979 Feature_IsARM | Feature_PreV8 | 0, // MRRC2 = 693 11980 Feature_IsARM | 0, // MRS = 694 11981 Feature_IsARM | Feature_HasVirtualization | 0, // MRSbanked = 695 11982 Feature_IsARM | 0, // MRSsys = 696 11983 Feature_IsARM | 0, // MSR = 697 11984 Feature_IsARM | Feature_HasVirtualization | 0, // MSRbanked = 698 11985 Feature_IsARM | 0, // MSRi = 699 11986 Feature_IsARM | Feature_HasV6 | 0, // MUL = 700 11987 Feature_IsARM | 0, // MVNi = 701 11988 Feature_IsARM | 0, // MVNr = 702 11989 Feature_IsARM | 0, // MVNsi = 703 11990 Feature_IsARM | 0, // MVNsr = 704 11991 Feature_IsARM | 0, // ORRri = 705 11992 Feature_IsARM | 0, // ORRrr = 706 11993 Feature_IsARM | 0, // ORRrsi = 707 11994 Feature_IsARM | 0, // ORRrsr = 708 11995 Feature_IsARM | Feature_HasV6 | 0, // PKHBT = 709 11996 Feature_IsARM | Feature_HasV6 | 0, // PKHTB = 710 11997 Feature_IsARM | Feature_HasV7 | Feature_HasMP | 0, // PLDWi12 = 711 11998 Feature_IsARM | Feature_HasV7 | Feature_HasMP | 0, // PLDWrs = 712 11999 Feature_IsARM | 0, // PLDi12 = 713 12000 Feature_IsARM | 0, // PLDrs = 714 12001 Feature_IsARM | Feature_HasV7 | 0, // PLIi12 = 715 12002 Feature_IsARM | Feature_HasV7 | 0, // PLIrs = 716 12003 Feature_IsARM | 0, // QADD = 717 12004 Feature_IsARM | 0, // QADD16 = 718 12005 Feature_IsARM | 0, // QADD8 = 719 12006 Feature_IsARM | 0, // QASX = 720 12007 Feature_IsARM | 0, // QDADD = 721 12008 Feature_IsARM | 0, // QDSUB = 722 12009 Feature_IsARM | 0, // QSAX = 723 12010 Feature_IsARM | 0, // QSUB = 724 12011 Feature_IsARM | 0, // QSUB16 = 725 12012 Feature_IsARM | 0, // QSUB8 = 726 12013 Feature_IsARM | Feature_HasV6T2 | 0, // RBIT = 727 12014 Feature_IsARM | Feature_HasV6 | 0, // REV = 728 12015 Feature_IsARM | Feature_HasV6 | 0, // REV16 = 729 12016 Feature_IsARM | Feature_HasV6 | 0, // REVSH = 730 12017 Feature_IsARM | 0, // RFEDA = 731 12018 Feature_IsARM | 0, // RFEDA_UPD = 732 12019 Feature_IsARM | 0, // RFEDB = 733 12020 Feature_IsARM | 0, // RFEDB_UPD = 734 12021 Feature_IsARM | 0, // RFEIA = 735 12022 Feature_IsARM | 0, // RFEIA_UPD = 736 12023 Feature_IsARM | 0, // RFEIB = 737 12024 Feature_IsARM | 0, // RFEIB_UPD = 738 12025 Feature_IsARM | 0, // RSBri = 739 12026 Feature_IsARM | 0, // RSBrr = 740 12027 Feature_IsARM | 0, // RSBrsi = 741 12028 Feature_IsARM | 0, // RSBrsr = 742 12029 Feature_IsARM | 0, // RSCri = 743 12030 Feature_IsARM | 0, // RSCrr = 744 12031 Feature_IsARM | 0, // RSCrsi = 745 12032 Feature_IsARM | 0, // RSCrsr = 746 12033 Feature_IsARM | 0, // SADD16 = 747 12034 Feature_IsARM | 0, // SADD8 = 748 12035 Feature_IsARM | 0, // SASX = 749 12036 Feature_IsARM | 0, // SBCri = 750 12037 Feature_IsARM | 0, // SBCrr = 751 12038 Feature_IsARM | 0, // SBCrsi = 752 12039 Feature_IsARM | 0, // SBCrsr = 753 12040 Feature_IsARM | Feature_HasV6T2 | 0, // SBFX = 754 12041 Feature_IsARM | Feature_HasDivideInARM | 0, // SDIV = 755 12042 Feature_IsARM | Feature_HasV6 | 0, // SEL = 756 12043 Feature_IsARM | 0, // SETEND = 757 12044 Feature_IsARM | Feature_HasV8 | Feature_HasV8_1a | 0, // SETPAN = 758 12045 Feature_HasV8 | Feature_HasCrypto | 0, // SHA1C = 759 12046 Feature_HasV8 | Feature_HasCrypto | 0, // SHA1H = 760 12047 Feature_HasV8 | Feature_HasCrypto | 0, // SHA1M = 761 12048 Feature_HasV8 | Feature_HasCrypto | 0, // SHA1P = 762 12049 Feature_HasV8 | Feature_HasCrypto | 0, // SHA1SU0 = 763 12050 Feature_HasV8 | Feature_HasCrypto | 0, // SHA1SU1 = 764 12051 Feature_HasV8 | Feature_HasCrypto | 0, // SHA256H = 765 12052 Feature_HasV8 | Feature_HasCrypto | 0, // SHA256H2 = 766 12053 Feature_HasV8 | Feature_HasCrypto | 0, // SHA256SU0 = 767 12054 Feature_HasV8 | Feature_HasCrypto | 0, // SHA256SU1 = 768 12055 Feature_IsARM | 0, // SHADD16 = 769 12056 Feature_IsARM | 0, // SHADD8 = 770 12057 Feature_IsARM | 0, // SHASX = 771 12058 Feature_IsARM | 0, // SHSAX = 772 12059 Feature_IsARM | 0, // SHSUB16 = 773 12060 Feature_IsARM | 0, // SHSUB8 = 774 12061 Feature_IsARM | Feature_HasTrustZone | 0, // SMC = 775 12062 Feature_IsARM | Feature_HasV5TE | 0, // SMLABB = 776 12063 Feature_IsARM | Feature_HasV5TE | 0, // SMLABT = 777 12064 Feature_IsARM | Feature_HasV6 | 0, // SMLAD = 778 12065 Feature_IsARM | Feature_HasV6 | 0, // SMLADX = 779 12066 Feature_IsARM | Feature_HasV6 | 0, // SMLAL = 780 12067 Feature_IsARM | Feature_HasV5TE | 0, // SMLALBB = 781 12068 Feature_IsARM | Feature_HasV5TE | 0, // SMLALBT = 782 12069 Feature_IsARM | Feature_HasV6 | 0, // SMLALD = 783 12070 Feature_IsARM | Feature_HasV6 | 0, // SMLALDX = 784 12071 Feature_IsARM | Feature_HasV5TE | 0, // SMLALTB = 785 12072 Feature_IsARM | Feature_HasV5TE | 0, // SMLALTT = 786 12073 Feature_IsARM | Feature_HasV5TE | 0, // SMLATB = 787 12074 Feature_IsARM | Feature_HasV5TE | 0, // SMLATT = 788 12075 Feature_IsARM | Feature_HasV5TE | 0, // SMLAWB = 789 12076 Feature_IsARM | Feature_HasV5TE | 0, // SMLAWT = 790 12077 Feature_IsARM | Feature_HasV6 | 0, // SMLSD = 791 12078 Feature_IsARM | Feature_HasV6 | 0, // SMLSDX = 792 12079 Feature_IsARM | Feature_HasV6 | 0, // SMLSLD = 793 12080 Feature_IsARM | Feature_HasV6 | 0, // SMLSLDX = 794 12081 Feature_IsARM | Feature_HasV6 | 0, // SMMLA = 795 12082 Feature_IsARM | Feature_HasV6 | 0, // SMMLAR = 796 12083 Feature_IsARM | Feature_HasV6 | 0, // SMMLS = 797 12084 Feature_IsARM | Feature_HasV6 | 0, // SMMLSR = 798 12085 Feature_IsARM | Feature_HasV6 | 0, // SMMUL = 799 12086 Feature_IsARM | Feature_HasV6 | 0, // SMMULR = 800 12087 Feature_IsARM | Feature_HasV6 | 0, // SMUAD = 801 12088 Feature_IsARM | Feature_HasV6 | 0, // SMUADX = 802 12089 Feature_IsARM | Feature_HasV5TE | 0, // SMULBB = 803 12090 Feature_IsARM | Feature_HasV5TE | 0, // SMULBT = 804 12091 Feature_IsARM | Feature_HasV6 | 0, // SMULL = 805 12092 Feature_IsARM | Feature_HasV5TE | 0, // SMULTB = 806 12093 Feature_IsARM | Feature_HasV5TE | 0, // SMULTT = 807 12094 Feature_IsARM | Feature_HasV5TE | 0, // SMULWB = 808 12095 Feature_IsARM | Feature_HasV5TE | 0, // SMULWT = 809 12096 Feature_IsARM | Feature_HasV6 | 0, // SMUSD = 810 12097 Feature_IsARM | Feature_HasV6 | 0, // SMUSDX = 811 12098 Feature_IsARM | 0, // SRSDA = 812 12099 Feature_IsARM | 0, // SRSDA_UPD = 813 12100 Feature_IsARM | 0, // SRSDB = 814 12101 Feature_IsARM | 0, // SRSDB_UPD = 815 12102 Feature_IsARM | 0, // SRSIA = 816 12103 Feature_IsARM | 0, // SRSIA_UPD = 817 12104 Feature_IsARM | 0, // SRSIB = 818 12105 Feature_IsARM | 0, // SRSIB_UPD = 819 12106 Feature_IsARM | Feature_HasV6 | 0, // SSAT = 820 12107 Feature_IsARM | Feature_HasV6 | 0, // SSAT16 = 821 12108 Feature_IsARM | 0, // SSAX = 822 12109 Feature_IsARM | 0, // SSUB16 = 823 12110 Feature_IsARM | 0, // SSUB8 = 824 12111 Feature_IsARM | Feature_PreV8 | 0, // STC2L_OFFSET = 825 12112 Feature_IsARM | Feature_PreV8 | 0, // STC2L_OPTION = 826 12113 Feature_IsARM | Feature_PreV8 | 0, // STC2L_POST = 827 12114 Feature_IsARM | Feature_PreV8 | 0, // STC2L_PRE = 828 12115 Feature_IsARM | Feature_PreV8 | 0, // STC2_OFFSET = 829 12116 Feature_IsARM | Feature_PreV8 | 0, // STC2_OPTION = 830 12117 Feature_IsARM | Feature_PreV8 | 0, // STC2_POST = 831 12118 Feature_IsARM | Feature_PreV8 | 0, // STC2_PRE = 832 12119 Feature_IsARM | 0, // STCL_OFFSET = 833 12120 Feature_IsARM | 0, // STCL_OPTION = 834 12121 Feature_IsARM | 0, // STCL_POST = 835 12122 Feature_IsARM | 0, // STCL_PRE = 836 12123 Feature_IsARM | 0, // STC_OFFSET = 837 12124 Feature_IsARM | 0, // STC_OPTION = 838 12125 Feature_IsARM | 0, // STC_POST = 839 12126 Feature_IsARM | 0, // STC_PRE = 840 12127 Feature_IsARM | Feature_HasAcquireRelease | 0, // STL = 841 12128 Feature_IsARM | Feature_HasAcquireRelease | 0, // STLB = 842 12129 Feature_IsARM | Feature_HasAcquireRelease | Feature_HasV7Clrex | 0, // STLEX = 843 12130 Feature_IsARM | Feature_HasAcquireRelease | Feature_HasV7Clrex | 0, // STLEXB = 844 12131 Feature_IsARM | Feature_HasAcquireRelease | Feature_HasV7Clrex | 0, // STLEXD = 845 12132 Feature_IsARM | Feature_HasAcquireRelease | Feature_HasV7Clrex | 0, // STLEXH = 846 12133 Feature_IsARM | Feature_HasAcquireRelease | 0, // STLH = 847 12134 Feature_IsARM | 0, // STMDA = 848 12135 Feature_IsARM | 0, // STMDA_UPD = 849 12136 Feature_IsARM | 0, // STMDB = 850 12137 Feature_IsARM | 0, // STMDB_UPD = 851 12138 Feature_IsARM | 0, // STMIA = 852 12139 Feature_IsARM | 0, // STMIA_UPD = 853 12140 Feature_IsARM | 0, // STMIB = 854 12141 Feature_IsARM | 0, // STMIB_UPD = 855 12142 Feature_IsARM | 0, // STRBT_POST_IMM = 856 12143 Feature_IsARM | 0, // STRBT_POST_REG = 857 12144 Feature_IsARM | 0, // STRB_POST_IMM = 858 12145 Feature_IsARM | 0, // STRB_POST_REG = 859 12146 Feature_IsARM | 0, // STRB_PRE_IMM = 860 12147 Feature_IsARM | 0, // STRB_PRE_REG = 861 12148 Feature_IsARM | 0, // STRBi12 = 862 12149 Feature_IsARM | 0, // STRBrs = 863 12150 Feature_IsARM | Feature_HasV5TE | 0, // STRD = 864 12151 Feature_IsARM | 0, // STRD_POST = 865 12152 Feature_IsARM | 0, // STRD_PRE = 866 12153 Feature_IsARM | 0, // STREX = 867 12154 Feature_IsARM | 0, // STREXB = 868 12155 Feature_IsARM | 0, // STREXD = 869 12156 Feature_IsARM | 0, // STREXH = 870 12157 Feature_IsARM | 0, // STRH = 871 12158 Feature_IsARM | 0, // STRHTi = 872 12159 Feature_IsARM | 0, // STRHTr = 873 12160 Feature_IsARM | 0, // STRH_POST = 874 12161 Feature_IsARM | 0, // STRH_PRE = 875 12162 Feature_IsARM | 0, // STRT_POST_IMM = 876 12163 Feature_IsARM | 0, // STRT_POST_REG = 877 12164 Feature_IsARM | 0, // STR_POST_IMM = 878 12165 Feature_IsARM | 0, // STR_POST_REG = 879 12166 Feature_IsARM | 0, // STR_PRE_IMM = 880 12167 Feature_IsARM | 0, // STR_PRE_REG = 881 12168 Feature_IsARM | 0, // STRi12 = 882 12169 Feature_IsARM | 0, // STRrs = 883 12170 Feature_IsARM | 0, // SUBri = 884 12171 Feature_IsARM | 0, // SUBrr = 885 12172 Feature_IsARM | 0, // SUBrsi = 886 12173 Feature_IsARM | 0, // SUBrsr = 887 12174 Feature_IsARM | 0, // SVC = 888 12175 Feature_IsARM | Feature_PreV8 | 0, // SWP = 889 12176 Feature_IsARM | Feature_PreV8 | 0, // SWPB = 890 12177 Feature_IsARM | Feature_HasV6 | 0, // SXTAB = 891 12178 Feature_IsARM | Feature_HasV6 | 0, // SXTAB16 = 892 12179 Feature_IsARM | Feature_HasV6 | 0, // SXTAH = 893 12180 Feature_IsARM | Feature_HasV6 | 0, // SXTB = 894 12181 Feature_IsARM | Feature_HasV6 | 0, // SXTB16 = 895 12182 Feature_IsARM | Feature_HasV6 | 0, // SXTH = 896 12183 Feature_IsARM | 0, // TEQri = 897 12184 Feature_IsARM | 0, // TEQrr = 898 12185 Feature_IsARM | 0, // TEQrsi = 899 12186 Feature_IsARM | 0, // TEQrsr = 900 12187 Feature_IsARM | 0, // TRAP = 901 12188 Feature_IsARM | Feature_UseNaClTrap | 0, // TRAPNaCl = 902 12189 Feature_IsARM | Feature_HasV8_4a | 0, // TSB = 903 12190 Feature_IsARM | 0, // TSTri = 904 12191 Feature_IsARM | 0, // TSTrr = 905 12192 Feature_IsARM | 0, // TSTrsi = 906 12193 Feature_IsARM | 0, // TSTrsr = 907 12194 Feature_IsARM | 0, // UADD16 = 908 12195 Feature_IsARM | 0, // UADD8 = 909 12196 Feature_IsARM | 0, // UASX = 910 12197 Feature_IsARM | Feature_HasV6T2 | 0, // UBFX = 911 12198 Feature_IsARM | 0, // UDF = 912 12199 Feature_IsARM | Feature_HasDivideInARM | 0, // UDIV = 913 12200 Feature_IsARM | 0, // UHADD16 = 914 12201 Feature_IsARM | 0, // UHADD8 = 915 12202 Feature_IsARM | 0, // UHASX = 916 12203 Feature_IsARM | 0, // UHSAX = 917 12204 Feature_IsARM | 0, // UHSUB16 = 918 12205 Feature_IsARM | 0, // UHSUB8 = 919 12206 Feature_IsARM | Feature_HasV6 | 0, // UMAAL = 920 12207 Feature_IsARM | Feature_HasV6 | 0, // UMLAL = 921 12208 Feature_IsARM | Feature_HasV6 | 0, // UMULL = 922 12209 Feature_IsARM | 0, // UQADD16 = 923 12210 Feature_IsARM | 0, // UQADD8 = 924 12211 Feature_IsARM | 0, // UQASX = 925 12212 Feature_IsARM | 0, // UQSAX = 926 12213 Feature_IsARM | 0, // UQSUB16 = 927 12214 Feature_IsARM | 0, // UQSUB8 = 928 12215 Feature_IsARM | Feature_HasV6 | 0, // USAD8 = 929 12216 Feature_IsARM | Feature_HasV6 | 0, // USADA8 = 930 12217 Feature_IsARM | Feature_HasV6 | 0, // USAT = 931 12218 Feature_IsARM | Feature_HasV6 | 0, // USAT16 = 932 12219 Feature_IsARM | 0, // USAX = 933 12220 Feature_IsARM | 0, // USUB16 = 934 12221 Feature_IsARM | 0, // USUB8 = 935 12222 Feature_IsARM | Feature_HasV6 | 0, // UXTAB = 936 12223 Feature_IsARM | Feature_HasV6 | 0, // UXTAB16 = 937 12224 Feature_IsARM | Feature_HasV6 | 0, // UXTAH = 938 12225 Feature_IsARM | Feature_HasV6 | 0, // UXTB = 939 12226 Feature_IsARM | Feature_HasV6 | 0, // UXTB16 = 940 12227 Feature_IsARM | Feature_HasV6 | 0, // UXTH = 941 12228 Feature_HasNEON | 0, // VABALsv2i64 = 942 12229 Feature_HasNEON | 0, // VABALsv4i32 = 943 12230 Feature_HasNEON | 0, // VABALsv8i16 = 944 12231 Feature_HasNEON | 0, // VABALuv2i64 = 945 12232 Feature_HasNEON | 0, // VABALuv4i32 = 946 12233 Feature_HasNEON | 0, // VABALuv8i16 = 947 12234 Feature_HasNEON | 0, // VABAsv16i8 = 948 12235 Feature_HasNEON | 0, // VABAsv2i32 = 949 12236 Feature_HasNEON | 0, // VABAsv4i16 = 950 12237 Feature_HasNEON | 0, // VABAsv4i32 = 951 12238 Feature_HasNEON | 0, // VABAsv8i16 = 952 12239 Feature_HasNEON | 0, // VABAsv8i8 = 953 12240 Feature_HasNEON | 0, // VABAuv16i8 = 954 12241 Feature_HasNEON | 0, // VABAuv2i32 = 955 12242 Feature_HasNEON | 0, // VABAuv4i16 = 956 12243 Feature_HasNEON | 0, // VABAuv4i32 = 957 12244 Feature_HasNEON | 0, // VABAuv8i16 = 958 12245 Feature_HasNEON | 0, // VABAuv8i8 = 959 12246 Feature_HasNEON | 0, // VABDLsv2i64 = 960 12247 Feature_HasNEON | 0, // VABDLsv4i32 = 961 12248 Feature_HasNEON | 0, // VABDLsv8i16 = 962 12249 Feature_HasNEON | 0, // VABDLuv2i64 = 963 12250 Feature_HasNEON | 0, // VABDLuv4i32 = 964 12251 Feature_HasNEON | 0, // VABDLuv8i16 = 965 12252 Feature_HasNEON | 0, // VABDfd = 966 12253 Feature_HasNEON | 0, // VABDfq = 967 12254 Feature_HasNEON | Feature_HasFullFP16 | 0, // VABDhd = 968 12255 Feature_HasNEON | Feature_HasFullFP16 | 0, // VABDhq = 969 12256 Feature_HasNEON | 0, // VABDsv16i8 = 970 12257 Feature_HasNEON | 0, // VABDsv2i32 = 971 12258 Feature_HasNEON | 0, // VABDsv4i16 = 972 12259 Feature_HasNEON | 0, // VABDsv4i32 = 973 12260 Feature_HasNEON | 0, // VABDsv8i16 = 974 12261 Feature_HasNEON | 0, // VABDsv8i8 = 975 12262 Feature_HasNEON | 0, // VABDuv16i8 = 976 12263 Feature_HasNEON | 0, // VABDuv2i32 = 977 12264 Feature_HasNEON | 0, // VABDuv4i16 = 978 12265 Feature_HasNEON | 0, // VABDuv4i32 = 979 12266 Feature_HasNEON | 0, // VABDuv8i16 = 980 12267 Feature_HasNEON | 0, // VABDuv8i8 = 981 12268 Feature_HasVFP2 | Feature_HasDPVFP | 0, // VABSD = 982 12269 Feature_HasFullFP16 | 0, // VABSH = 983 12270 Feature_HasVFP2 | 0, // VABSS = 984 12271 Feature_HasNEON | 0, // VABSfd = 985 12272 Feature_HasNEON | 0, // VABSfq = 986 12273 Feature_HasNEON | Feature_HasFullFP16 | 0, // VABShd = 987 12274 Feature_HasNEON | Feature_HasFullFP16 | 0, // VABShq = 988 12275 Feature_HasNEON | 0, // VABSv16i8 = 989 12276 Feature_HasNEON | 0, // VABSv2i32 = 990 12277 Feature_HasNEON | 0, // VABSv4i16 = 991 12278 Feature_HasNEON | 0, // VABSv4i32 = 992 12279 Feature_HasNEON | 0, // VABSv8i16 = 993 12280 Feature_HasNEON | 0, // VABSv8i8 = 994 12281 Feature_HasNEON | 0, // VACGEfd = 995 12282 Feature_HasNEON | 0, // VACGEfq = 996 12283 Feature_HasNEON | Feature_HasFullFP16 | 0, // VACGEhd = 997 12284 Feature_HasNEON | Feature_HasFullFP16 | 0, // VACGEhq = 998 12285 Feature_HasNEON | 0, // VACGTfd = 999 12286 Feature_HasNEON | 0, // VACGTfq = 1000 12287 Feature_HasNEON | Feature_HasFullFP16 | 0, // VACGThd = 1001 12288 Feature_HasNEON | Feature_HasFullFP16 | 0, // VACGThq = 1002 12289 Feature_HasVFP2 | Feature_HasDPVFP | 0, // VADDD = 1003 12290 Feature_HasFullFP16 | 0, // VADDH = 1004 12291 Feature_HasNEON | 0, // VADDHNv2i32 = 1005 12292 Feature_HasNEON | 0, // VADDHNv4i16 = 1006 12293 Feature_HasNEON | 0, // VADDHNv8i8 = 1007 12294 Feature_HasNEON | 0, // VADDLsv2i64 = 1008 12295 Feature_HasNEON | 0, // VADDLsv4i32 = 1009 12296 Feature_HasNEON | 0, // VADDLsv8i16 = 1010 12297 Feature_HasNEON | 0, // VADDLuv2i64 = 1011 12298 Feature_HasNEON | 0, // VADDLuv4i32 = 1012 12299 Feature_HasNEON | 0, // VADDLuv8i16 = 1013 12300 Feature_HasVFP2 | 0, // VADDS = 1014 12301 Feature_HasNEON | 0, // VADDWsv2i64 = 1015 12302 Feature_HasNEON | 0, // VADDWsv4i32 = 1016 12303 Feature_HasNEON | 0, // VADDWsv8i16 = 1017 12304 Feature_HasNEON | 0, // VADDWuv2i64 = 1018 12305 Feature_HasNEON | 0, // VADDWuv4i32 = 1019 12306 Feature_HasNEON | 0, // VADDWuv8i16 = 1020 12307 Feature_HasNEON | 0, // VADDfd = 1021 12308 Feature_HasNEON | 0, // VADDfq = 1022 12309 Feature_HasNEON | Feature_HasFullFP16 | 0, // VADDhd = 1023 12310 Feature_HasNEON | Feature_HasFullFP16 | 0, // VADDhq = 1024 12311 Feature_HasNEON | 0, // VADDv16i8 = 1025 12312 Feature_HasNEON | 0, // VADDv1i64 = 1026 12313 Feature_HasNEON | 0, // VADDv2i32 = 1027 12314 Feature_HasNEON | 0, // VADDv2i64 = 1028 12315 Feature_HasNEON | 0, // VADDv4i16 = 1029 12316 Feature_HasNEON | 0, // VADDv4i32 = 1030 12317 Feature_HasNEON | 0, // VADDv8i16 = 1031 12318 Feature_HasNEON | 0, // VADDv8i8 = 1032 12319 Feature_HasNEON | 0, // VANDd = 1033 12320 Feature_HasNEON | 0, // VANDq = 1034 12321 Feature_HasNEON | 0, // VBICd = 1035 12322 Feature_HasNEON | 0, // VBICiv2i32 = 1036 12323 Feature_HasNEON | 0, // VBICiv4i16 = 1037 12324 Feature_HasNEON | 0, // VBICiv4i32 = 1038 12325 Feature_HasNEON | 0, // VBICiv8i16 = 1039 12326 Feature_HasNEON | 0, // VBICq = 1040 12327 Feature_HasNEON | 0, // VBIFd = 1041 12328 Feature_HasNEON | 0, // VBIFq = 1042 12329 Feature_HasNEON | 0, // VBITd = 1043 12330 Feature_HasNEON | 0, // VBITq = 1044 12331 Feature_HasNEON | 0, // VBSLd = 1045 12332 Feature_HasNEON | 0, // VBSLq = 1046 12333 Feature_HasNEON | Feature_HasV8_3a | 0, // VCADDv2f32 = 1047 12334 Feature_HasNEON | Feature_HasV8_3a | Feature_HasFullFP16 | 0, // VCADDv4f16 = 1048 12335 Feature_HasNEON | Feature_HasV8_3a | 0, // VCADDv4f32 = 1049 12336 Feature_HasNEON | Feature_HasV8_3a | Feature_HasFullFP16 | 0, // VCADDv8f16 = 1050 12337 Feature_HasNEON | 0, // VCEQfd = 1051 12338 Feature_HasNEON | 0, // VCEQfq = 1052 12339 Feature_HasNEON | Feature_HasFullFP16 | 0, // VCEQhd = 1053 12340 Feature_HasNEON | Feature_HasFullFP16 | 0, // VCEQhq = 1054 12341 Feature_HasNEON | 0, // VCEQv16i8 = 1055 12342 Feature_HasNEON | 0, // VCEQv2i32 = 1056 12343 Feature_HasNEON | 0, // VCEQv4i16 = 1057 12344 Feature_HasNEON | 0, // VCEQv4i32 = 1058 12345 Feature_HasNEON | 0, // VCEQv8i16 = 1059 12346 Feature_HasNEON | 0, // VCEQv8i8 = 1060 12347 Feature_HasNEON | 0, // VCEQzv16i8 = 1061 12348 Feature_HasNEON | 0, // VCEQzv2f32 = 1062 12349 Feature_HasNEON | 0, // VCEQzv2i32 = 1063 12350 Feature_HasNEON | Feature_HasFullFP16 | 0, // VCEQzv4f16 = 1064 12351 Feature_HasNEON | 0, // VCEQzv4f32 = 1065 12352 Feature_HasNEON | 0, // VCEQzv4i16 = 1066 12353 Feature_HasNEON | 0, // VCEQzv4i32 = 1067 12354 Feature_HasNEON | Feature_HasFullFP16 | 0, // VCEQzv8f16 = 1068 12355 Feature_HasNEON | 0, // VCEQzv8i16 = 1069 12356 Feature_HasNEON | 0, // VCEQzv8i8 = 1070 12357 Feature_HasNEON | 0, // VCGEfd = 1071 12358 Feature_HasNEON | 0, // VCGEfq = 1072 12359 Feature_HasNEON | Feature_HasFullFP16 | 0, // VCGEhd = 1073 12360 Feature_HasNEON | Feature_HasFullFP16 | 0, // VCGEhq = 1074 12361 Feature_HasNEON | 0, // VCGEsv16i8 = 1075 12362 Feature_HasNEON | 0, // VCGEsv2i32 = 1076 12363 Feature_HasNEON | 0, // VCGEsv4i16 = 1077 12364 Feature_HasNEON | 0, // VCGEsv4i32 = 1078 12365 Feature_HasNEON | 0, // VCGEsv8i16 = 1079 12366 Feature_HasNEON | 0, // VCGEsv8i8 = 1080 12367 Feature_HasNEON | 0, // VCGEuv16i8 = 1081 12368 Feature_HasNEON | 0, // VCGEuv2i32 = 1082 12369 Feature_HasNEON | 0, // VCGEuv4i16 = 1083 12370 Feature_HasNEON | 0, // VCGEuv4i32 = 1084 12371 Feature_HasNEON | 0, // VCGEuv8i16 = 1085 12372 Feature_HasNEON | 0, // VCGEuv8i8 = 1086 12373 Feature_HasNEON | 0, // VCGEzv16i8 = 1087 12374 Feature_HasNEON | 0, // VCGEzv2f32 = 1088 12375 Feature_HasNEON | 0, // VCGEzv2i32 = 1089 12376 Feature_HasNEON | Feature_HasFullFP16 | 0, // VCGEzv4f16 = 1090 12377 Feature_HasNEON | 0, // VCGEzv4f32 = 1091 12378 Feature_HasNEON | 0, // VCGEzv4i16 = 1092 12379 Feature_HasNEON | 0, // VCGEzv4i32 = 1093 12380 Feature_HasNEON | Feature_HasFullFP16 | 0, // VCGEzv8f16 = 1094 12381 Feature_HasNEON | 0, // VCGEzv8i16 = 1095 12382 Feature_HasNEON | 0, // VCGEzv8i8 = 1096 12383 Feature_HasNEON | 0, // VCGTfd = 1097 12384 Feature_HasNEON | 0, // VCGTfq = 1098 12385 Feature_HasNEON | Feature_HasFullFP16 | 0, // VCGThd = 1099 12386 Feature_HasNEON | Feature_HasFullFP16 | 0, // VCGThq = 1100 12387 Feature_HasNEON | 0, // VCGTsv16i8 = 1101 12388 Feature_HasNEON | 0, // VCGTsv2i32 = 1102 12389 Feature_HasNEON | 0, // VCGTsv4i16 = 1103 12390 Feature_HasNEON | 0, // VCGTsv4i32 = 1104 12391 Feature_HasNEON | 0, // VCGTsv8i16 = 1105 12392 Feature_HasNEON | 0, // VCGTsv8i8 = 1106 12393 Feature_HasNEON | 0, // VCGTuv16i8 = 1107 12394 Feature_HasNEON | 0, // VCGTuv2i32 = 1108 12395 Feature_HasNEON | 0, // VCGTuv4i16 = 1109 12396 Feature_HasNEON | 0, // VCGTuv4i32 = 1110 12397 Feature_HasNEON | 0, // VCGTuv8i16 = 1111 12398 Feature_HasNEON | 0, // VCGTuv8i8 = 1112 12399 Feature_HasNEON | 0, // VCGTzv16i8 = 1113 12400 Feature_HasNEON | 0, // VCGTzv2f32 = 1114 12401 Feature_HasNEON | 0, // VCGTzv2i32 = 1115 12402 Feature_HasNEON | Feature_HasFullFP16 | 0, // VCGTzv4f16 = 1116 12403 Feature_HasNEON | 0, // VCGTzv4f32 = 1117 12404 Feature_HasNEON | 0, // VCGTzv4i16 = 1118 12405 Feature_HasNEON | 0, // VCGTzv4i32 = 1119 12406 Feature_HasNEON | Feature_HasFullFP16 | 0, // VCGTzv8f16 = 1120 12407 Feature_HasNEON | 0, // VCGTzv8i16 = 1121 12408 Feature_HasNEON | 0, // VCGTzv8i8 = 1122 12409 Feature_HasNEON | 0, // VCLEzv16i8 = 1123 12410 Feature_HasNEON | 0, // VCLEzv2f32 = 1124 12411 Feature_HasNEON | 0, // VCLEzv2i32 = 1125 12412 Feature_HasNEON | Feature_HasFullFP16 | 0, // VCLEzv4f16 = 1126 12413 Feature_HasNEON | 0, // VCLEzv4f32 = 1127 12414 Feature_HasNEON | 0, // VCLEzv4i16 = 1128 12415 Feature_HasNEON | 0, // VCLEzv4i32 = 1129 12416 Feature_HasNEON | Feature_HasFullFP16 | 0, // VCLEzv8f16 = 1130 12417 Feature_HasNEON | 0, // VCLEzv8i16 = 1131 12418 Feature_HasNEON | 0, // VCLEzv8i8 = 1132 12419 Feature_HasNEON | 0, // VCLSv16i8 = 1133 12420 Feature_HasNEON | 0, // VCLSv2i32 = 1134 12421 Feature_HasNEON | 0, // VCLSv4i16 = 1135 12422 Feature_HasNEON | 0, // VCLSv4i32 = 1136 12423 Feature_HasNEON | 0, // VCLSv8i16 = 1137 12424 Feature_HasNEON | 0, // VCLSv8i8 = 1138 12425 Feature_HasNEON | 0, // VCLTzv16i8 = 1139 12426 Feature_HasNEON | 0, // VCLTzv2f32 = 1140 12427 Feature_HasNEON | 0, // VCLTzv2i32 = 1141 12428 Feature_HasNEON | Feature_HasFullFP16 | 0, // VCLTzv4f16 = 1142 12429 Feature_HasNEON | 0, // VCLTzv4f32 = 1143 12430 Feature_HasNEON | 0, // VCLTzv4i16 = 1144 12431 Feature_HasNEON | 0, // VCLTzv4i32 = 1145 12432 Feature_HasNEON | Feature_HasFullFP16 | 0, // VCLTzv8f16 = 1146 12433 Feature_HasNEON | 0, // VCLTzv8i16 = 1147 12434 Feature_HasNEON | 0, // VCLTzv8i8 = 1148 12435 Feature_HasNEON | 0, // VCLZv16i8 = 1149 12436 Feature_HasNEON | 0, // VCLZv2i32 = 1150 12437 Feature_HasNEON | 0, // VCLZv4i16 = 1151 12438 Feature_HasNEON | 0, // VCLZv4i32 = 1152 12439 Feature_HasNEON | 0, // VCLZv8i16 = 1153 12440 Feature_HasNEON | 0, // VCLZv8i8 = 1154 12441 Feature_HasNEON | Feature_HasV8_3a | 0, // VCMLAv2f32 = 1155 12442 Feature_HasNEON | Feature_HasV8_3a | 0, // VCMLAv2f32_indexed = 1156 12443 Feature_HasNEON | Feature_HasV8_3a | Feature_HasFullFP16 | 0, // VCMLAv4f16 = 1157 12444 Feature_HasNEON | Feature_HasV8_3a | Feature_HasFullFP16 | 0, // VCMLAv4f16_indexed = 1158 12445 Feature_HasNEON | Feature_HasV8_3a | 0, // VCMLAv4f32 = 1159 12446 Feature_HasNEON | Feature_HasV8_3a | 0, // VCMLAv4f32_indexed = 1160 12447 Feature_HasNEON | Feature_HasV8_3a | Feature_HasFullFP16 | 0, // VCMLAv8f16 = 1161 12448 Feature_HasNEON | Feature_HasV8_3a | Feature_HasFullFP16 | 0, // VCMLAv8f16_indexed = 1162 12449 Feature_HasVFP2 | Feature_HasDPVFP | 0, // VCMPD = 1163 12450 Feature_HasVFP2 | Feature_HasDPVFP | 0, // VCMPED = 1164 12451 Feature_HasFullFP16 | 0, // VCMPEH = 1165 12452 Feature_HasVFP2 | 0, // VCMPES = 1166 12453 Feature_HasVFP2 | Feature_HasDPVFP | 0, // VCMPEZD = 1167 12454 Feature_HasFullFP16 | 0, // VCMPEZH = 1168 12455 Feature_HasVFP2 | 0, // VCMPEZS = 1169 12456 Feature_HasFullFP16 | 0, // VCMPH = 1170 12457 Feature_HasVFP2 | 0, // VCMPS = 1171 12458 Feature_HasVFP2 | Feature_HasDPVFP | 0, // VCMPZD = 1172 12459 Feature_HasFullFP16 | 0, // VCMPZH = 1173 12460 Feature_HasVFP2 | 0, // VCMPZS = 1174 12461 Feature_HasNEON | 0, // VCNTd = 1175 12462 Feature_HasNEON | 0, // VCNTq = 1176 12463 Feature_HasV8 | Feature_HasNEON | 0, // VCVTANSDf = 1177 12464 Feature_HasV8 | Feature_HasNEON | Feature_HasFullFP16 | 0, // VCVTANSDh = 1178 12465 Feature_HasV8 | Feature_HasNEON | 0, // VCVTANSQf = 1179 12466 Feature_HasV8 | Feature_HasNEON | Feature_HasFullFP16 | 0, // VCVTANSQh = 1180 12467 Feature_HasV8 | Feature_HasNEON | 0, // VCVTANUDf = 1181 12468 Feature_HasV8 | Feature_HasNEON | Feature_HasFullFP16 | 0, // VCVTANUDh = 1182 12469 Feature_HasV8 | Feature_HasNEON | 0, // VCVTANUQf = 1183 12470 Feature_HasV8 | Feature_HasNEON | Feature_HasFullFP16 | 0, // VCVTANUQh = 1184 12471 Feature_HasFPARMv8 | Feature_HasDPVFP | 0, // VCVTASD = 1185 12472 Feature_HasFullFP16 | 0, // VCVTASH = 1186 12473 Feature_HasFPARMv8 | 0, // VCVTASS = 1187 12474 Feature_HasFPARMv8 | Feature_HasDPVFP | 0, // VCVTAUD = 1188 12475 Feature_HasFullFP16 | 0, // VCVTAUH = 1189 12476 Feature_HasFPARMv8 | 0, // VCVTAUS = 1190 12477 Feature_HasFPARMv8 | Feature_HasDPVFP | 0, // VCVTBDH = 1191 12478 Feature_HasFPARMv8 | Feature_HasDPVFP | 0, // VCVTBHD = 1192 12479 Feature_HasFP16 | 0, // VCVTBHS = 1193 12480 Feature_HasFP16 | 0, // VCVTBSH = 1194 12481 Feature_HasVFP2 | Feature_HasDPVFP | 0, // VCVTDS = 1195 12482 Feature_HasV8 | Feature_HasNEON | 0, // VCVTMNSDf = 1196 12483 Feature_HasV8 | Feature_HasNEON | Feature_HasFullFP16 | 0, // VCVTMNSDh = 1197 12484 Feature_HasV8 | Feature_HasNEON | 0, // VCVTMNSQf = 1198 12485 Feature_HasV8 | Feature_HasNEON | Feature_HasFullFP16 | 0, // VCVTMNSQh = 1199 12486 Feature_HasV8 | Feature_HasNEON | 0, // VCVTMNUDf = 1200 12487 Feature_HasV8 | Feature_HasNEON | Feature_HasFullFP16 | 0, // VCVTMNUDh = 1201 12488 Feature_HasV8 | Feature_HasNEON | 0, // VCVTMNUQf = 1202 12489 Feature_HasV8 | Feature_HasNEON | Feature_HasFullFP16 | 0, // VCVTMNUQh = 1203 12490 Feature_HasFPARMv8 | Feature_HasDPVFP | 0, // VCVTMSD = 1204 12491 Feature_HasFullFP16 | 0, // VCVTMSH = 1205 12492 Feature_HasFPARMv8 | 0, // VCVTMSS = 1206 12493 Feature_HasFPARMv8 | Feature_HasDPVFP | 0, // VCVTMUD = 1207 12494 Feature_HasFullFP16 | 0, // VCVTMUH = 1208 12495 Feature_HasFPARMv8 | 0, // VCVTMUS = 1209 12496 Feature_HasV8 | Feature_HasNEON | 0, // VCVTNNSDf = 1210 12497 Feature_HasV8 | Feature_HasNEON | Feature_HasFullFP16 | 0, // VCVTNNSDh = 1211 12498 Feature_HasV8 | Feature_HasNEON | 0, // VCVTNNSQf = 1212 12499 Feature_HasV8 | Feature_HasNEON | Feature_HasFullFP16 | 0, // VCVTNNSQh = 1213 12500 Feature_HasV8 | Feature_HasNEON | 0, // VCVTNNUDf = 1214 12501 Feature_HasV8 | Feature_HasNEON | Feature_HasFullFP16 | 0, // VCVTNNUDh = 1215 12502 Feature_HasV8 | Feature_HasNEON | 0, // VCVTNNUQf = 1216 12503 Feature_HasV8 | Feature_HasNEON | Feature_HasFullFP16 | 0, // VCVTNNUQh = 1217 12504 Feature_HasFPARMv8 | Feature_HasDPVFP | 0, // VCVTNSD = 1218 12505 Feature_HasFullFP16 | 0, // VCVTNSH = 1219 12506 Feature_HasFPARMv8 | 0, // VCVTNSS = 1220 12507 Feature_HasFPARMv8 | Feature_HasDPVFP | 0, // VCVTNUD = 1221 12508 Feature_HasFullFP16 | 0, // VCVTNUH = 1222 12509 Feature_HasFPARMv8 | 0, // VCVTNUS = 1223 12510 Feature_HasV8 | Feature_HasNEON | 0, // VCVTPNSDf = 1224 12511 Feature_HasV8 | Feature_HasNEON | Feature_HasFullFP16 | 0, // VCVTPNSDh = 1225 12512 Feature_HasV8 | Feature_HasNEON | 0, // VCVTPNSQf = 1226 12513 Feature_HasV8 | Feature_HasNEON | Feature_HasFullFP16 | 0, // VCVTPNSQh = 1227 12514 Feature_HasV8 | Feature_HasNEON | 0, // VCVTPNUDf = 1228 12515 Feature_HasV8 | Feature_HasNEON | Feature_HasFullFP16 | 0, // VCVTPNUDh = 1229 12516 Feature_HasV8 | Feature_HasNEON | 0, // VCVTPNUQf = 1230 12517 Feature_HasV8 | Feature_HasNEON | Feature_HasFullFP16 | 0, // VCVTPNUQh = 1231 12518 Feature_HasFPARMv8 | Feature_HasDPVFP | 0, // VCVTPSD = 1232 12519 Feature_HasFullFP16 | 0, // VCVTPSH = 1233 12520 Feature_HasFPARMv8 | 0, // VCVTPSS = 1234 12521 Feature_HasFPARMv8 | Feature_HasDPVFP | 0, // VCVTPUD = 1235 12522 Feature_HasFullFP16 | 0, // VCVTPUH = 1236 12523 Feature_HasFPARMv8 | 0, // VCVTPUS = 1237 12524 Feature_HasVFP2 | Feature_HasDPVFP | 0, // VCVTSD = 1238 12525 Feature_HasFPARMv8 | Feature_HasDPVFP | 0, // VCVTTDH = 1239 12526 Feature_HasFPARMv8 | Feature_HasDPVFP | 0, // VCVTTHD = 1240 12527 Feature_HasFP16 | 0, // VCVTTHS = 1241 12528 Feature_HasFP16 | 0, // VCVTTSH = 1242 12529 Feature_HasNEON | Feature_HasFP16 | 0, // VCVTf2h = 1243 12530 Feature_HasNEON | 0, // VCVTf2sd = 1244 12531 Feature_HasNEON | 0, // VCVTf2sq = 1245 12532 Feature_HasNEON | 0, // VCVTf2ud = 1246 12533 Feature_HasNEON | 0, // VCVTf2uq = 1247 12534 Feature_HasNEON | 0, // VCVTf2xsd = 1248 12535 Feature_HasNEON | 0, // VCVTf2xsq = 1249 12536 Feature_HasNEON | 0, // VCVTf2xud = 1250 12537 Feature_HasNEON | 0, // VCVTf2xuq = 1251 12538 Feature_HasNEON | Feature_HasFP16 | 0, // VCVTh2f = 1252 12539 Feature_HasNEON | Feature_HasFullFP16 | 0, // VCVTh2sd = 1253 12540 Feature_HasNEON | Feature_HasFullFP16 | 0, // VCVTh2sq = 1254 12541 Feature_HasNEON | Feature_HasFullFP16 | 0, // VCVTh2ud = 1255 12542 Feature_HasNEON | Feature_HasFullFP16 | 0, // VCVTh2uq = 1256 12543 Feature_HasNEON | Feature_HasFullFP16 | 0, // VCVTh2xsd = 1257 12544 Feature_HasNEON | Feature_HasFullFP16 | 0, // VCVTh2xsq = 1258 12545 Feature_HasNEON | Feature_HasFullFP16 | 0, // VCVTh2xud = 1259 12546 Feature_HasNEON | Feature_HasFullFP16 | 0, // VCVTh2xuq = 1260 12547 Feature_HasNEON | 0, // VCVTs2fd = 1261 12548 Feature_HasNEON | 0, // VCVTs2fq = 1262 12549 Feature_HasNEON | Feature_HasFullFP16 | 0, // VCVTs2hd = 1263 12550 Feature_HasNEON | Feature_HasFullFP16 | 0, // VCVTs2hq = 1264 12551 Feature_HasNEON | 0, // VCVTu2fd = 1265 12552 Feature_HasNEON | 0, // VCVTu2fq = 1266 12553 Feature_HasNEON | Feature_HasFullFP16 | 0, // VCVTu2hd = 1267 12554 Feature_HasNEON | Feature_HasFullFP16 | 0, // VCVTu2hq = 1268 12555 Feature_HasNEON | 0, // VCVTxs2fd = 1269 12556 Feature_HasNEON | 0, // VCVTxs2fq = 1270 12557 Feature_HasNEON | Feature_HasFullFP16 | 0, // VCVTxs2hd = 1271 12558 Feature_HasNEON | Feature_HasFullFP16 | 0, // VCVTxs2hq = 1272 12559 Feature_HasNEON | 0, // VCVTxu2fd = 1273 12560 Feature_HasNEON | 0, // VCVTxu2fq = 1274 12561 Feature_HasNEON | Feature_HasFullFP16 | 0, // VCVTxu2hd = 1275 12562 Feature_HasNEON | Feature_HasFullFP16 | 0, // VCVTxu2hq = 1276 12563 Feature_HasVFP2 | Feature_HasDPVFP | 0, // VDIVD = 1277 12564 Feature_HasFullFP16 | 0, // VDIVH = 1278 12565 Feature_HasVFP2 | 0, // VDIVS = 1279 12566 Feature_HasNEON | 0, // VDUP16d = 1280 12567 Feature_HasNEON | 0, // VDUP16q = 1281 12568 Feature_HasNEON | 0, // VDUP32d = 1282 12569 Feature_HasNEON | 0, // VDUP32q = 1283 12570 Feature_HasNEON | 0, // VDUP8d = 1284 12571 Feature_HasNEON | 0, // VDUP8q = 1285 12572 Feature_HasNEON | 0, // VDUPLN16d = 1286 12573 Feature_HasNEON | 0, // VDUPLN16q = 1287 12574 Feature_HasNEON | 0, // VDUPLN32d = 1288 12575 Feature_HasNEON | 0, // VDUPLN32q = 1289 12576 Feature_HasNEON | 0, // VDUPLN8d = 1290 12577 Feature_HasNEON | 0, // VDUPLN8q = 1291 12578 Feature_HasNEON | 0, // VEORd = 1292 12579 Feature_HasNEON | 0, // VEORq = 1293 12580 Feature_HasNEON | 0, // VEXTd16 = 1294 12581 Feature_HasNEON | 0, // VEXTd32 = 1295 12582 Feature_HasNEON | 0, // VEXTd8 = 1296 12583 Feature_HasNEON | 0, // VEXTq16 = 1297 12584 Feature_HasNEON | 0, // VEXTq32 = 1298 12585 Feature_HasNEON | 0, // VEXTq64 = 1299 12586 Feature_HasNEON | 0, // VEXTq8 = 1300 12587 Feature_HasVFP4 | Feature_HasDPVFP | 0, // VFMAD = 1301 12588 Feature_HasFullFP16 | 0, // VFMAH = 1302 12589 Feature_HasVFP4 | 0, // VFMAS = 1303 12590 Feature_HasNEON | Feature_HasVFP4 | 0, // VFMAfd = 1304 12591 Feature_HasNEON | Feature_HasVFP4 | 0, // VFMAfq = 1305 12592 Feature_HasNEON | Feature_HasFullFP16 | 0, // VFMAhd = 1306 12593 Feature_HasNEON | Feature_HasFullFP16 | 0, // VFMAhq = 1307 12594 Feature_HasVFP4 | Feature_HasDPVFP | 0, // VFMSD = 1308 12595 Feature_HasFullFP16 | 0, // VFMSH = 1309 12596 Feature_HasVFP4 | 0, // VFMSS = 1310 12597 Feature_HasNEON | Feature_HasVFP4 | 0, // VFMSfd = 1311 12598 Feature_HasNEON | Feature_HasVFP4 | 0, // VFMSfq = 1312 12599 Feature_HasNEON | Feature_HasFullFP16 | 0, // VFMShd = 1313 12600 Feature_HasNEON | Feature_HasFullFP16 | 0, // VFMShq = 1314 12601 Feature_HasVFP4 | Feature_HasDPVFP | 0, // VFNMAD = 1315 12602 Feature_HasFullFP16 | 0, // VFNMAH = 1316 12603 Feature_HasVFP4 | 0, // VFNMAS = 1317 12604 Feature_HasVFP4 | Feature_HasDPVFP | 0, // VFNMSD = 1318 12605 Feature_HasFullFP16 | 0, // VFNMSH = 1319 12606 Feature_HasVFP4 | 0, // VFNMSS = 1320 12607 Feature_HasVFP2 | 0, // VGETLNi32 = 1321 12608 Feature_HasNEON | 0, // VGETLNs16 = 1322 12609 Feature_HasNEON | 0, // VGETLNs8 = 1323 12610 Feature_HasNEON | 0, // VGETLNu16 = 1324 12611 Feature_HasNEON | 0, // VGETLNu8 = 1325 12612 Feature_HasNEON | 0, // VHADDsv16i8 = 1326 12613 Feature_HasNEON | 0, // VHADDsv2i32 = 1327 12614 Feature_HasNEON | 0, // VHADDsv4i16 = 1328 12615 Feature_HasNEON | 0, // VHADDsv4i32 = 1329 12616 Feature_HasNEON | 0, // VHADDsv8i16 = 1330 12617 Feature_HasNEON | 0, // VHADDsv8i8 = 1331 12618 Feature_HasNEON | 0, // VHADDuv16i8 = 1332 12619 Feature_HasNEON | 0, // VHADDuv2i32 = 1333 12620 Feature_HasNEON | 0, // VHADDuv4i16 = 1334 12621 Feature_HasNEON | 0, // VHADDuv4i32 = 1335 12622 Feature_HasNEON | 0, // VHADDuv8i16 = 1336 12623 Feature_HasNEON | 0, // VHADDuv8i8 = 1337 12624 Feature_HasNEON | 0, // VHSUBsv16i8 = 1338 12625 Feature_HasNEON | 0, // VHSUBsv2i32 = 1339 12626 Feature_HasNEON | 0, // VHSUBsv4i16 = 1340 12627 Feature_HasNEON | 0, // VHSUBsv4i32 = 1341 12628 Feature_HasNEON | 0, // VHSUBsv8i16 = 1342 12629 Feature_HasNEON | 0, // VHSUBsv8i8 = 1343 12630 Feature_HasNEON | 0, // VHSUBuv16i8 = 1344 12631 Feature_HasNEON | 0, // VHSUBuv2i32 = 1345 12632 Feature_HasNEON | 0, // VHSUBuv4i16 = 1346 12633 Feature_HasNEON | 0, // VHSUBuv4i32 = 1347 12634 Feature_HasNEON | 0, // VHSUBuv8i16 = 1348 12635 Feature_HasNEON | 0, // VHSUBuv8i8 = 1349 12636 Feature_HasFullFP16 | 0, // VINSH = 1350 12637 Feature_HasFPARMv8 | Feature_HasV8_3a | 0, // VJCVT = 1351 12638 Feature_HasNEON | 0, // VLD1DUPd16 = 1352 12639 Feature_HasNEON | 0, // VLD1DUPd16wb_fixed = 1353 12640 Feature_HasNEON | 0, // VLD1DUPd16wb_register = 1354 12641 Feature_HasNEON | 0, // VLD1DUPd32 = 1355 12642 Feature_HasNEON | 0, // VLD1DUPd32wb_fixed = 1356 12643 Feature_HasNEON | 0, // VLD1DUPd32wb_register = 1357 12644 Feature_HasNEON | 0, // VLD1DUPd8 = 1358 12645 Feature_HasNEON | 0, // VLD1DUPd8wb_fixed = 1359 12646 Feature_HasNEON | 0, // VLD1DUPd8wb_register = 1360 12647 Feature_HasNEON | 0, // VLD1DUPq16 = 1361 12648 Feature_HasNEON | 0, // VLD1DUPq16wb_fixed = 1362 12649 Feature_HasNEON | 0, // VLD1DUPq16wb_register = 1363 12650 Feature_HasNEON | 0, // VLD1DUPq32 = 1364 12651 Feature_HasNEON | 0, // VLD1DUPq32wb_fixed = 1365 12652 Feature_HasNEON | 0, // VLD1DUPq32wb_register = 1366 12653 Feature_HasNEON | 0, // VLD1DUPq8 = 1367 12654 Feature_HasNEON | 0, // VLD1DUPq8wb_fixed = 1368 12655 Feature_HasNEON | 0, // VLD1DUPq8wb_register = 1369 12656 Feature_HasNEON | 0, // VLD1LNd16 = 1370 12657 Feature_HasNEON | 0, // VLD1LNd16_UPD = 1371 12658 Feature_HasNEON | 0, // VLD1LNd32 = 1372 12659 Feature_HasNEON | 0, // VLD1LNd32_UPD = 1373 12660 Feature_HasNEON | 0, // VLD1LNd8 = 1374 12661 Feature_HasNEON | 0, // VLD1LNd8_UPD = 1375 12662 Feature_HasNEON | 0, // VLD1LNq16Pseudo = 1376 12663 Feature_HasNEON | 0, // VLD1LNq16Pseudo_UPD = 1377 12664 Feature_HasNEON | 0, // VLD1LNq32Pseudo = 1378 12665 Feature_HasNEON | 0, // VLD1LNq32Pseudo_UPD = 1379 12666 Feature_HasNEON | 0, // VLD1LNq8Pseudo = 1380 12667 Feature_HasNEON | 0, // VLD1LNq8Pseudo_UPD = 1381 12668 Feature_HasNEON | 0, // VLD1d16 = 1382 12669 Feature_HasNEON | 0, // VLD1d16Q = 1383 12670 Feature_HasNEON | 0, // VLD1d16QPseudo = 1384 12671 Feature_HasNEON | 0, // VLD1d16Qwb_fixed = 1385 12672 Feature_HasNEON | 0, // VLD1d16Qwb_register = 1386 12673 Feature_HasNEON | 0, // VLD1d16T = 1387 12674 Feature_HasNEON | 0, // VLD1d16TPseudo = 1388 12675 Feature_HasNEON | 0, // VLD1d16Twb_fixed = 1389 12676 Feature_HasNEON | 0, // VLD1d16Twb_register = 1390 12677 Feature_HasNEON | 0, // VLD1d16wb_fixed = 1391 12678 Feature_HasNEON | 0, // VLD1d16wb_register = 1392 12679 Feature_HasNEON | 0, // VLD1d32 = 1393 12680 Feature_HasNEON | 0, // VLD1d32Q = 1394 12681 Feature_HasNEON | 0, // VLD1d32QPseudo = 1395 12682 Feature_HasNEON | 0, // VLD1d32Qwb_fixed = 1396 12683 Feature_HasNEON | 0, // VLD1d32Qwb_register = 1397 12684 Feature_HasNEON | 0, // VLD1d32T = 1398 12685 Feature_HasNEON | 0, // VLD1d32TPseudo = 1399 12686 Feature_HasNEON | 0, // VLD1d32Twb_fixed = 1400 12687 Feature_HasNEON | 0, // VLD1d32Twb_register = 1401 12688 Feature_HasNEON | 0, // VLD1d32wb_fixed = 1402 12689 Feature_HasNEON | 0, // VLD1d32wb_register = 1403 12690 Feature_HasNEON | 0, // VLD1d64 = 1404 12691 Feature_HasNEON | 0, // VLD1d64Q = 1405 12692 Feature_HasNEON | 0, // VLD1d64QPseudo = 1406 12693 Feature_HasNEON | 0, // VLD1d64QPseudoWB_fixed = 1407 12694 Feature_HasNEON | 0, // VLD1d64QPseudoWB_register = 1408 12695 Feature_HasNEON | 0, // VLD1d64Qwb_fixed = 1409 12696 Feature_HasNEON | 0, // VLD1d64Qwb_register = 1410 12697 Feature_HasNEON | 0, // VLD1d64T = 1411 12698 Feature_HasNEON | 0, // VLD1d64TPseudo = 1412 12699 Feature_HasNEON | 0, // VLD1d64TPseudoWB_fixed = 1413 12700 Feature_HasNEON | 0, // VLD1d64TPseudoWB_register = 1414 12701 Feature_HasNEON | 0, // VLD1d64Twb_fixed = 1415 12702 Feature_HasNEON | 0, // VLD1d64Twb_register = 1416 12703 Feature_HasNEON | 0, // VLD1d64wb_fixed = 1417 12704 Feature_HasNEON | 0, // VLD1d64wb_register = 1418 12705 Feature_HasNEON | 0, // VLD1d8 = 1419 12706 Feature_HasNEON | 0, // VLD1d8Q = 1420 12707 Feature_HasNEON | 0, // VLD1d8QPseudo = 1421 12708 Feature_HasNEON | 0, // VLD1d8Qwb_fixed = 1422 12709 Feature_HasNEON | 0, // VLD1d8Qwb_register = 1423 12710 Feature_HasNEON | 0, // VLD1d8T = 1424 12711 Feature_HasNEON | 0, // VLD1d8TPseudo = 1425 12712 Feature_HasNEON | 0, // VLD1d8Twb_fixed = 1426 12713 Feature_HasNEON | 0, // VLD1d8Twb_register = 1427 12714 Feature_HasNEON | 0, // VLD1d8wb_fixed = 1428 12715 Feature_HasNEON | 0, // VLD1d8wb_register = 1429 12716 Feature_HasNEON | 0, // VLD1q16 = 1430 12717 Feature_HasNEON | 0, // VLD1q16HighQPseudo = 1431 12718 Feature_HasNEON | 0, // VLD1q16HighTPseudo = 1432 12719 Feature_HasNEON | 0, // VLD1q16LowQPseudo_UPD = 1433 12720 Feature_HasNEON | 0, // VLD1q16LowTPseudo_UPD = 1434 12721 Feature_HasNEON | 0, // VLD1q16wb_fixed = 1435 12722 Feature_HasNEON | 0, // VLD1q16wb_register = 1436 12723 Feature_HasNEON | 0, // VLD1q32 = 1437 12724 Feature_HasNEON | 0, // VLD1q32HighQPseudo = 1438 12725 Feature_HasNEON | 0, // VLD1q32HighTPseudo = 1439 12726 Feature_HasNEON | 0, // VLD1q32LowQPseudo_UPD = 1440 12727 Feature_HasNEON | 0, // VLD1q32LowTPseudo_UPD = 1441 12728 Feature_HasNEON | 0, // VLD1q32wb_fixed = 1442 12729 Feature_HasNEON | 0, // VLD1q32wb_register = 1443 12730 Feature_HasNEON | 0, // VLD1q64 = 1444 12731 Feature_HasNEON | 0, // VLD1q64HighQPseudo = 1445 12732 Feature_HasNEON | 0, // VLD1q64HighTPseudo = 1446 12733 Feature_HasNEON | 0, // VLD1q64LowQPseudo_UPD = 1447 12734 Feature_HasNEON | 0, // VLD1q64LowTPseudo_UPD = 1448 12735 Feature_HasNEON | 0, // VLD1q64wb_fixed = 1449 12736 Feature_HasNEON | 0, // VLD1q64wb_register = 1450 12737 Feature_HasNEON | 0, // VLD1q8 = 1451 12738 Feature_HasNEON | 0, // VLD1q8HighQPseudo = 1452 12739 Feature_HasNEON | 0, // VLD1q8HighTPseudo = 1453 12740 Feature_HasNEON | 0, // VLD1q8LowQPseudo_UPD = 1454 12741 Feature_HasNEON | 0, // VLD1q8LowTPseudo_UPD = 1455 12742 Feature_HasNEON | 0, // VLD1q8wb_fixed = 1456 12743 Feature_HasNEON | 0, // VLD1q8wb_register = 1457 12744 Feature_HasNEON | 0, // VLD2DUPd16 = 1458 12745 Feature_HasNEON | 0, // VLD2DUPd16wb_fixed = 1459 12746 Feature_HasNEON | 0, // VLD2DUPd16wb_register = 1460 12747 Feature_HasNEON | 0, // VLD2DUPd16x2 = 1461 12748 Feature_HasNEON | 0, // VLD2DUPd16x2wb_fixed = 1462 12749 Feature_HasNEON | 0, // VLD2DUPd16x2wb_register = 1463 12750 Feature_HasNEON | 0, // VLD2DUPd32 = 1464 12751 Feature_HasNEON | 0, // VLD2DUPd32wb_fixed = 1465 12752 Feature_HasNEON | 0, // VLD2DUPd32wb_register = 1466 12753 Feature_HasNEON | 0, // VLD2DUPd32x2 = 1467 12754 Feature_HasNEON | 0, // VLD2DUPd32x2wb_fixed = 1468 12755 Feature_HasNEON | 0, // VLD2DUPd32x2wb_register = 1469 12756 Feature_HasNEON | 0, // VLD2DUPd8 = 1470 12757 Feature_HasNEON | 0, // VLD2DUPd8wb_fixed = 1471 12758 Feature_HasNEON | 0, // VLD2DUPd8wb_register = 1472 12759 Feature_HasNEON | 0, // VLD2DUPd8x2 = 1473 12760 Feature_HasNEON | 0, // VLD2DUPd8x2wb_fixed = 1474 12761 Feature_HasNEON | 0, // VLD2DUPd8x2wb_register = 1475 12762 Feature_HasNEON | 0, // VLD2DUPq16EvenPseudo = 1476 12763 Feature_HasNEON | 0, // VLD2DUPq16OddPseudo = 1477 12764 Feature_HasNEON | 0, // VLD2DUPq32EvenPseudo = 1478 12765 Feature_HasNEON | 0, // VLD2DUPq32OddPseudo = 1479 12766 Feature_HasNEON | 0, // VLD2DUPq8EvenPseudo = 1480 12767 Feature_HasNEON | 0, // VLD2DUPq8OddPseudo = 1481 12768 Feature_HasNEON | 0, // VLD2LNd16 = 1482 12769 Feature_HasNEON | 0, // VLD2LNd16Pseudo = 1483 12770 Feature_HasNEON | 0, // VLD2LNd16Pseudo_UPD = 1484 12771 Feature_HasNEON | 0, // VLD2LNd16_UPD = 1485 12772 Feature_HasNEON | 0, // VLD2LNd32 = 1486 12773 Feature_HasNEON | 0, // VLD2LNd32Pseudo = 1487 12774 Feature_HasNEON | 0, // VLD2LNd32Pseudo_UPD = 1488 12775 Feature_HasNEON | 0, // VLD2LNd32_UPD = 1489 12776 Feature_HasNEON | 0, // VLD2LNd8 = 1490 12777 Feature_HasNEON | 0, // VLD2LNd8Pseudo = 1491 12778 Feature_HasNEON | 0, // VLD2LNd8Pseudo_UPD = 1492 12779 Feature_HasNEON | 0, // VLD2LNd8_UPD = 1493 12780 Feature_HasNEON | 0, // VLD2LNq16 = 1494 12781 Feature_HasNEON | 0, // VLD2LNq16Pseudo = 1495 12782 Feature_HasNEON | 0, // VLD2LNq16Pseudo_UPD = 1496 12783 Feature_HasNEON | 0, // VLD2LNq16_UPD = 1497 12784 Feature_HasNEON | 0, // VLD2LNq32 = 1498 12785 Feature_HasNEON | 0, // VLD2LNq32Pseudo = 1499 12786 Feature_HasNEON | 0, // VLD2LNq32Pseudo_UPD = 1500 12787 Feature_HasNEON | 0, // VLD2LNq32_UPD = 1501 12788 Feature_HasNEON | 0, // VLD2b16 = 1502 12789 Feature_HasNEON | 0, // VLD2b16wb_fixed = 1503 12790 Feature_HasNEON | 0, // VLD2b16wb_register = 1504 12791 Feature_HasNEON | 0, // VLD2b32 = 1505 12792 Feature_HasNEON | 0, // VLD2b32wb_fixed = 1506 12793 Feature_HasNEON | 0, // VLD2b32wb_register = 1507 12794 Feature_HasNEON | 0, // VLD2b8 = 1508 12795 Feature_HasNEON | 0, // VLD2b8wb_fixed = 1509 12796 Feature_HasNEON | 0, // VLD2b8wb_register = 1510 12797 Feature_HasNEON | 0, // VLD2d16 = 1511 12798 Feature_HasNEON | 0, // VLD2d16wb_fixed = 1512 12799 Feature_HasNEON | 0, // VLD2d16wb_register = 1513 12800 Feature_HasNEON | 0, // VLD2d32 = 1514 12801 Feature_HasNEON | 0, // VLD2d32wb_fixed = 1515 12802 Feature_HasNEON | 0, // VLD2d32wb_register = 1516 12803 Feature_HasNEON | 0, // VLD2d8 = 1517 12804 Feature_HasNEON | 0, // VLD2d8wb_fixed = 1518 12805 Feature_HasNEON | 0, // VLD2d8wb_register = 1519 12806 Feature_HasNEON | 0, // VLD2q16 = 1520 12807 Feature_HasNEON | 0, // VLD2q16Pseudo = 1521 12808 Feature_HasNEON | 0, // VLD2q16PseudoWB_fixed = 1522 12809 Feature_HasNEON | 0, // VLD2q16PseudoWB_register = 1523 12810 Feature_HasNEON | 0, // VLD2q16wb_fixed = 1524 12811 Feature_HasNEON | 0, // VLD2q16wb_register = 1525 12812 Feature_HasNEON | 0, // VLD2q32 = 1526 12813 Feature_HasNEON | 0, // VLD2q32Pseudo = 1527 12814 Feature_HasNEON | 0, // VLD2q32PseudoWB_fixed = 1528 12815 Feature_HasNEON | 0, // VLD2q32PseudoWB_register = 1529 12816 Feature_HasNEON | 0, // VLD2q32wb_fixed = 1530 12817 Feature_HasNEON | 0, // VLD2q32wb_register = 1531 12818 Feature_HasNEON | 0, // VLD2q8 = 1532 12819 Feature_HasNEON | 0, // VLD2q8Pseudo = 1533 12820 Feature_HasNEON | 0, // VLD2q8PseudoWB_fixed = 1534 12821 Feature_HasNEON | 0, // VLD2q8PseudoWB_register = 1535 12822 Feature_HasNEON | 0, // VLD2q8wb_fixed = 1536 12823 Feature_HasNEON | 0, // VLD2q8wb_register = 1537 12824 Feature_HasNEON | 0, // VLD3DUPd16 = 1538 12825 Feature_HasNEON | 0, // VLD3DUPd16Pseudo = 1539 12826 Feature_HasNEON | 0, // VLD3DUPd16Pseudo_UPD = 1540 12827 Feature_HasNEON | 0, // VLD3DUPd16_UPD = 1541 12828 Feature_HasNEON | 0, // VLD3DUPd32 = 1542 12829 Feature_HasNEON | 0, // VLD3DUPd32Pseudo = 1543 12830 Feature_HasNEON | 0, // VLD3DUPd32Pseudo_UPD = 1544 12831 Feature_HasNEON | 0, // VLD3DUPd32_UPD = 1545 12832 Feature_HasNEON | 0, // VLD3DUPd8 = 1546 12833 Feature_HasNEON | 0, // VLD3DUPd8Pseudo = 1547 12834 Feature_HasNEON | 0, // VLD3DUPd8Pseudo_UPD = 1548 12835 Feature_HasNEON | 0, // VLD3DUPd8_UPD = 1549 12836 Feature_HasNEON | 0, // VLD3DUPq16 = 1550 12837 Feature_HasNEON | 0, // VLD3DUPq16EvenPseudo = 1551 12838 Feature_HasNEON | 0, // VLD3DUPq16OddPseudo = 1552 12839 Feature_HasNEON | 0, // VLD3DUPq16_UPD = 1553 12840 Feature_HasNEON | 0, // VLD3DUPq32 = 1554 12841 Feature_HasNEON | 0, // VLD3DUPq32EvenPseudo = 1555 12842 Feature_HasNEON | 0, // VLD3DUPq32OddPseudo = 1556 12843 Feature_HasNEON | 0, // VLD3DUPq32_UPD = 1557 12844 Feature_HasNEON | 0, // VLD3DUPq8 = 1558 12845 Feature_HasNEON | 0, // VLD3DUPq8EvenPseudo = 1559 12846 Feature_HasNEON | 0, // VLD3DUPq8OddPseudo = 1560 12847 Feature_HasNEON | 0, // VLD3DUPq8_UPD = 1561 12848 Feature_HasNEON | 0, // VLD3LNd16 = 1562 12849 Feature_HasNEON | 0, // VLD3LNd16Pseudo = 1563 12850 Feature_HasNEON | 0, // VLD3LNd16Pseudo_UPD = 1564 12851 Feature_HasNEON | 0, // VLD3LNd16_UPD = 1565 12852 Feature_HasNEON | 0, // VLD3LNd32 = 1566 12853 Feature_HasNEON | 0, // VLD3LNd32Pseudo = 1567 12854 Feature_HasNEON | 0, // VLD3LNd32Pseudo_UPD = 1568 12855 Feature_HasNEON | 0, // VLD3LNd32_UPD = 1569 12856 Feature_HasNEON | 0, // VLD3LNd8 = 1570 12857 Feature_HasNEON | 0, // VLD3LNd8Pseudo = 1571 12858 Feature_HasNEON | 0, // VLD3LNd8Pseudo_UPD = 1572 12859 Feature_HasNEON | 0, // VLD3LNd8_UPD = 1573 12860 Feature_HasNEON | 0, // VLD3LNq16 = 1574 12861 Feature_HasNEON | 0, // VLD3LNq16Pseudo = 1575 12862 Feature_HasNEON | 0, // VLD3LNq16Pseudo_UPD = 1576 12863 Feature_HasNEON | 0, // VLD3LNq16_UPD = 1577 12864 Feature_HasNEON | 0, // VLD3LNq32 = 1578 12865 Feature_HasNEON | 0, // VLD3LNq32Pseudo = 1579 12866 Feature_HasNEON | 0, // VLD3LNq32Pseudo_UPD = 1580 12867 Feature_HasNEON | 0, // VLD3LNq32_UPD = 1581 12868 Feature_HasNEON | 0, // VLD3d16 = 1582 12869 Feature_HasNEON | 0, // VLD3d16Pseudo = 1583 12870 Feature_HasNEON | 0, // VLD3d16Pseudo_UPD = 1584 12871 Feature_HasNEON | 0, // VLD3d16_UPD = 1585 12872 Feature_HasNEON | 0, // VLD3d32 = 1586 12873 Feature_HasNEON | 0, // VLD3d32Pseudo = 1587 12874 Feature_HasNEON | 0, // VLD3d32Pseudo_UPD = 1588 12875 Feature_HasNEON | 0, // VLD3d32_UPD = 1589 12876 Feature_HasNEON | 0, // VLD3d8 = 1590 12877 Feature_HasNEON | 0, // VLD3d8Pseudo = 1591 12878 Feature_HasNEON | 0, // VLD3d8Pseudo_UPD = 1592 12879 Feature_HasNEON | 0, // VLD3d8_UPD = 1593 12880 Feature_HasNEON | 0, // VLD3q16 = 1594 12881 Feature_HasNEON | 0, // VLD3q16Pseudo_UPD = 1595 12882 Feature_HasNEON | 0, // VLD3q16_UPD = 1596 12883 Feature_HasNEON | 0, // VLD3q16oddPseudo = 1597 12884 Feature_HasNEON | 0, // VLD3q16oddPseudo_UPD = 1598 12885 Feature_HasNEON | 0, // VLD3q32 = 1599 12886 Feature_HasNEON | 0, // VLD3q32Pseudo_UPD = 1600 12887 Feature_HasNEON | 0, // VLD3q32_UPD = 1601 12888 Feature_HasNEON | 0, // VLD3q32oddPseudo = 1602 12889 Feature_HasNEON | 0, // VLD3q32oddPseudo_UPD = 1603 12890 Feature_HasNEON | 0, // VLD3q8 = 1604 12891 Feature_HasNEON | 0, // VLD3q8Pseudo_UPD = 1605 12892 Feature_HasNEON | 0, // VLD3q8_UPD = 1606 12893 Feature_HasNEON | 0, // VLD3q8oddPseudo = 1607 12894 Feature_HasNEON | 0, // VLD3q8oddPseudo_UPD = 1608 12895 Feature_HasNEON | 0, // VLD4DUPd16 = 1609 12896 Feature_HasNEON | 0, // VLD4DUPd16Pseudo = 1610 12897 Feature_HasNEON | 0, // VLD4DUPd16Pseudo_UPD = 1611 12898 Feature_HasNEON | 0, // VLD4DUPd16_UPD = 1612 12899 Feature_HasNEON | 0, // VLD4DUPd32 = 1613 12900 Feature_HasNEON | 0, // VLD4DUPd32Pseudo = 1614 12901 Feature_HasNEON | 0, // VLD4DUPd32Pseudo_UPD = 1615 12902 Feature_HasNEON | 0, // VLD4DUPd32_UPD = 1616 12903 Feature_HasNEON | 0, // VLD4DUPd8 = 1617 12904 Feature_HasNEON | 0, // VLD4DUPd8Pseudo = 1618 12905 Feature_HasNEON | 0, // VLD4DUPd8Pseudo_UPD = 1619 12906 Feature_HasNEON | 0, // VLD4DUPd8_UPD = 1620 12907 Feature_HasNEON | 0, // VLD4DUPq16 = 1621 12908 Feature_HasNEON | 0, // VLD4DUPq16EvenPseudo = 1622 12909 Feature_HasNEON | 0, // VLD4DUPq16OddPseudo = 1623 12910 Feature_HasNEON | 0, // VLD4DUPq16_UPD = 1624 12911 Feature_HasNEON | 0, // VLD4DUPq32 = 1625 12912 Feature_HasNEON | 0, // VLD4DUPq32EvenPseudo = 1626 12913 Feature_HasNEON | 0, // VLD4DUPq32OddPseudo = 1627 12914 Feature_HasNEON | 0, // VLD4DUPq32_UPD = 1628 12915 Feature_HasNEON | 0, // VLD4DUPq8 = 1629 12916 Feature_HasNEON | 0, // VLD4DUPq8EvenPseudo = 1630 12917 Feature_HasNEON | 0, // VLD4DUPq8OddPseudo = 1631 12918 Feature_HasNEON | 0, // VLD4DUPq8_UPD = 1632 12919 Feature_HasNEON | 0, // VLD4LNd16 = 1633 12920 Feature_HasNEON | 0, // VLD4LNd16Pseudo = 1634 12921 Feature_HasNEON | 0, // VLD4LNd16Pseudo_UPD = 1635 12922 Feature_HasNEON | 0, // VLD4LNd16_UPD = 1636 12923 Feature_HasNEON | 0, // VLD4LNd32 = 1637 12924 Feature_HasNEON | 0, // VLD4LNd32Pseudo = 1638 12925 Feature_HasNEON | 0, // VLD4LNd32Pseudo_UPD = 1639 12926 Feature_HasNEON | 0, // VLD4LNd32_UPD = 1640 12927 Feature_HasNEON | 0, // VLD4LNd8 = 1641 12928 Feature_HasNEON | 0, // VLD4LNd8Pseudo = 1642 12929 Feature_HasNEON | 0, // VLD4LNd8Pseudo_UPD = 1643 12930 Feature_HasNEON | 0, // VLD4LNd8_UPD = 1644 12931 Feature_HasNEON | 0, // VLD4LNq16 = 1645 12932 Feature_HasNEON | 0, // VLD4LNq16Pseudo = 1646 12933 Feature_HasNEON | 0, // VLD4LNq16Pseudo_UPD = 1647 12934 Feature_HasNEON | 0, // VLD4LNq16_UPD = 1648 12935 Feature_HasNEON | 0, // VLD4LNq32 = 1649 12936 Feature_HasNEON | 0, // VLD4LNq32Pseudo = 1650 12937 Feature_HasNEON | 0, // VLD4LNq32Pseudo_UPD = 1651 12938 Feature_HasNEON | 0, // VLD4LNq32_UPD = 1652 12939 Feature_HasNEON | 0, // VLD4d16 = 1653 12940 Feature_HasNEON | 0, // VLD4d16Pseudo = 1654 12941 Feature_HasNEON | 0, // VLD4d16Pseudo_UPD = 1655 12942 Feature_HasNEON | 0, // VLD4d16_UPD = 1656 12943 Feature_HasNEON | 0, // VLD4d32 = 1657 12944 Feature_HasNEON | 0, // VLD4d32Pseudo = 1658 12945 Feature_HasNEON | 0, // VLD4d32Pseudo_UPD = 1659 12946 Feature_HasNEON | 0, // VLD4d32_UPD = 1660 12947 Feature_HasNEON | 0, // VLD4d8 = 1661 12948 Feature_HasNEON | 0, // VLD4d8Pseudo = 1662 12949 Feature_HasNEON | 0, // VLD4d8Pseudo_UPD = 1663 12950 Feature_HasNEON | 0, // VLD4d8_UPD = 1664 12951 Feature_HasNEON | 0, // VLD4q16 = 1665 12952 Feature_HasNEON | 0, // VLD4q16Pseudo_UPD = 1666 12953 Feature_HasNEON | 0, // VLD4q16_UPD = 1667 12954 Feature_HasNEON | 0, // VLD4q16oddPseudo = 1668 12955 Feature_HasNEON | 0, // VLD4q16oddPseudo_UPD = 1669 12956 Feature_HasNEON | 0, // VLD4q32 = 1670 12957 Feature_HasNEON | 0, // VLD4q32Pseudo_UPD = 1671 12958 Feature_HasNEON | 0, // VLD4q32_UPD = 1672 12959 Feature_HasNEON | 0, // VLD4q32oddPseudo = 1673 12960 Feature_HasNEON | 0, // VLD4q32oddPseudo_UPD = 1674 12961 Feature_HasNEON | 0, // VLD4q8 = 1675 12962 Feature_HasNEON | 0, // VLD4q8Pseudo_UPD = 1676 12963 Feature_HasNEON | 0, // VLD4q8_UPD = 1677 12964 Feature_HasNEON | 0, // VLD4q8oddPseudo = 1678 12965 Feature_HasNEON | 0, // VLD4q8oddPseudo_UPD = 1679 12966 Feature_HasVFP2 | 0, // VLDMDDB_UPD = 1680 12967 Feature_HasVFP2 | 0, // VLDMDIA = 1681 12968 Feature_HasVFP2 | 0, // VLDMDIA_UPD = 1682 12969 Feature_HasVFP2 | 0, // VLDMQIA = 1683 12970 Feature_HasVFP2 | 0, // VLDMSDB_UPD = 1684 12971 Feature_HasVFP2 | 0, // VLDMSIA = 1685 12972 Feature_HasVFP2 | 0, // VLDMSIA_UPD = 1686 12973 Feature_HasVFP2 | 0, // VLDRD = 1687 12974 Feature_HasFullFP16 | 0, // VLDRH = 1688 12975 Feature_HasVFP2 | 0, // VLDRS = 1689 12976 Feature_HasV8MMainline | Feature_Has8MSecExt | 0, // VLLDM = 1690 12977 Feature_HasV8MMainline | Feature_Has8MSecExt | 0, // VLSTM = 1691 12978 Feature_HasFPARMv8 | Feature_HasDPVFP | 0, // VMAXNMD = 1692 12979 Feature_HasFullFP16 | 0, // VMAXNMH = 1693 12980 Feature_HasV8 | Feature_HasNEON | 0, // VMAXNMNDf = 1694 12981 Feature_HasV8 | Feature_HasNEON | Feature_HasFullFP16 | 0, // VMAXNMNDh = 1695 12982 Feature_HasV8 | Feature_HasNEON | 0, // VMAXNMNQf = 1696 12983 Feature_HasV8 | Feature_HasNEON | Feature_HasFullFP16 | 0, // VMAXNMNQh = 1697 12984 Feature_HasFPARMv8 | 0, // VMAXNMS = 1698 12985 Feature_HasNEON | 0, // VMAXfd = 1699 12986 Feature_HasNEON | 0, // VMAXfq = 1700 12987 Feature_HasNEON | Feature_HasFullFP16 | 0, // VMAXhd = 1701 12988 Feature_HasNEON | Feature_HasFullFP16 | 0, // VMAXhq = 1702 12989 Feature_HasNEON | 0, // VMAXsv16i8 = 1703 12990 Feature_HasNEON | 0, // VMAXsv2i32 = 1704 12991 Feature_HasNEON | 0, // VMAXsv4i16 = 1705 12992 Feature_HasNEON | 0, // VMAXsv4i32 = 1706 12993 Feature_HasNEON | 0, // VMAXsv8i16 = 1707 12994 Feature_HasNEON | 0, // VMAXsv8i8 = 1708 12995 Feature_HasNEON | 0, // VMAXuv16i8 = 1709 12996 Feature_HasNEON | 0, // VMAXuv2i32 = 1710 12997 Feature_HasNEON | 0, // VMAXuv4i16 = 1711 12998 Feature_HasNEON | 0, // VMAXuv4i32 = 1712 12999 Feature_HasNEON | 0, // VMAXuv8i16 = 1713 13000 Feature_HasNEON | 0, // VMAXuv8i8 = 1714 13001 Feature_HasFPARMv8 | Feature_HasDPVFP | 0, // VMINNMD = 1715 13002 Feature_HasFullFP16 | 0, // VMINNMH = 1716 13003 Feature_HasV8 | Feature_HasNEON | 0, // VMINNMNDf = 1717 13004 Feature_HasV8 | Feature_HasNEON | Feature_HasFullFP16 | 0, // VMINNMNDh = 1718 13005 Feature_HasV8 | Feature_HasNEON | 0, // VMINNMNQf = 1719 13006 Feature_HasV8 | Feature_HasNEON | Feature_HasFullFP16 | 0, // VMINNMNQh = 1720 13007 Feature_HasFPARMv8 | 0, // VMINNMS = 1721 13008 Feature_HasNEON | 0, // VMINfd = 1722 13009 Feature_HasNEON | 0, // VMINfq = 1723 13010 Feature_HasNEON | Feature_HasFullFP16 | 0, // VMINhd = 1724 13011 Feature_HasNEON | Feature_HasFullFP16 | 0, // VMINhq = 1725 13012 Feature_HasNEON | 0, // VMINsv16i8 = 1726 13013 Feature_HasNEON | 0, // VMINsv2i32 = 1727 13014 Feature_HasNEON | 0, // VMINsv4i16 = 1728 13015 Feature_HasNEON | 0, // VMINsv4i32 = 1729 13016 Feature_HasNEON | 0, // VMINsv8i16 = 1730 13017 Feature_HasNEON | 0, // VMINsv8i8 = 1731 13018 Feature_HasNEON | 0, // VMINuv16i8 = 1732 13019 Feature_HasNEON | 0, // VMINuv2i32 = 1733 13020 Feature_HasNEON | 0, // VMINuv4i16 = 1734 13021 Feature_HasNEON | 0, // VMINuv4i32 = 1735 13022 Feature_HasNEON | 0, // VMINuv8i16 = 1736 13023 Feature_HasNEON | 0, // VMINuv8i8 = 1737 13024 Feature_HasVFP2 | Feature_HasDPVFP | 0, // VMLAD = 1738 13025 Feature_HasFullFP16 | 0, // VMLAH = 1739 13026 Feature_HasNEON | 0, // VMLALslsv2i32 = 1740 13027 Feature_HasNEON | 0, // VMLALslsv4i16 = 1741 13028 Feature_HasNEON | 0, // VMLALsluv2i32 = 1742 13029 Feature_HasNEON | 0, // VMLALsluv4i16 = 1743 13030 Feature_HasNEON | 0, // VMLALsv2i64 = 1744 13031 Feature_HasNEON | 0, // VMLALsv4i32 = 1745 13032 Feature_HasNEON | 0, // VMLALsv8i16 = 1746 13033 Feature_HasNEON | 0, // VMLALuv2i64 = 1747 13034 Feature_HasNEON | 0, // VMLALuv4i32 = 1748 13035 Feature_HasNEON | 0, // VMLALuv8i16 = 1749 13036 Feature_HasVFP2 | 0, // VMLAS = 1750 13037 Feature_HasNEON | 0, // VMLAfd = 1751 13038 Feature_HasNEON | 0, // VMLAfq = 1752 13039 Feature_HasNEON | Feature_HasFullFP16 | 0, // VMLAhd = 1753 13040 Feature_HasNEON | Feature_HasFullFP16 | 0, // VMLAhq = 1754 13041 Feature_HasNEON | 0, // VMLAslfd = 1755 13042 Feature_HasNEON | 0, // VMLAslfq = 1756 13043 Feature_HasNEON | Feature_HasFullFP16 | 0, // VMLAslhd = 1757 13044 Feature_HasNEON | Feature_HasFullFP16 | 0, // VMLAslhq = 1758 13045 Feature_HasNEON | 0, // VMLAslv2i32 = 1759 13046 Feature_HasNEON | 0, // VMLAslv4i16 = 1760 13047 Feature_HasNEON | 0, // VMLAslv4i32 = 1761 13048 Feature_HasNEON | 0, // VMLAslv8i16 = 1762 13049 Feature_HasNEON | 0, // VMLAv16i8 = 1763 13050 Feature_HasNEON | 0, // VMLAv2i32 = 1764 13051 Feature_HasNEON | 0, // VMLAv4i16 = 1765 13052 Feature_HasNEON | 0, // VMLAv4i32 = 1766 13053 Feature_HasNEON | 0, // VMLAv8i16 = 1767 13054 Feature_HasNEON | 0, // VMLAv8i8 = 1768 13055 Feature_HasVFP2 | Feature_HasDPVFP | 0, // VMLSD = 1769 13056 Feature_HasFullFP16 | 0, // VMLSH = 1770 13057 Feature_HasNEON | 0, // VMLSLslsv2i32 = 1771 13058 Feature_HasNEON | 0, // VMLSLslsv4i16 = 1772 13059 Feature_HasNEON | 0, // VMLSLsluv2i32 = 1773 13060 Feature_HasNEON | 0, // VMLSLsluv4i16 = 1774 13061 Feature_HasNEON | 0, // VMLSLsv2i64 = 1775 13062 Feature_HasNEON | 0, // VMLSLsv4i32 = 1776 13063 Feature_HasNEON | 0, // VMLSLsv8i16 = 1777 13064 Feature_HasNEON | 0, // VMLSLuv2i64 = 1778 13065 Feature_HasNEON | 0, // VMLSLuv4i32 = 1779 13066 Feature_HasNEON | 0, // VMLSLuv8i16 = 1780 13067 Feature_HasVFP2 | 0, // VMLSS = 1781 13068 Feature_HasNEON | 0, // VMLSfd = 1782 13069 Feature_HasNEON | 0, // VMLSfq = 1783 13070 Feature_HasNEON | Feature_HasFullFP16 | 0, // VMLShd = 1784 13071 Feature_HasNEON | Feature_HasFullFP16 | 0, // VMLShq = 1785 13072 Feature_HasNEON | 0, // VMLSslfd = 1786 13073 Feature_HasNEON | 0, // VMLSslfq = 1787 13074 Feature_HasNEON | Feature_HasFullFP16 | 0, // VMLSslhd = 1788 13075 Feature_HasNEON | Feature_HasFullFP16 | 0, // VMLSslhq = 1789 13076 Feature_HasNEON | 0, // VMLSslv2i32 = 1790 13077 Feature_HasNEON | 0, // VMLSslv4i16 = 1791 13078 Feature_HasNEON | 0, // VMLSslv4i32 = 1792 13079 Feature_HasNEON | 0, // VMLSslv8i16 = 1793 13080 Feature_HasNEON | 0, // VMLSv16i8 = 1794 13081 Feature_HasNEON | 0, // VMLSv2i32 = 1795 13082 Feature_HasNEON | 0, // VMLSv4i16 = 1796 13083 Feature_HasNEON | 0, // VMLSv4i32 = 1797 13084 Feature_HasNEON | 0, // VMLSv8i16 = 1798 13085 Feature_HasNEON | 0, // VMLSv8i8 = 1799 13086 Feature_HasVFP2 | Feature_HasDPVFP | 0, // VMOVD = 1800 13087 Feature_HasVFP2 | 0, // VMOVDRR = 1801 13088 Feature_HasFullFP16 | 0, // VMOVH = 1802 13089 Feature_HasFullFP16 | 0, // VMOVHR = 1803 13090 Feature_HasNEON | 0, // VMOVLsv2i64 = 1804 13091 Feature_HasNEON | 0, // VMOVLsv4i32 = 1805 13092 Feature_HasNEON | 0, // VMOVLsv8i16 = 1806 13093 Feature_HasNEON | 0, // VMOVLuv2i64 = 1807 13094 Feature_HasNEON | 0, // VMOVLuv4i32 = 1808 13095 Feature_HasNEON | 0, // VMOVLuv8i16 = 1809 13096 Feature_HasNEON | 0, // VMOVNv2i32 = 1810 13097 Feature_HasNEON | 0, // VMOVNv4i16 = 1811 13098 Feature_HasNEON | 0, // VMOVNv8i8 = 1812 13099 Feature_HasFullFP16 | 0, // VMOVRH = 1813 13100 Feature_HasVFP2 | 0, // VMOVRRD = 1814 13101 Feature_HasVFP2 | 0, // VMOVRRS = 1815 13102 Feature_HasVFP2 | 0, // VMOVRS = 1816 13103 Feature_HasVFP2 | 0, // VMOVS = 1817 13104 Feature_HasVFP2 | 0, // VMOVSR = 1818 13105 Feature_HasVFP2 | 0, // VMOVSRR = 1819 13106 Feature_HasNEON | 0, // VMOVv16i8 = 1820 13107 Feature_HasNEON | 0, // VMOVv1i64 = 1821 13108 Feature_HasNEON | 0, // VMOVv2f32 = 1822 13109 Feature_HasNEON | 0, // VMOVv2i32 = 1823 13110 Feature_HasNEON | 0, // VMOVv2i64 = 1824 13111 Feature_HasNEON | 0, // VMOVv4f32 = 1825 13112 Feature_HasNEON | 0, // VMOVv4i16 = 1826 13113 Feature_HasNEON | 0, // VMOVv4i32 = 1827 13114 Feature_HasNEON | 0, // VMOVv8i16 = 1828 13115 Feature_HasNEON | 0, // VMOVv8i8 = 1829 13116 Feature_HasVFP2 | 0, // VMRS = 1830 13117 Feature_HasVFP2 | 0, // VMRS_FPEXC = 1831 13118 Feature_HasVFP2 | 0, // VMRS_FPINST = 1832 13119 Feature_HasVFP2 | 0, // VMRS_FPINST2 = 1833 13120 Feature_HasVFP2 | 0, // VMRS_FPSID = 1834 13121 Feature_HasVFP2 | 0, // VMRS_MVFR0 = 1835 13122 Feature_HasVFP2 | 0, // VMRS_MVFR1 = 1836 13123 Feature_HasFPARMv8 | 0, // VMRS_MVFR2 = 1837 13124 Feature_HasVFP2 | 0, // VMSR = 1838 13125 Feature_HasVFP2 | 0, // VMSR_FPEXC = 1839 13126 Feature_HasVFP2 | 0, // VMSR_FPINST = 1840 13127 Feature_HasVFP2 | 0, // VMSR_FPINST2 = 1841 13128 Feature_HasVFP2 | 0, // VMSR_FPSID = 1842 13129 Feature_HasVFP2 | Feature_HasDPVFP | 0, // VMULD = 1843 13130 Feature_HasFullFP16 | 0, // VMULH = 1844 13131 Feature_HasV8 | Feature_HasCrypto | 0, // VMULLp64 = 1845 13132 Feature_HasNEON | 0, // VMULLp8 = 1846 13133 Feature_HasNEON | 0, // VMULLslsv2i32 = 1847 13134 Feature_HasNEON | 0, // VMULLslsv4i16 = 1848 13135 Feature_HasNEON | 0, // VMULLsluv2i32 = 1849 13136 Feature_HasNEON | 0, // VMULLsluv4i16 = 1850 13137 Feature_HasNEON | 0, // VMULLsv2i64 = 1851 13138 Feature_HasNEON | 0, // VMULLsv4i32 = 1852 13139 Feature_HasNEON | 0, // VMULLsv8i16 = 1853 13140 Feature_HasNEON | 0, // VMULLuv2i64 = 1854 13141 Feature_HasNEON | 0, // VMULLuv4i32 = 1855 13142 Feature_HasNEON | 0, // VMULLuv8i16 = 1856 13143 Feature_HasVFP2 | 0, // VMULS = 1857 13144 Feature_HasNEON | 0, // VMULfd = 1858 13145 Feature_HasNEON | 0, // VMULfq = 1859 13146 Feature_HasNEON | Feature_HasFullFP16 | 0, // VMULhd = 1860 13147 Feature_HasNEON | Feature_HasFullFP16 | 0, // VMULhq = 1861 13148 Feature_HasNEON | 0, // VMULpd = 1862 13149 Feature_HasNEON | 0, // VMULpq = 1863 13150 Feature_HasNEON | 0, // VMULslfd = 1864 13151 Feature_HasNEON | 0, // VMULslfq = 1865 13152 Feature_HasNEON | Feature_HasFullFP16 | 0, // VMULslhd = 1866 13153 Feature_HasNEON | Feature_HasFullFP16 | 0, // VMULslhq = 1867 13154 Feature_HasNEON | 0, // VMULslv2i32 = 1868 13155 Feature_HasNEON | 0, // VMULslv4i16 = 1869 13156 Feature_HasNEON | 0, // VMULslv4i32 = 1870 13157 Feature_HasNEON | 0, // VMULslv8i16 = 1871 13158 Feature_HasNEON | 0, // VMULv16i8 = 1872 13159 Feature_HasNEON | 0, // VMULv2i32 = 1873 13160 Feature_HasNEON | 0, // VMULv4i16 = 1874 13161 Feature_HasNEON | 0, // VMULv4i32 = 1875 13162 Feature_HasNEON | 0, // VMULv8i16 = 1876 13163 Feature_HasNEON | 0, // VMULv8i8 = 1877 13164 Feature_HasNEON | 0, // VMVNd = 1878 13165 Feature_HasNEON | 0, // VMVNq = 1879 13166 Feature_HasNEON | 0, // VMVNv2i32 = 1880 13167 Feature_HasNEON | 0, // VMVNv4i16 = 1881 13168 Feature_HasNEON | 0, // VMVNv4i32 = 1882 13169 Feature_HasNEON | 0, // VMVNv8i16 = 1883 13170 Feature_HasVFP2 | Feature_HasDPVFP | 0, // VNEGD = 1884 13171 Feature_HasFullFP16 | 0, // VNEGH = 1885 13172 Feature_HasVFP2 | 0, // VNEGS = 1886 13173 Feature_HasNEON | 0, // VNEGf32q = 1887 13174 Feature_HasNEON | 0, // VNEGfd = 1888 13175 Feature_HasNEON | Feature_HasFullFP16 | 0, // VNEGhd = 1889 13176 Feature_HasNEON | Feature_HasFullFP16 | 0, // VNEGhq = 1890 13177 Feature_HasNEON | 0, // VNEGs16d = 1891 13178 Feature_HasNEON | 0, // VNEGs16q = 1892 13179 Feature_HasNEON | 0, // VNEGs32d = 1893 13180 Feature_HasNEON | 0, // VNEGs32q = 1894 13181 Feature_HasNEON | 0, // VNEGs8d = 1895 13182 Feature_HasNEON | 0, // VNEGs8q = 1896 13183 Feature_HasVFP2 | Feature_HasDPVFP | 0, // VNMLAD = 1897 13184 Feature_HasFullFP16 | 0, // VNMLAH = 1898 13185 Feature_HasVFP2 | 0, // VNMLAS = 1899 13186 Feature_HasVFP2 | Feature_HasDPVFP | 0, // VNMLSD = 1900 13187 Feature_HasFullFP16 | 0, // VNMLSH = 1901 13188 Feature_HasVFP2 | 0, // VNMLSS = 1902 13189 Feature_HasVFP2 | Feature_HasDPVFP | 0, // VNMULD = 1903 13190 Feature_HasFullFP16 | 0, // VNMULH = 1904 13191 Feature_HasVFP2 | 0, // VNMULS = 1905 13192 Feature_HasNEON | 0, // VORNd = 1906 13193 Feature_HasNEON | 0, // VORNq = 1907 13194 Feature_HasNEON | 0, // VORRd = 1908 13195 Feature_HasNEON | 0, // VORRiv2i32 = 1909 13196 Feature_HasNEON | 0, // VORRiv4i16 = 1910 13197 Feature_HasNEON | 0, // VORRiv4i32 = 1911 13198 Feature_HasNEON | 0, // VORRiv8i16 = 1912 13199 Feature_HasNEON | 0, // VORRq = 1913 13200 Feature_HasNEON | 0, // VPADALsv16i8 = 1914 13201 Feature_HasNEON | 0, // VPADALsv2i32 = 1915 13202 Feature_HasNEON | 0, // VPADALsv4i16 = 1916 13203 Feature_HasNEON | 0, // VPADALsv4i32 = 1917 13204 Feature_HasNEON | 0, // VPADALsv8i16 = 1918 13205 Feature_HasNEON | 0, // VPADALsv8i8 = 1919 13206 Feature_HasNEON | 0, // VPADALuv16i8 = 1920 13207 Feature_HasNEON | 0, // VPADALuv2i32 = 1921 13208 Feature_HasNEON | 0, // VPADALuv4i16 = 1922 13209 Feature_HasNEON | 0, // VPADALuv4i32 = 1923 13210 Feature_HasNEON | 0, // VPADALuv8i16 = 1924 13211 Feature_HasNEON | 0, // VPADALuv8i8 = 1925 13212 Feature_HasNEON | 0, // VPADDLsv16i8 = 1926 13213 Feature_HasNEON | 0, // VPADDLsv2i32 = 1927 13214 Feature_HasNEON | 0, // VPADDLsv4i16 = 1928 13215 Feature_HasNEON | 0, // VPADDLsv4i32 = 1929 13216 Feature_HasNEON | 0, // VPADDLsv8i16 = 1930 13217 Feature_HasNEON | 0, // VPADDLsv8i8 = 1931 13218 Feature_HasNEON | 0, // VPADDLuv16i8 = 1932 13219 Feature_HasNEON | 0, // VPADDLuv2i32 = 1933 13220 Feature_HasNEON | 0, // VPADDLuv4i16 = 1934 13221 Feature_HasNEON | 0, // VPADDLuv4i32 = 1935 13222 Feature_HasNEON | 0, // VPADDLuv8i16 = 1936 13223 Feature_HasNEON | 0, // VPADDLuv8i8 = 1937 13224 Feature_HasNEON | 0, // VPADDf = 1938 13225 Feature_HasNEON | Feature_HasFullFP16 | 0, // VPADDh = 1939 13226 Feature_HasNEON | 0, // VPADDi16 = 1940 13227 Feature_HasNEON | 0, // VPADDi32 = 1941 13228 Feature_HasNEON | 0, // VPADDi8 = 1942 13229 Feature_HasNEON | 0, // VPMAXf = 1943 13230 Feature_HasNEON | Feature_HasFullFP16 | 0, // VPMAXh = 1944 13231 Feature_HasNEON | 0, // VPMAXs16 = 1945 13232 Feature_HasNEON | 0, // VPMAXs32 = 1946 13233 Feature_HasNEON | 0, // VPMAXs8 = 1947 13234 Feature_HasNEON | 0, // VPMAXu16 = 1948 13235 Feature_HasNEON | 0, // VPMAXu32 = 1949 13236 Feature_HasNEON | 0, // VPMAXu8 = 1950 13237 Feature_HasNEON | 0, // VPMINf = 1951 13238 Feature_HasNEON | Feature_HasFullFP16 | 0, // VPMINh = 1952 13239 Feature_HasNEON | 0, // VPMINs16 = 1953 13240 Feature_HasNEON | 0, // VPMINs32 = 1954 13241 Feature_HasNEON | 0, // VPMINs8 = 1955 13242 Feature_HasNEON | 0, // VPMINu16 = 1956 13243 Feature_HasNEON | 0, // VPMINu32 = 1957 13244 Feature_HasNEON | 0, // VPMINu8 = 1958 13245 Feature_HasNEON | 0, // VQABSv16i8 = 1959 13246 Feature_HasNEON | 0, // VQABSv2i32 = 1960 13247 Feature_HasNEON | 0, // VQABSv4i16 = 1961 13248 Feature_HasNEON | 0, // VQABSv4i32 = 1962 13249 Feature_HasNEON | 0, // VQABSv8i16 = 1963 13250 Feature_HasNEON | 0, // VQABSv8i8 = 1964 13251 Feature_HasNEON | 0, // VQADDsv16i8 = 1965 13252 Feature_HasNEON | 0, // VQADDsv1i64 = 1966 13253 Feature_HasNEON | 0, // VQADDsv2i32 = 1967 13254 Feature_HasNEON | 0, // VQADDsv2i64 = 1968 13255 Feature_HasNEON | 0, // VQADDsv4i16 = 1969 13256 Feature_HasNEON | 0, // VQADDsv4i32 = 1970 13257 Feature_HasNEON | 0, // VQADDsv8i16 = 1971 13258 Feature_HasNEON | 0, // VQADDsv8i8 = 1972 13259 Feature_HasNEON | 0, // VQADDuv16i8 = 1973 13260 Feature_HasNEON | 0, // VQADDuv1i64 = 1974 13261 Feature_HasNEON | 0, // VQADDuv2i32 = 1975 13262 Feature_HasNEON | 0, // VQADDuv2i64 = 1976 13263 Feature_HasNEON | 0, // VQADDuv4i16 = 1977 13264 Feature_HasNEON | 0, // VQADDuv4i32 = 1978 13265 Feature_HasNEON | 0, // VQADDuv8i16 = 1979 13266 Feature_HasNEON | 0, // VQADDuv8i8 = 1980 13267 Feature_HasNEON | 0, // VQDMLALslv2i32 = 1981 13268 Feature_HasNEON | 0, // VQDMLALslv4i16 = 1982 13269 Feature_HasNEON | 0, // VQDMLALv2i64 = 1983 13270 Feature_HasNEON | 0, // VQDMLALv4i32 = 1984 13271 Feature_HasNEON | 0, // VQDMLSLslv2i32 = 1985 13272 Feature_HasNEON | 0, // VQDMLSLslv4i16 = 1986 13273 Feature_HasNEON | 0, // VQDMLSLv2i64 = 1987 13274 Feature_HasNEON | 0, // VQDMLSLv4i32 = 1988 13275 Feature_HasNEON | 0, // VQDMULHslv2i32 = 1989 13276 Feature_HasNEON | 0, // VQDMULHslv4i16 = 1990 13277 Feature_HasNEON | 0, // VQDMULHslv4i32 = 1991 13278 Feature_HasNEON | 0, // VQDMULHslv8i16 = 1992 13279 Feature_HasNEON | 0, // VQDMULHv2i32 = 1993 13280 Feature_HasNEON | 0, // VQDMULHv4i16 = 1994 13281 Feature_HasNEON | 0, // VQDMULHv4i32 = 1995 13282 Feature_HasNEON | 0, // VQDMULHv8i16 = 1996 13283 Feature_HasNEON | 0, // VQDMULLslv2i32 = 1997 13284 Feature_HasNEON | 0, // VQDMULLslv4i16 = 1998 13285 Feature_HasNEON | 0, // VQDMULLv2i64 = 1999 13286 Feature_HasNEON | 0, // VQDMULLv4i32 = 2000 13287 Feature_HasNEON | 0, // VQMOVNsuv2i32 = 2001 13288 Feature_HasNEON | 0, // VQMOVNsuv4i16 = 2002 13289 Feature_HasNEON | 0, // VQMOVNsuv8i8 = 2003 13290 Feature_HasNEON | 0, // VQMOVNsv2i32 = 2004 13291 Feature_HasNEON | 0, // VQMOVNsv4i16 = 2005 13292 Feature_HasNEON | 0, // VQMOVNsv8i8 = 2006 13293 Feature_HasNEON | 0, // VQMOVNuv2i32 = 2007 13294 Feature_HasNEON | 0, // VQMOVNuv4i16 = 2008 13295 Feature_HasNEON | 0, // VQMOVNuv8i8 = 2009 13296 Feature_HasNEON | 0, // VQNEGv16i8 = 2010 13297 Feature_HasNEON | 0, // VQNEGv2i32 = 2011 13298 Feature_HasNEON | 0, // VQNEGv4i16 = 2012 13299 Feature_HasNEON | 0, // VQNEGv4i32 = 2013 13300 Feature_HasNEON | 0, // VQNEGv8i16 = 2014 13301 Feature_HasNEON | 0, // VQNEGv8i8 = 2015 13302 Feature_HasNEON | Feature_HasV8_1a | 0, // VQRDMLAHslv2i32 = 2016 13303 Feature_HasNEON | Feature_HasV8_1a | 0, // VQRDMLAHslv4i16 = 2017 13304 Feature_HasNEON | Feature_HasV8_1a | 0, // VQRDMLAHslv4i32 = 2018 13305 Feature_HasNEON | Feature_HasV8_1a | 0, // VQRDMLAHslv8i16 = 2019 13306 Feature_HasNEON | Feature_HasV8_1a | 0, // VQRDMLAHv2i32 = 2020 13307 Feature_HasNEON | Feature_HasV8_1a | 0, // VQRDMLAHv4i16 = 2021 13308 Feature_HasNEON | Feature_HasV8_1a | 0, // VQRDMLAHv4i32 = 2022 13309 Feature_HasNEON | Feature_HasV8_1a | 0, // VQRDMLAHv8i16 = 2023 13310 Feature_HasNEON | Feature_HasV8_1a | 0, // VQRDMLSHslv2i32 = 2024 13311 Feature_HasNEON | Feature_HasV8_1a | 0, // VQRDMLSHslv4i16 = 2025 13312 Feature_HasNEON | Feature_HasV8_1a | 0, // VQRDMLSHslv4i32 = 2026 13313 Feature_HasNEON | Feature_HasV8_1a | 0, // VQRDMLSHslv8i16 = 2027 13314 Feature_HasNEON | Feature_HasV8_1a | 0, // VQRDMLSHv2i32 = 2028 13315 Feature_HasNEON | Feature_HasV8_1a | 0, // VQRDMLSHv4i16 = 2029 13316 Feature_HasNEON | Feature_HasV8_1a | 0, // VQRDMLSHv4i32 = 2030 13317 Feature_HasNEON | Feature_HasV8_1a | 0, // VQRDMLSHv8i16 = 2031 13318 Feature_HasNEON | 0, // VQRDMULHslv2i32 = 2032 13319 Feature_HasNEON | 0, // VQRDMULHslv4i16 = 2033 13320 Feature_HasNEON | 0, // VQRDMULHslv4i32 = 2034 13321 Feature_HasNEON | 0, // VQRDMULHslv8i16 = 2035 13322 Feature_HasNEON | 0, // VQRDMULHv2i32 = 2036 13323 Feature_HasNEON | 0, // VQRDMULHv4i16 = 2037 13324 Feature_HasNEON | 0, // VQRDMULHv4i32 = 2038 13325 Feature_HasNEON | 0, // VQRDMULHv8i16 = 2039 13326 Feature_HasNEON | 0, // VQRSHLsv16i8 = 2040 13327 Feature_HasNEON | 0, // VQRSHLsv1i64 = 2041 13328 Feature_HasNEON | 0, // VQRSHLsv2i32 = 2042 13329 Feature_HasNEON | 0, // VQRSHLsv2i64 = 2043 13330 Feature_HasNEON | 0, // VQRSHLsv4i16 = 2044 13331 Feature_HasNEON | 0, // VQRSHLsv4i32 = 2045 13332 Feature_HasNEON | 0, // VQRSHLsv8i16 = 2046 13333 Feature_HasNEON | 0, // VQRSHLsv8i8 = 2047 13334 Feature_HasNEON | 0, // VQRSHLuv16i8 = 2048 13335 Feature_HasNEON | 0, // VQRSHLuv1i64 = 2049 13336 Feature_HasNEON | 0, // VQRSHLuv2i32 = 2050 13337 Feature_HasNEON | 0, // VQRSHLuv2i64 = 2051 13338 Feature_HasNEON | 0, // VQRSHLuv4i16 = 2052 13339 Feature_HasNEON | 0, // VQRSHLuv4i32 = 2053 13340 Feature_HasNEON | 0, // VQRSHLuv8i16 = 2054 13341 Feature_HasNEON | 0, // VQRSHLuv8i8 = 2055 13342 Feature_HasNEON | 0, // VQRSHRNsv2i32 = 2056 13343 Feature_HasNEON | 0, // VQRSHRNsv4i16 = 2057 13344 Feature_HasNEON | 0, // VQRSHRNsv8i8 = 2058 13345 Feature_HasNEON | 0, // VQRSHRNuv2i32 = 2059 13346 Feature_HasNEON | 0, // VQRSHRNuv4i16 = 2060 13347 Feature_HasNEON | 0, // VQRSHRNuv8i8 = 2061 13348 Feature_HasNEON | 0, // VQRSHRUNv2i32 = 2062 13349 Feature_HasNEON | 0, // VQRSHRUNv4i16 = 2063 13350 Feature_HasNEON | 0, // VQRSHRUNv8i8 = 2064 13351 Feature_HasNEON | 0, // VQSHLsiv16i8 = 2065 13352 Feature_HasNEON | 0, // VQSHLsiv1i64 = 2066 13353 Feature_HasNEON | 0, // VQSHLsiv2i32 = 2067 13354 Feature_HasNEON | 0, // VQSHLsiv2i64 = 2068 13355 Feature_HasNEON | 0, // VQSHLsiv4i16 = 2069 13356 Feature_HasNEON | 0, // VQSHLsiv4i32 = 2070 13357 Feature_HasNEON | 0, // VQSHLsiv8i16 = 2071 13358 Feature_HasNEON | 0, // VQSHLsiv8i8 = 2072 13359 Feature_HasNEON | 0, // VQSHLsuv16i8 = 2073 13360 Feature_HasNEON | 0, // VQSHLsuv1i64 = 2074 13361 Feature_HasNEON | 0, // VQSHLsuv2i32 = 2075 13362 Feature_HasNEON | 0, // VQSHLsuv2i64 = 2076 13363 Feature_HasNEON | 0, // VQSHLsuv4i16 = 2077 13364 Feature_HasNEON | 0, // VQSHLsuv4i32 = 2078 13365 Feature_HasNEON | 0, // VQSHLsuv8i16 = 2079 13366 Feature_HasNEON | 0, // VQSHLsuv8i8 = 2080 13367 Feature_HasNEON | 0, // VQSHLsv16i8 = 2081 13368 Feature_HasNEON | 0, // VQSHLsv1i64 = 2082 13369 Feature_HasNEON | 0, // VQSHLsv2i32 = 2083 13370 Feature_HasNEON | 0, // VQSHLsv2i64 = 2084 13371 Feature_HasNEON | 0, // VQSHLsv4i16 = 2085 13372 Feature_HasNEON | 0, // VQSHLsv4i32 = 2086 13373 Feature_HasNEON | 0, // VQSHLsv8i16 = 2087 13374 Feature_HasNEON | 0, // VQSHLsv8i8 = 2088 13375 Feature_HasNEON | 0, // VQSHLuiv16i8 = 2089 13376 Feature_HasNEON | 0, // VQSHLuiv1i64 = 2090 13377 Feature_HasNEON | 0, // VQSHLuiv2i32 = 2091 13378 Feature_HasNEON | 0, // VQSHLuiv2i64 = 2092 13379 Feature_HasNEON | 0, // VQSHLuiv4i16 = 2093 13380 Feature_HasNEON | 0, // VQSHLuiv4i32 = 2094 13381 Feature_HasNEON | 0, // VQSHLuiv8i16 = 2095 13382 Feature_HasNEON | 0, // VQSHLuiv8i8 = 2096 13383 Feature_HasNEON | 0, // VQSHLuv16i8 = 2097 13384 Feature_HasNEON | 0, // VQSHLuv1i64 = 2098 13385 Feature_HasNEON | 0, // VQSHLuv2i32 = 2099 13386 Feature_HasNEON | 0, // VQSHLuv2i64 = 2100 13387 Feature_HasNEON | 0, // VQSHLuv4i16 = 2101 13388 Feature_HasNEON | 0, // VQSHLuv4i32 = 2102 13389 Feature_HasNEON | 0, // VQSHLuv8i16 = 2103 13390 Feature_HasNEON | 0, // VQSHLuv8i8 = 2104 13391 Feature_HasNEON | 0, // VQSHRNsv2i32 = 2105 13392 Feature_HasNEON | 0, // VQSHRNsv4i16 = 2106 13393 Feature_HasNEON | 0, // VQSHRNsv8i8 = 2107 13394 Feature_HasNEON | 0, // VQSHRNuv2i32 = 2108 13395 Feature_HasNEON | 0, // VQSHRNuv4i16 = 2109 13396 Feature_HasNEON | 0, // VQSHRNuv8i8 = 2110 13397 Feature_HasNEON | 0, // VQSHRUNv2i32 = 2111 13398 Feature_HasNEON | 0, // VQSHRUNv4i16 = 2112 13399 Feature_HasNEON | 0, // VQSHRUNv8i8 = 2113 13400 Feature_HasNEON | 0, // VQSUBsv16i8 = 2114 13401 Feature_HasNEON | 0, // VQSUBsv1i64 = 2115 13402 Feature_HasNEON | 0, // VQSUBsv2i32 = 2116 13403 Feature_HasNEON | 0, // VQSUBsv2i64 = 2117 13404 Feature_HasNEON | 0, // VQSUBsv4i16 = 2118 13405 Feature_HasNEON | 0, // VQSUBsv4i32 = 2119 13406 Feature_HasNEON | 0, // VQSUBsv8i16 = 2120 13407 Feature_HasNEON | 0, // VQSUBsv8i8 = 2121 13408 Feature_HasNEON | 0, // VQSUBuv16i8 = 2122 13409 Feature_HasNEON | 0, // VQSUBuv1i64 = 2123 13410 Feature_HasNEON | 0, // VQSUBuv2i32 = 2124 13411 Feature_HasNEON | 0, // VQSUBuv2i64 = 2125 13412 Feature_HasNEON | 0, // VQSUBuv4i16 = 2126 13413 Feature_HasNEON | 0, // VQSUBuv4i32 = 2127 13414 Feature_HasNEON | 0, // VQSUBuv8i16 = 2128 13415 Feature_HasNEON | 0, // VQSUBuv8i8 = 2129 13416 Feature_HasNEON | 0, // VRADDHNv2i32 = 2130 13417 Feature_HasNEON | 0, // VRADDHNv4i16 = 2131 13418 Feature_HasNEON | 0, // VRADDHNv8i8 = 2132 13419 Feature_HasNEON | 0, // VRECPEd = 2133 13420 Feature_HasNEON | 0, // VRECPEfd = 2134 13421 Feature_HasNEON | 0, // VRECPEfq = 2135 13422 Feature_HasNEON | Feature_HasFullFP16 | 0, // VRECPEhd = 2136 13423 Feature_HasNEON | Feature_HasFullFP16 | 0, // VRECPEhq = 2137 13424 Feature_HasNEON | 0, // VRECPEq = 2138 13425 Feature_HasNEON | 0, // VRECPSfd = 2139 13426 Feature_HasNEON | 0, // VRECPSfq = 2140 13427 Feature_HasNEON | Feature_HasFullFP16 | 0, // VRECPShd = 2141 13428 Feature_HasNEON | Feature_HasFullFP16 | 0, // VRECPShq = 2142 13429 Feature_HasNEON | 0, // VREV16d8 = 2143 13430 Feature_HasNEON | 0, // VREV16q8 = 2144 13431 Feature_HasNEON | 0, // VREV32d16 = 2145 13432 Feature_HasNEON | 0, // VREV32d8 = 2146 13433 Feature_HasNEON | 0, // VREV32q16 = 2147 13434 Feature_HasNEON | 0, // VREV32q8 = 2148 13435 Feature_HasNEON | 0, // VREV64d16 = 2149 13436 Feature_HasNEON | 0, // VREV64d32 = 2150 13437 Feature_HasNEON | 0, // VREV64d8 = 2151 13438 Feature_HasNEON | 0, // VREV64q16 = 2152 13439 Feature_HasNEON | 0, // VREV64q32 = 2153 13440 Feature_HasNEON | 0, // VREV64q8 = 2154 13441 Feature_HasNEON | 0, // VRHADDsv16i8 = 2155 13442 Feature_HasNEON | 0, // VRHADDsv2i32 = 2156 13443 Feature_HasNEON | 0, // VRHADDsv4i16 = 2157 13444 Feature_HasNEON | 0, // VRHADDsv4i32 = 2158 13445 Feature_HasNEON | 0, // VRHADDsv8i16 = 2159 13446 Feature_HasNEON | 0, // VRHADDsv8i8 = 2160 13447 Feature_HasNEON | 0, // VRHADDuv16i8 = 2161 13448 Feature_HasNEON | 0, // VRHADDuv2i32 = 2162 13449 Feature_HasNEON | 0, // VRHADDuv4i16 = 2163 13450 Feature_HasNEON | 0, // VRHADDuv4i32 = 2164 13451 Feature_HasNEON | 0, // VRHADDuv8i16 = 2165 13452 Feature_HasNEON | 0, // VRHADDuv8i8 = 2166 13453 Feature_HasFPARMv8 | Feature_HasDPVFP | 0, // VRINTAD = 2167 13454 Feature_HasFullFP16 | 0, // VRINTAH = 2168 13455 Feature_HasV8 | Feature_HasNEON | 0, // VRINTANDf = 2169 13456 Feature_HasV8 | Feature_HasNEON | Feature_HasFullFP16 | 0, // VRINTANDh = 2170 13457 Feature_HasV8 | Feature_HasNEON | 0, // VRINTANQf = 2171 13458 Feature_HasV8 | Feature_HasNEON | Feature_HasFullFP16 | 0, // VRINTANQh = 2172 13459 Feature_HasFPARMv8 | 0, // VRINTAS = 2173 13460 Feature_HasFPARMv8 | Feature_HasDPVFP | 0, // VRINTMD = 2174 13461 Feature_HasFullFP16 | 0, // VRINTMH = 2175 13462 Feature_HasV8 | Feature_HasNEON | 0, // VRINTMNDf = 2176 13463 Feature_HasV8 | Feature_HasNEON | Feature_HasFullFP16 | 0, // VRINTMNDh = 2177 13464 Feature_HasV8 | Feature_HasNEON | 0, // VRINTMNQf = 2178 13465 Feature_HasV8 | Feature_HasNEON | Feature_HasFullFP16 | 0, // VRINTMNQh = 2179 13466 Feature_HasFPARMv8 | 0, // VRINTMS = 2180 13467 Feature_HasFPARMv8 | Feature_HasDPVFP | 0, // VRINTND = 2181 13468 Feature_HasFullFP16 | 0, // VRINTNH = 2182 13469 Feature_HasV8 | Feature_HasNEON | 0, // VRINTNNDf = 2183 13470 Feature_HasV8 | Feature_HasNEON | Feature_HasFullFP16 | 0, // VRINTNNDh = 2184 13471 Feature_HasV8 | Feature_HasNEON | 0, // VRINTNNQf = 2185 13472 Feature_HasV8 | Feature_HasNEON | Feature_HasFullFP16 | 0, // VRINTNNQh = 2186 13473 Feature_HasFPARMv8 | 0, // VRINTNS = 2187 13474 Feature_HasFPARMv8 | Feature_HasDPVFP | 0, // VRINTPD = 2188 13475 Feature_HasFullFP16 | 0, // VRINTPH = 2189 13476 Feature_HasV8 | Feature_HasNEON | 0, // VRINTPNDf = 2190 13477 Feature_HasV8 | Feature_HasNEON | Feature_HasFullFP16 | 0, // VRINTPNDh = 2191 13478 Feature_HasV8 | Feature_HasNEON | 0, // VRINTPNQf = 2192 13479 Feature_HasV8 | Feature_HasNEON | Feature_HasFullFP16 | 0, // VRINTPNQh = 2193 13480 Feature_HasFPARMv8 | 0, // VRINTPS = 2194 13481 Feature_HasFPARMv8 | Feature_HasDPVFP | 0, // VRINTRD = 2195 13482 Feature_HasFullFP16 | 0, // VRINTRH = 2196 13483 Feature_HasFPARMv8 | 0, // VRINTRS = 2197 13484 Feature_HasFPARMv8 | Feature_HasDPVFP | 0, // VRINTXD = 2198 13485 Feature_HasFullFP16 | 0, // VRINTXH = 2199 13486 Feature_HasV8 | Feature_HasNEON | 0, // VRINTXNDf = 2200 13487 Feature_HasV8 | Feature_HasNEON | Feature_HasFullFP16 | 0, // VRINTXNDh = 2201 13488 Feature_HasV8 | Feature_HasNEON | 0, // VRINTXNQf = 2202 13489 Feature_HasV8 | Feature_HasNEON | Feature_HasFullFP16 | 0, // VRINTXNQh = 2203 13490 Feature_HasFPARMv8 | 0, // VRINTXS = 2204 13491 Feature_HasFPARMv8 | Feature_HasDPVFP | 0, // VRINTZD = 2205 13492 Feature_HasFullFP16 | 0, // VRINTZH = 2206 13493 Feature_HasV8 | Feature_HasNEON | 0, // VRINTZNDf = 2207 13494 Feature_HasV8 | Feature_HasNEON | Feature_HasFullFP16 | 0, // VRINTZNDh = 2208 13495 Feature_HasV8 | Feature_HasNEON | 0, // VRINTZNQf = 2209 13496 Feature_HasV8 | Feature_HasNEON | Feature_HasFullFP16 | 0, // VRINTZNQh = 2210 13497 Feature_HasFPARMv8 | 0, // VRINTZS = 2211 13498 Feature_HasNEON | 0, // VRSHLsv16i8 = 2212 13499 Feature_HasNEON | 0, // VRSHLsv1i64 = 2213 13500 Feature_HasNEON | 0, // VRSHLsv2i32 = 2214 13501 Feature_HasNEON | 0, // VRSHLsv2i64 = 2215 13502 Feature_HasNEON | 0, // VRSHLsv4i16 = 2216 13503 Feature_HasNEON | 0, // VRSHLsv4i32 = 2217 13504 Feature_HasNEON | 0, // VRSHLsv8i16 = 2218 13505 Feature_HasNEON | 0, // VRSHLsv8i8 = 2219 13506 Feature_HasNEON | 0, // VRSHLuv16i8 = 2220 13507 Feature_HasNEON | 0, // VRSHLuv1i64 = 2221 13508 Feature_HasNEON | 0, // VRSHLuv2i32 = 2222 13509 Feature_HasNEON | 0, // VRSHLuv2i64 = 2223 13510 Feature_HasNEON | 0, // VRSHLuv4i16 = 2224 13511 Feature_HasNEON | 0, // VRSHLuv4i32 = 2225 13512 Feature_HasNEON | 0, // VRSHLuv8i16 = 2226 13513 Feature_HasNEON | 0, // VRSHLuv8i8 = 2227 13514 Feature_HasNEON | 0, // VRSHRNv2i32 = 2228 13515 Feature_HasNEON | 0, // VRSHRNv4i16 = 2229 13516 Feature_HasNEON | 0, // VRSHRNv8i8 = 2230 13517 Feature_HasNEON | 0, // VRSHRsv16i8 = 2231 13518 Feature_HasNEON | 0, // VRSHRsv1i64 = 2232 13519 Feature_HasNEON | 0, // VRSHRsv2i32 = 2233 13520 Feature_HasNEON | 0, // VRSHRsv2i64 = 2234 13521 Feature_HasNEON | 0, // VRSHRsv4i16 = 2235 13522 Feature_HasNEON | 0, // VRSHRsv4i32 = 2236 13523 Feature_HasNEON | 0, // VRSHRsv8i16 = 2237 13524 Feature_HasNEON | 0, // VRSHRsv8i8 = 2238 13525 Feature_HasNEON | 0, // VRSHRuv16i8 = 2239 13526 Feature_HasNEON | 0, // VRSHRuv1i64 = 2240 13527 Feature_HasNEON | 0, // VRSHRuv2i32 = 2241 13528 Feature_HasNEON | 0, // VRSHRuv2i64 = 2242 13529 Feature_HasNEON | 0, // VRSHRuv4i16 = 2243 13530 Feature_HasNEON | 0, // VRSHRuv4i32 = 2244 13531 Feature_HasNEON | 0, // VRSHRuv8i16 = 2245 13532 Feature_HasNEON | 0, // VRSHRuv8i8 = 2246 13533 Feature_HasNEON | 0, // VRSQRTEd = 2247 13534 Feature_HasNEON | 0, // VRSQRTEfd = 2248 13535 Feature_HasNEON | 0, // VRSQRTEfq = 2249 13536 Feature_HasNEON | Feature_HasFullFP16 | 0, // VRSQRTEhd = 2250 13537 Feature_HasNEON | Feature_HasFullFP16 | 0, // VRSQRTEhq = 2251 13538 Feature_HasNEON | 0, // VRSQRTEq = 2252 13539 Feature_HasNEON | 0, // VRSQRTSfd = 2253 13540 Feature_HasNEON | 0, // VRSQRTSfq = 2254 13541 Feature_HasNEON | Feature_HasFullFP16 | 0, // VRSQRTShd = 2255 13542 Feature_HasNEON | Feature_HasFullFP16 | 0, // VRSQRTShq = 2256 13543 Feature_HasNEON | 0, // VRSRAsv16i8 = 2257 13544 Feature_HasNEON | 0, // VRSRAsv1i64 = 2258 13545 Feature_HasNEON | 0, // VRSRAsv2i32 = 2259 13546 Feature_HasNEON | 0, // VRSRAsv2i64 = 2260 13547 Feature_HasNEON | 0, // VRSRAsv4i16 = 2261 13548 Feature_HasNEON | 0, // VRSRAsv4i32 = 2262 13549 Feature_HasNEON | 0, // VRSRAsv8i16 = 2263 13550 Feature_HasNEON | 0, // VRSRAsv8i8 = 2264 13551 Feature_HasNEON | 0, // VRSRAuv16i8 = 2265 13552 Feature_HasNEON | 0, // VRSRAuv1i64 = 2266 13553 Feature_HasNEON | 0, // VRSRAuv2i32 = 2267 13554 Feature_HasNEON | 0, // VRSRAuv2i64 = 2268 13555 Feature_HasNEON | 0, // VRSRAuv4i16 = 2269 13556 Feature_HasNEON | 0, // VRSRAuv4i32 = 2270 13557 Feature_HasNEON | 0, // VRSRAuv8i16 = 2271 13558 Feature_HasNEON | 0, // VRSRAuv8i8 = 2272 13559 Feature_HasNEON | 0, // VRSUBHNv2i32 = 2273 13560 Feature_HasNEON | 0, // VRSUBHNv4i16 = 2274 13561 Feature_HasNEON | 0, // VRSUBHNv8i8 = 2275 13562 Feature_HasDotProd | 0, // VSDOTD = 2276 13563 Feature_HasDotProd | 0, // VSDOTDI = 2277 13564 Feature_HasDotProd | 0, // VSDOTQ = 2278 13565 Feature_HasDotProd | 0, // VSDOTQI = 2279 13566 Feature_HasFPARMv8 | Feature_HasDPVFP | 0, // VSELEQD = 2280 13567 Feature_HasFullFP16 | 0, // VSELEQH = 2281 13568 Feature_HasFPARMv8 | 0, // VSELEQS = 2282 13569 Feature_HasFPARMv8 | Feature_HasDPVFP | 0, // VSELGED = 2283 13570 Feature_HasFullFP16 | 0, // VSELGEH = 2284 13571 Feature_HasFPARMv8 | 0, // VSELGES = 2285 13572 Feature_HasFPARMv8 | Feature_HasDPVFP | 0, // VSELGTD = 2286 13573 Feature_HasFullFP16 | 0, // VSELGTH = 2287 13574 Feature_HasFPARMv8 | 0, // VSELGTS = 2288 13575 Feature_HasFPARMv8 | Feature_HasDPVFP | 0, // VSELVSD = 2289 13576 Feature_HasFullFP16 | 0, // VSELVSH = 2290 13577 Feature_HasFPARMv8 | 0, // VSELVSS = 2291 13578 Feature_HasNEON | 0, // VSETLNi16 = 2292 13579 Feature_HasVFP2 | 0, // VSETLNi32 = 2293 13580 Feature_HasNEON | 0, // VSETLNi8 = 2294 13581 Feature_HasNEON | 0, // VSHLLi16 = 2295 13582 Feature_HasNEON | 0, // VSHLLi32 = 2296 13583 Feature_HasNEON | 0, // VSHLLi8 = 2297 13584 Feature_HasNEON | 0, // VSHLLsv2i64 = 2298 13585 Feature_HasNEON | 0, // VSHLLsv4i32 = 2299 13586 Feature_HasNEON | 0, // VSHLLsv8i16 = 2300 13587 Feature_HasNEON | 0, // VSHLLuv2i64 = 2301 13588 Feature_HasNEON | 0, // VSHLLuv4i32 = 2302 13589 Feature_HasNEON | 0, // VSHLLuv8i16 = 2303 13590 Feature_HasNEON | 0, // VSHLiv16i8 = 2304 13591 Feature_HasNEON | 0, // VSHLiv1i64 = 2305 13592 Feature_HasNEON | 0, // VSHLiv2i32 = 2306 13593 Feature_HasNEON | 0, // VSHLiv2i64 = 2307 13594 Feature_HasNEON | 0, // VSHLiv4i16 = 2308 13595 Feature_HasNEON | 0, // VSHLiv4i32 = 2309 13596 Feature_HasNEON | 0, // VSHLiv8i16 = 2310 13597 Feature_HasNEON | 0, // VSHLiv8i8 = 2311 13598 Feature_HasNEON | 0, // VSHLsv16i8 = 2312 13599 Feature_HasNEON | 0, // VSHLsv1i64 = 2313 13600 Feature_HasNEON | 0, // VSHLsv2i32 = 2314 13601 Feature_HasNEON | 0, // VSHLsv2i64 = 2315 13602 Feature_HasNEON | 0, // VSHLsv4i16 = 2316 13603 Feature_HasNEON | 0, // VSHLsv4i32 = 2317 13604 Feature_HasNEON | 0, // VSHLsv8i16 = 2318 13605 Feature_HasNEON | 0, // VSHLsv8i8 = 2319 13606 Feature_HasNEON | 0, // VSHLuv16i8 = 2320 13607 Feature_HasNEON | 0, // VSHLuv1i64 = 2321 13608 Feature_HasNEON | 0, // VSHLuv2i32 = 2322 13609 Feature_HasNEON | 0, // VSHLuv2i64 = 2323 13610 Feature_HasNEON | 0, // VSHLuv4i16 = 2324 13611 Feature_HasNEON | 0, // VSHLuv4i32 = 2325 13612 Feature_HasNEON | 0, // VSHLuv8i16 = 2326 13613 Feature_HasNEON | 0, // VSHLuv8i8 = 2327 13614 Feature_HasNEON | 0, // VSHRNv2i32 = 2328 13615 Feature_HasNEON | 0, // VSHRNv4i16 = 2329 13616 Feature_HasNEON | 0, // VSHRNv8i8 = 2330 13617 Feature_HasNEON | 0, // VSHRsv16i8 = 2331 13618 Feature_HasNEON | 0, // VSHRsv1i64 = 2332 13619 Feature_HasNEON | 0, // VSHRsv2i32 = 2333 13620 Feature_HasNEON | 0, // VSHRsv2i64 = 2334 13621 Feature_HasNEON | 0, // VSHRsv4i16 = 2335 13622 Feature_HasNEON | 0, // VSHRsv4i32 = 2336 13623 Feature_HasNEON | 0, // VSHRsv8i16 = 2337 13624 Feature_HasNEON | 0, // VSHRsv8i8 = 2338 13625 Feature_HasNEON | 0, // VSHRuv16i8 = 2339 13626 Feature_HasNEON | 0, // VSHRuv1i64 = 2340 13627 Feature_HasNEON | 0, // VSHRuv2i32 = 2341 13628 Feature_HasNEON | 0, // VSHRuv2i64 = 2342 13629 Feature_HasNEON | 0, // VSHRuv4i16 = 2343 13630 Feature_HasNEON | 0, // VSHRuv4i32 = 2344 13631 Feature_HasNEON | 0, // VSHRuv8i16 = 2345 13632 Feature_HasNEON | 0, // VSHRuv8i8 = 2346 13633 Feature_HasVFP2 | Feature_HasDPVFP | 0, // VSHTOD = 2347 13634 Feature_HasFullFP16 | 0, // VSHTOH = 2348 13635 Feature_HasVFP2 | 0, // VSHTOS = 2349 13636 Feature_HasVFP2 | Feature_HasDPVFP | 0, // VSITOD = 2350 13637 Feature_HasFullFP16 | 0, // VSITOH = 2351 13638 Feature_HasVFP2 | 0, // VSITOS = 2352 13639 Feature_HasNEON | 0, // VSLIv16i8 = 2353 13640 Feature_HasNEON | 0, // VSLIv1i64 = 2354 13641 Feature_HasNEON | 0, // VSLIv2i32 = 2355 13642 Feature_HasNEON | 0, // VSLIv2i64 = 2356 13643 Feature_HasNEON | 0, // VSLIv4i16 = 2357 13644 Feature_HasNEON | 0, // VSLIv4i32 = 2358 13645 Feature_HasNEON | 0, // VSLIv8i16 = 2359 13646 Feature_HasNEON | 0, // VSLIv8i8 = 2360 13647 Feature_HasVFP2 | Feature_HasDPVFP | 0, // VSLTOD = 2361 13648 Feature_HasFullFP16 | 0, // VSLTOH = 2362 13649 Feature_HasVFP2 | 0, // VSLTOS = 2363 13650 Feature_HasVFP2 | Feature_HasDPVFP | 0, // VSQRTD = 2364 13651 Feature_HasFullFP16 | 0, // VSQRTH = 2365 13652 Feature_HasVFP2 | 0, // VSQRTS = 2366 13653 Feature_HasNEON | 0, // VSRAsv16i8 = 2367 13654 Feature_HasNEON | 0, // VSRAsv1i64 = 2368 13655 Feature_HasNEON | 0, // VSRAsv2i32 = 2369 13656 Feature_HasNEON | 0, // VSRAsv2i64 = 2370 13657 Feature_HasNEON | 0, // VSRAsv4i16 = 2371 13658 Feature_HasNEON | 0, // VSRAsv4i32 = 2372 13659 Feature_HasNEON | 0, // VSRAsv8i16 = 2373 13660 Feature_HasNEON | 0, // VSRAsv8i8 = 2374 13661 Feature_HasNEON | 0, // VSRAuv16i8 = 2375 13662 Feature_HasNEON | 0, // VSRAuv1i64 = 2376 13663 Feature_HasNEON | 0, // VSRAuv2i32 = 2377 13664 Feature_HasNEON | 0, // VSRAuv2i64 = 2378 13665 Feature_HasNEON | 0, // VSRAuv4i16 = 2379 13666 Feature_HasNEON | 0, // VSRAuv4i32 = 2380 13667 Feature_HasNEON | 0, // VSRAuv8i16 = 2381 13668 Feature_HasNEON | 0, // VSRAuv8i8 = 2382 13669 Feature_HasNEON | 0, // VSRIv16i8 = 2383 13670 Feature_HasNEON | 0, // VSRIv1i64 = 2384 13671 Feature_HasNEON | 0, // VSRIv2i32 = 2385 13672 Feature_HasNEON | 0, // VSRIv2i64 = 2386 13673 Feature_HasNEON | 0, // VSRIv4i16 = 2387 13674 Feature_HasNEON | 0, // VSRIv4i32 = 2388 13675 Feature_HasNEON | 0, // VSRIv8i16 = 2389 13676 Feature_HasNEON | 0, // VSRIv8i8 = 2390 13677 Feature_HasNEON | 0, // VST1LNd16 = 2391 13678 Feature_HasNEON | 0, // VST1LNd16_UPD = 2392 13679 Feature_HasNEON | 0, // VST1LNd32 = 2393 13680 Feature_HasNEON | 0, // VST1LNd32_UPD = 2394 13681 Feature_HasNEON | 0, // VST1LNd8 = 2395 13682 Feature_HasNEON | 0, // VST1LNd8_UPD = 2396 13683 Feature_HasNEON | 0, // VST1LNq16Pseudo = 2397 13684 Feature_HasNEON | 0, // VST1LNq16Pseudo_UPD = 2398 13685 Feature_HasNEON | 0, // VST1LNq32Pseudo = 2399 13686 Feature_HasNEON | 0, // VST1LNq32Pseudo_UPD = 2400 13687 Feature_HasNEON | 0, // VST1LNq8Pseudo = 2401 13688 Feature_HasNEON | 0, // VST1LNq8Pseudo_UPD = 2402 13689 Feature_HasNEON | 0, // VST1d16 = 2403 13690 Feature_HasNEON | 0, // VST1d16Q = 2404 13691 Feature_HasNEON | 0, // VST1d16QPseudo = 2405 13692 Feature_HasNEON | 0, // VST1d16Qwb_fixed = 2406 13693 Feature_HasNEON | 0, // VST1d16Qwb_register = 2407 13694 Feature_HasNEON | 0, // VST1d16T = 2408 13695 Feature_HasNEON | 0, // VST1d16TPseudo = 2409 13696 Feature_HasNEON | 0, // VST1d16Twb_fixed = 2410 13697 Feature_HasNEON | 0, // VST1d16Twb_register = 2411 13698 Feature_HasNEON | 0, // VST1d16wb_fixed = 2412 13699 Feature_HasNEON | 0, // VST1d16wb_register = 2413 13700 Feature_HasNEON | 0, // VST1d32 = 2414 13701 Feature_HasNEON | 0, // VST1d32Q = 2415 13702 Feature_HasNEON | 0, // VST1d32QPseudo = 2416 13703 Feature_HasNEON | 0, // VST1d32Qwb_fixed = 2417 13704 Feature_HasNEON | 0, // VST1d32Qwb_register = 2418 13705 Feature_HasNEON | 0, // VST1d32T = 2419 13706 Feature_HasNEON | 0, // VST1d32TPseudo = 2420 13707 Feature_HasNEON | 0, // VST1d32Twb_fixed = 2421 13708 Feature_HasNEON | 0, // VST1d32Twb_register = 2422 13709 Feature_HasNEON | 0, // VST1d32wb_fixed = 2423 13710 Feature_HasNEON | 0, // VST1d32wb_register = 2424 13711 Feature_HasNEON | 0, // VST1d64 = 2425 13712 Feature_HasNEON | 0, // VST1d64Q = 2426 13713 Feature_HasNEON | 0, // VST1d64QPseudo = 2427 13714 Feature_HasNEON | 0, // VST1d64QPseudoWB_fixed = 2428 13715 Feature_HasNEON | 0, // VST1d64QPseudoWB_register = 2429 13716 Feature_HasNEON | 0, // VST1d64Qwb_fixed = 2430 13717 Feature_HasNEON | 0, // VST1d64Qwb_register = 2431 13718 Feature_HasNEON | 0, // VST1d64T = 2432 13719 Feature_HasNEON | 0, // VST1d64TPseudo = 2433 13720 Feature_HasNEON | 0, // VST1d64TPseudoWB_fixed = 2434 13721 Feature_HasNEON | 0, // VST1d64TPseudoWB_register = 2435 13722 Feature_HasNEON | 0, // VST1d64Twb_fixed = 2436 13723 Feature_HasNEON | 0, // VST1d64Twb_register = 2437 13724 Feature_HasNEON | 0, // VST1d64wb_fixed = 2438 13725 Feature_HasNEON | 0, // VST1d64wb_register = 2439 13726 Feature_HasNEON | 0, // VST1d8 = 2440 13727 Feature_HasNEON | 0, // VST1d8Q = 2441 13728 Feature_HasNEON | 0, // VST1d8QPseudo = 2442 13729 Feature_HasNEON | 0, // VST1d8Qwb_fixed = 2443 13730 Feature_HasNEON | 0, // VST1d8Qwb_register = 2444 13731 Feature_HasNEON | 0, // VST1d8T = 2445 13732 Feature_HasNEON | 0, // VST1d8TPseudo = 2446 13733 Feature_HasNEON | 0, // VST1d8Twb_fixed = 2447 13734 Feature_HasNEON | 0, // VST1d8Twb_register = 2448 13735 Feature_HasNEON | 0, // VST1d8wb_fixed = 2449 13736 Feature_HasNEON | 0, // VST1d8wb_register = 2450 13737 Feature_HasNEON | 0, // VST1q16 = 2451 13738 Feature_HasNEON | 0, // VST1q16HighQPseudo = 2452 13739 Feature_HasNEON | 0, // VST1q16HighTPseudo = 2453 13740 Feature_HasNEON | 0, // VST1q16LowQPseudo_UPD = 2454 13741 Feature_HasNEON | 0, // VST1q16LowTPseudo_UPD = 2455 13742 Feature_HasNEON | 0, // VST1q16wb_fixed = 2456 13743 Feature_HasNEON | 0, // VST1q16wb_register = 2457 13744 Feature_HasNEON | 0, // VST1q32 = 2458 13745 Feature_HasNEON | 0, // VST1q32HighQPseudo = 2459 13746 Feature_HasNEON | 0, // VST1q32HighTPseudo = 2460 13747 Feature_HasNEON | 0, // VST1q32LowQPseudo_UPD = 2461 13748 Feature_HasNEON | 0, // VST1q32LowTPseudo_UPD = 2462 13749 Feature_HasNEON | 0, // VST1q32wb_fixed = 2463 13750 Feature_HasNEON | 0, // VST1q32wb_register = 2464 13751 Feature_HasNEON | 0, // VST1q64 = 2465 13752 Feature_HasNEON | 0, // VST1q64HighQPseudo = 2466 13753 Feature_HasNEON | 0, // VST1q64HighTPseudo = 2467 13754 Feature_HasNEON | 0, // VST1q64LowQPseudo_UPD = 2468 13755 Feature_HasNEON | 0, // VST1q64LowTPseudo_UPD = 2469 13756 Feature_HasNEON | 0, // VST1q64wb_fixed = 2470 13757 Feature_HasNEON | 0, // VST1q64wb_register = 2471 13758 Feature_HasNEON | 0, // VST1q8 = 2472 13759 Feature_HasNEON | 0, // VST1q8HighQPseudo = 2473 13760 Feature_HasNEON | 0, // VST1q8HighTPseudo = 2474 13761 Feature_HasNEON | 0, // VST1q8LowQPseudo_UPD = 2475 13762 Feature_HasNEON | 0, // VST1q8LowTPseudo_UPD = 2476 13763 Feature_HasNEON | 0, // VST1q8wb_fixed = 2477 13764 Feature_HasNEON | 0, // VST1q8wb_register = 2478 13765 Feature_HasNEON | 0, // VST2LNd16 = 2479 13766 Feature_HasNEON | 0, // VST2LNd16Pseudo = 2480 13767 Feature_HasNEON | 0, // VST2LNd16Pseudo_UPD = 2481 13768 Feature_HasNEON | 0, // VST2LNd16_UPD = 2482 13769 Feature_HasNEON | 0, // VST2LNd32 = 2483 13770 Feature_HasNEON | 0, // VST2LNd32Pseudo = 2484 13771 Feature_HasNEON | 0, // VST2LNd32Pseudo_UPD = 2485 13772 Feature_HasNEON | 0, // VST2LNd32_UPD = 2486 13773 Feature_HasNEON | 0, // VST2LNd8 = 2487 13774 Feature_HasNEON | 0, // VST2LNd8Pseudo = 2488 13775 Feature_HasNEON | 0, // VST2LNd8Pseudo_UPD = 2489 13776 Feature_HasNEON | 0, // VST2LNd8_UPD = 2490 13777 Feature_HasNEON | 0, // VST2LNq16 = 2491 13778 Feature_HasNEON | 0, // VST2LNq16Pseudo = 2492 13779 Feature_HasNEON | 0, // VST2LNq16Pseudo_UPD = 2493 13780 Feature_HasNEON | 0, // VST2LNq16_UPD = 2494 13781 Feature_HasNEON | 0, // VST2LNq32 = 2495 13782 Feature_HasNEON | 0, // VST2LNq32Pseudo = 2496 13783 Feature_HasNEON | 0, // VST2LNq32Pseudo_UPD = 2497 13784 Feature_HasNEON | 0, // VST2LNq32_UPD = 2498 13785 Feature_HasNEON | 0, // VST2b16 = 2499 13786 Feature_HasNEON | 0, // VST2b16wb_fixed = 2500 13787 Feature_HasNEON | 0, // VST2b16wb_register = 2501 13788 Feature_HasNEON | 0, // VST2b32 = 2502 13789 Feature_HasNEON | 0, // VST2b32wb_fixed = 2503 13790 Feature_HasNEON | 0, // VST2b32wb_register = 2504 13791 Feature_HasNEON | 0, // VST2b8 = 2505 13792 Feature_HasNEON | 0, // VST2b8wb_fixed = 2506 13793 Feature_HasNEON | 0, // VST2b8wb_register = 2507 13794 Feature_HasNEON | 0, // VST2d16 = 2508 13795 Feature_HasNEON | 0, // VST2d16wb_fixed = 2509 13796 Feature_HasNEON | 0, // VST2d16wb_register = 2510 13797 Feature_HasNEON | 0, // VST2d32 = 2511 13798 Feature_HasNEON | 0, // VST2d32wb_fixed = 2512 13799 Feature_HasNEON | 0, // VST2d32wb_register = 2513 13800 Feature_HasNEON | 0, // VST2d8 = 2514 13801 Feature_HasNEON | 0, // VST2d8wb_fixed = 2515 13802 Feature_HasNEON | 0, // VST2d8wb_register = 2516 13803 Feature_HasNEON | 0, // VST2q16 = 2517 13804 Feature_HasNEON | 0, // VST2q16Pseudo = 2518 13805 Feature_HasNEON | 0, // VST2q16PseudoWB_fixed = 2519 13806 Feature_HasNEON | 0, // VST2q16PseudoWB_register = 2520 13807 Feature_HasNEON | 0, // VST2q16wb_fixed = 2521 13808 Feature_HasNEON | 0, // VST2q16wb_register = 2522 13809 Feature_HasNEON | 0, // VST2q32 = 2523 13810 Feature_HasNEON | 0, // VST2q32Pseudo = 2524 13811 Feature_HasNEON | 0, // VST2q32PseudoWB_fixed = 2525 13812 Feature_HasNEON | 0, // VST2q32PseudoWB_register = 2526 13813 Feature_HasNEON | 0, // VST2q32wb_fixed = 2527 13814 Feature_HasNEON | 0, // VST2q32wb_register = 2528 13815 Feature_HasNEON | 0, // VST2q8 = 2529 13816 Feature_HasNEON | 0, // VST2q8Pseudo = 2530 13817 Feature_HasNEON | 0, // VST2q8PseudoWB_fixed = 2531 13818 Feature_HasNEON | 0, // VST2q8PseudoWB_register = 2532 13819 Feature_HasNEON | 0, // VST2q8wb_fixed = 2533 13820 Feature_HasNEON | 0, // VST2q8wb_register = 2534 13821 Feature_HasNEON | 0, // VST3LNd16 = 2535 13822 Feature_HasNEON | 0, // VST3LNd16Pseudo = 2536 13823 Feature_HasNEON | 0, // VST3LNd16Pseudo_UPD = 2537 13824 Feature_HasNEON | 0, // VST3LNd16_UPD = 2538 13825 Feature_HasNEON | 0, // VST3LNd32 = 2539 13826 Feature_HasNEON | 0, // VST3LNd32Pseudo = 2540 13827 Feature_HasNEON | 0, // VST3LNd32Pseudo_UPD = 2541 13828 Feature_HasNEON | 0, // VST3LNd32_UPD = 2542 13829 Feature_HasNEON | 0, // VST3LNd8 = 2543 13830 Feature_HasNEON | 0, // VST3LNd8Pseudo = 2544 13831 Feature_HasNEON | 0, // VST3LNd8Pseudo_UPD = 2545 13832 Feature_HasNEON | 0, // VST3LNd8_UPD = 2546 13833 Feature_HasNEON | 0, // VST3LNq16 = 2547 13834 Feature_HasNEON | 0, // VST3LNq16Pseudo = 2548 13835 Feature_HasNEON | 0, // VST3LNq16Pseudo_UPD = 2549 13836 Feature_HasNEON | 0, // VST3LNq16_UPD = 2550 13837 Feature_HasNEON | 0, // VST3LNq32 = 2551 13838 Feature_HasNEON | 0, // VST3LNq32Pseudo = 2552 13839 Feature_HasNEON | 0, // VST3LNq32Pseudo_UPD = 2553 13840 Feature_HasNEON | 0, // VST3LNq32_UPD = 2554 13841 Feature_HasNEON | 0, // VST3d16 = 2555 13842 Feature_HasNEON | 0, // VST3d16Pseudo = 2556 13843 Feature_HasNEON | 0, // VST3d16Pseudo_UPD = 2557 13844 Feature_HasNEON | 0, // VST3d16_UPD = 2558 13845 Feature_HasNEON | 0, // VST3d32 = 2559 13846 Feature_HasNEON | 0, // VST3d32Pseudo = 2560 13847 Feature_HasNEON | 0, // VST3d32Pseudo_UPD = 2561 13848 Feature_HasNEON | 0, // VST3d32_UPD = 2562 13849 Feature_HasNEON | 0, // VST3d8 = 2563 13850 Feature_HasNEON | 0, // VST3d8Pseudo = 2564 13851 Feature_HasNEON | 0, // VST3d8Pseudo_UPD = 2565 13852 Feature_HasNEON | 0, // VST3d8_UPD = 2566 13853 Feature_HasNEON | 0, // VST3q16 = 2567 13854 Feature_HasNEON | 0, // VST3q16Pseudo_UPD = 2568 13855 Feature_HasNEON | 0, // VST3q16_UPD = 2569 13856 Feature_HasNEON | 0, // VST3q16oddPseudo = 2570 13857 Feature_HasNEON | 0, // VST3q16oddPseudo_UPD = 2571 13858 Feature_HasNEON | 0, // VST3q32 = 2572 13859 Feature_HasNEON | 0, // VST3q32Pseudo_UPD = 2573 13860 Feature_HasNEON | 0, // VST3q32_UPD = 2574 13861 Feature_HasNEON | 0, // VST3q32oddPseudo = 2575 13862 Feature_HasNEON | 0, // VST3q32oddPseudo_UPD = 2576 13863 Feature_HasNEON | 0, // VST3q8 = 2577 13864 Feature_HasNEON | 0, // VST3q8Pseudo_UPD = 2578 13865 Feature_HasNEON | 0, // VST3q8_UPD = 2579 13866 Feature_HasNEON | 0, // VST3q8oddPseudo = 2580 13867 Feature_HasNEON | 0, // VST3q8oddPseudo_UPD = 2581 13868 Feature_HasNEON | 0, // VST4LNd16 = 2582 13869 Feature_HasNEON | 0, // VST4LNd16Pseudo = 2583 13870 Feature_HasNEON | 0, // VST4LNd16Pseudo_UPD = 2584 13871 Feature_HasNEON | 0, // VST4LNd16_UPD = 2585 13872 Feature_HasNEON | 0, // VST4LNd32 = 2586 13873 Feature_HasNEON | 0, // VST4LNd32Pseudo = 2587 13874 Feature_HasNEON | 0, // VST4LNd32Pseudo_UPD = 2588 13875 Feature_HasNEON | 0, // VST4LNd32_UPD = 2589 13876 Feature_HasNEON | 0, // VST4LNd8 = 2590 13877 Feature_HasNEON | 0, // VST4LNd8Pseudo = 2591 13878 Feature_HasNEON | 0, // VST4LNd8Pseudo_UPD = 2592 13879 Feature_HasNEON | 0, // VST4LNd8_UPD = 2593 13880 Feature_HasNEON | 0, // VST4LNq16 = 2594 13881 Feature_HasNEON | 0, // VST4LNq16Pseudo = 2595 13882 Feature_HasNEON | 0, // VST4LNq16Pseudo_UPD = 2596 13883 Feature_HasNEON | 0, // VST4LNq16_UPD = 2597 13884 Feature_HasNEON | 0, // VST4LNq32 = 2598 13885 Feature_HasNEON | 0, // VST4LNq32Pseudo = 2599 13886 Feature_HasNEON | 0, // VST4LNq32Pseudo_UPD = 2600 13887 Feature_HasNEON | 0, // VST4LNq32_UPD = 2601 13888 Feature_HasNEON | 0, // VST4d16 = 2602 13889 Feature_HasNEON | 0, // VST4d16Pseudo = 2603 13890 Feature_HasNEON | 0, // VST4d16Pseudo_UPD = 2604 13891 Feature_HasNEON | 0, // VST4d16_UPD = 2605 13892 Feature_HasNEON | 0, // VST4d32 = 2606 13893 Feature_HasNEON | 0, // VST4d32Pseudo = 2607 13894 Feature_HasNEON | 0, // VST4d32Pseudo_UPD = 2608 13895 Feature_HasNEON | 0, // VST4d32_UPD = 2609 13896 Feature_HasNEON | 0, // VST4d8 = 2610 13897 Feature_HasNEON | 0, // VST4d8Pseudo = 2611 13898 Feature_HasNEON | 0, // VST4d8Pseudo_UPD = 2612 13899 Feature_HasNEON | 0, // VST4d8_UPD = 2613 13900 Feature_HasNEON | 0, // VST4q16 = 2614 13901 Feature_HasNEON | 0, // VST4q16Pseudo_UPD = 2615 13902 Feature_HasNEON | 0, // VST4q16_UPD = 2616 13903 Feature_HasNEON | 0, // VST4q16oddPseudo = 2617 13904 Feature_HasNEON | 0, // VST4q16oddPseudo_UPD = 2618 13905 Feature_HasNEON | 0, // VST4q32 = 2619 13906 Feature_HasNEON | 0, // VST4q32Pseudo_UPD = 2620 13907 Feature_HasNEON | 0, // VST4q32_UPD = 2621 13908 Feature_HasNEON | 0, // VST4q32oddPseudo = 2622 13909 Feature_HasNEON | 0, // VST4q32oddPseudo_UPD = 2623 13910 Feature_HasNEON | 0, // VST4q8 = 2624 13911 Feature_HasNEON | 0, // VST4q8Pseudo_UPD = 2625 13912 Feature_HasNEON | 0, // VST4q8_UPD = 2626 13913 Feature_HasNEON | 0, // VST4q8oddPseudo = 2627 13914 Feature_HasNEON | 0, // VST4q8oddPseudo_UPD = 2628 13915 Feature_HasVFP2 | 0, // VSTMDDB_UPD = 2629 13916 Feature_HasVFP2 | 0, // VSTMDIA = 2630 13917 Feature_HasVFP2 | 0, // VSTMDIA_UPD = 2631 13918 Feature_HasVFP2 | 0, // VSTMQIA = 2632 13919 Feature_HasVFP2 | 0, // VSTMSDB_UPD = 2633 13920 Feature_HasVFP2 | 0, // VSTMSIA = 2634 13921 Feature_HasVFP2 | 0, // VSTMSIA_UPD = 2635 13922 Feature_HasVFP2 | 0, // VSTRD = 2636 13923 Feature_HasFullFP16 | 0, // VSTRH = 2637 13924 Feature_HasVFP2 | 0, // VSTRS = 2638 13925 Feature_HasVFP2 | Feature_HasDPVFP | 0, // VSUBD = 2639 13926 Feature_HasFullFP16 | 0, // VSUBH = 2640 13927 Feature_HasNEON | 0, // VSUBHNv2i32 = 2641 13928 Feature_HasNEON | 0, // VSUBHNv4i16 = 2642 13929 Feature_HasNEON | 0, // VSUBHNv8i8 = 2643 13930 Feature_HasNEON | 0, // VSUBLsv2i64 = 2644 13931 Feature_HasNEON | 0, // VSUBLsv4i32 = 2645 13932 Feature_HasNEON | 0, // VSUBLsv8i16 = 2646 13933 Feature_HasNEON | 0, // VSUBLuv2i64 = 2647 13934 Feature_HasNEON | 0, // VSUBLuv4i32 = 2648 13935 Feature_HasNEON | 0, // VSUBLuv8i16 = 2649 13936 Feature_HasVFP2 | 0, // VSUBS = 2650 13937 Feature_HasNEON | 0, // VSUBWsv2i64 = 2651 13938 Feature_HasNEON | 0, // VSUBWsv4i32 = 2652 13939 Feature_HasNEON | 0, // VSUBWsv8i16 = 2653 13940 Feature_HasNEON | 0, // VSUBWuv2i64 = 2654 13941 Feature_HasNEON | 0, // VSUBWuv4i32 = 2655 13942 Feature_HasNEON | 0, // VSUBWuv8i16 = 2656 13943 Feature_HasNEON | 0, // VSUBfd = 2657 13944 Feature_HasNEON | 0, // VSUBfq = 2658 13945 Feature_HasNEON | Feature_HasFullFP16 | 0, // VSUBhd = 2659 13946 Feature_HasNEON | Feature_HasFullFP16 | 0, // VSUBhq = 2660 13947 Feature_HasNEON | 0, // VSUBv16i8 = 2661 13948 Feature_HasNEON | 0, // VSUBv1i64 = 2662 13949 Feature_HasNEON | 0, // VSUBv2i32 = 2663 13950 Feature_HasNEON | 0, // VSUBv2i64 = 2664 13951 Feature_HasNEON | 0, // VSUBv4i16 = 2665 13952 Feature_HasNEON | 0, // VSUBv4i32 = 2666 13953 Feature_HasNEON | 0, // VSUBv8i16 = 2667 13954 Feature_HasNEON | 0, // VSUBv8i8 = 2668 13955 Feature_HasNEON | 0, // VSWPd = 2669 13956 Feature_HasNEON | 0, // VSWPq = 2670 13957 Feature_HasNEON | 0, // VTBL1 = 2671 13958 Feature_HasNEON | 0, // VTBL2 = 2672 13959 Feature_HasNEON | 0, // VTBL3 = 2673 13960 Feature_HasNEON | 0, // VTBL3Pseudo = 2674 13961 Feature_HasNEON | 0, // VTBL4 = 2675 13962 Feature_HasNEON | 0, // VTBL4Pseudo = 2676 13963 Feature_HasNEON | 0, // VTBX1 = 2677 13964 Feature_HasNEON | 0, // VTBX2 = 2678 13965 Feature_HasNEON | 0, // VTBX3 = 2679 13966 Feature_HasNEON | 0, // VTBX3Pseudo = 2680 13967 Feature_HasNEON | 0, // VTBX4 = 2681 13968 Feature_HasNEON | 0, // VTBX4Pseudo = 2682 13969 Feature_HasVFP2 | Feature_HasDPVFP | 0, // VTOSHD = 2683 13970 Feature_HasFullFP16 | 0, // VTOSHH = 2684 13971 Feature_HasVFP2 | 0, // VTOSHS = 2685 13972 Feature_HasVFP2 | Feature_HasDPVFP | 0, // VTOSIRD = 2686 13973 Feature_HasFullFP16 | 0, // VTOSIRH = 2687 13974 Feature_HasVFP2 | 0, // VTOSIRS = 2688 13975 Feature_HasVFP2 | Feature_HasDPVFP | 0, // VTOSIZD = 2689 13976 Feature_HasFullFP16 | 0, // VTOSIZH = 2690 13977 Feature_HasVFP2 | 0, // VTOSIZS = 2691 13978 Feature_HasVFP2 | Feature_HasDPVFP | 0, // VTOSLD = 2692 13979 Feature_HasFullFP16 | 0, // VTOSLH = 2693 13980 Feature_HasVFP2 | 0, // VTOSLS = 2694 13981 Feature_HasVFP2 | Feature_HasDPVFP | 0, // VTOUHD = 2695 13982 Feature_HasFullFP16 | 0, // VTOUHH = 2696 13983 Feature_HasVFP2 | 0, // VTOUHS = 2697 13984 Feature_HasVFP2 | Feature_HasDPVFP | 0, // VTOUIRD = 2698 13985 Feature_HasFullFP16 | 0, // VTOUIRH = 2699 13986 Feature_HasVFP2 | 0, // VTOUIRS = 2700 13987 Feature_HasVFP2 | Feature_HasDPVFP | 0, // VTOUIZD = 2701 13988 Feature_HasFullFP16 | 0, // VTOUIZH = 2702 13989 Feature_HasVFP2 | 0, // VTOUIZS = 2703 13990 Feature_HasVFP2 | Feature_HasDPVFP | 0, // VTOULD = 2704 13991 Feature_HasFullFP16 | 0, // VTOULH = 2705 13992 Feature_HasVFP2 | 0, // VTOULS = 2706 13993 Feature_HasNEON | 0, // VTRNd16 = 2707 13994 Feature_HasNEON | 0, // VTRNd32 = 2708 13995 Feature_HasNEON | 0, // VTRNd8 = 2709 13996 Feature_HasNEON | 0, // VTRNq16 = 2710 13997 Feature_HasNEON | 0, // VTRNq32 = 2711 13998 Feature_HasNEON | 0, // VTRNq8 = 2712 13999 Feature_HasNEON | 0, // VTSTv16i8 = 2713 14000 Feature_HasNEON | 0, // VTSTv2i32 = 2714 14001 Feature_HasNEON | 0, // VTSTv4i16 = 2715 14002 Feature_HasNEON | 0, // VTSTv4i32 = 2716 14003 Feature_HasNEON | 0, // VTSTv8i16 = 2717 14004 Feature_HasNEON | 0, // VTSTv8i8 = 2718 14005 Feature_HasDotProd | 0, // VUDOTD = 2719 14006 Feature_HasDotProd | 0, // VUDOTDI = 2720 14007 Feature_HasDotProd | 0, // VUDOTQ = 2721 14008 Feature_HasDotProd | 0, // VUDOTQI = 2722 14009 Feature_HasVFP2 | Feature_HasDPVFP | 0, // VUHTOD = 2723 14010 Feature_HasFullFP16 | 0, // VUHTOH = 2724 14011 Feature_HasVFP2 | 0, // VUHTOS = 2725 14012 Feature_HasVFP2 | Feature_HasDPVFP | 0, // VUITOD = 2726 14013 Feature_HasFullFP16 | 0, // VUITOH = 2727 14014 Feature_HasVFP2 | 0, // VUITOS = 2728 14015 Feature_HasVFP2 | Feature_HasDPVFP | 0, // VULTOD = 2729 14016 Feature_HasFullFP16 | 0, // VULTOH = 2730 14017 Feature_HasVFP2 | 0, // VULTOS = 2731 14018 Feature_HasNEON | 0, // VUZPd16 = 2732 14019 Feature_HasNEON | 0, // VUZPd8 = 2733 14020 Feature_HasNEON | 0, // VUZPq16 = 2734 14021 Feature_HasNEON | 0, // VUZPq32 = 2735 14022 Feature_HasNEON | 0, // VUZPq8 = 2736 14023 Feature_HasNEON | 0, // VZIPd16 = 2737 14024 Feature_HasNEON | 0, // VZIPd8 = 2738 14025 Feature_HasNEON | 0, // VZIPq16 = 2739 14026 Feature_HasNEON | 0, // VZIPq32 = 2740 14027 Feature_HasNEON | 0, // VZIPq8 = 2741 14028 Feature_IsARM | 0, // sysLDMDA = 2742 14029 Feature_IsARM | 0, // sysLDMDA_UPD = 2743 14030 Feature_IsARM | 0, // sysLDMDB = 2744 14031 Feature_IsARM | 0, // sysLDMDB_UPD = 2745 14032 Feature_IsARM | 0, // sysLDMIA = 2746 14033 Feature_IsARM | 0, // sysLDMIA_UPD = 2747 14034 Feature_IsARM | 0, // sysLDMIB = 2748 14035 Feature_IsARM | 0, // sysLDMIB_UPD = 2749 14036 Feature_IsARM | 0, // sysSTMDA = 2750 14037 Feature_IsARM | 0, // sysSTMDA_UPD = 2751 14038 Feature_IsARM | 0, // sysSTMDB = 2752 14039 Feature_IsARM | 0, // sysSTMDB_UPD = 2753 14040 Feature_IsARM | 0, // sysSTMIA = 2754 14041 Feature_IsARM | 0, // sysSTMIA_UPD = 2755 14042 Feature_IsARM | 0, // sysSTMIB = 2756 14043 Feature_IsARM | 0, // sysSTMIB_UPD = 2757 14044 Feature_IsThumb2 | 0, // t2ADCri = 2758 14045 Feature_IsThumb2 | 0, // t2ADCrr = 2759 14046 Feature_IsThumb2 | 0, // t2ADCrs = 2760 14047 Feature_IsThumb2 | 0, // t2ADDri = 2761 14048 Feature_IsThumb2 | 0, // t2ADDri12 = 2762 14049 Feature_IsThumb2 | 0, // t2ADDrr = 2763 14050 Feature_IsThumb2 | 0, // t2ADDrs = 2764 14051 Feature_IsThumb2 | 0, // t2ADR = 2765 14052 Feature_IsThumb2 | 0, // t2ANDri = 2766 14053 Feature_IsThumb2 | 0, // t2ANDrr = 2767 14054 Feature_IsThumb2 | 0, // t2ANDrs = 2768 14055 Feature_IsThumb2 | 0, // t2ASRri = 2769 14056 Feature_IsThumb2 | 0, // t2ASRrr = 2770 14057 Feature_IsThumb | Feature_HasV8MBaseline | 0, // t2B = 2771 14058 Feature_IsThumb2 | 0, // t2BFC = 2772 14059 Feature_IsThumb2 | 0, // t2BFI = 2773 14060 Feature_IsThumb2 | 0, // t2BICri = 2774 14061 Feature_IsThumb2 | 0, // t2BICrr = 2775 14062 Feature_IsThumb2 | 0, // t2BICrs = 2776 14063 Feature_IsThumb2 | Feature_IsNotMClass | 0, // t2BXJ = 2777 14064 Feature_IsThumb2 | 0, // t2Bcc = 2778 14065 Feature_IsThumb2 | Feature_PreV8 | 0, // t2CDP = 2779 14066 Feature_IsThumb2 | Feature_PreV8 | 0, // t2CDP2 = 2780 14067 Feature_IsThumb | Feature_HasV7Clrex | 0, // t2CLREX = 2781 14068 Feature_IsThumb2 | 0, // t2CLZ = 2782 14069 Feature_IsThumb2 | 0, // t2CMNri = 2783 14070 Feature_IsThumb2 | 0, // t2CMNzrr = 2784 14071 Feature_IsThumb2 | 0, // t2CMNzrs = 2785 14072 Feature_IsThumb2 | 0, // t2CMPri = 2786 14073 Feature_IsThumb2 | 0, // t2CMPrr = 2787 14074 Feature_IsThumb2 | 0, // t2CMPrs = 2788 14075 Feature_IsThumb2 | Feature_IsNotMClass | 0, // t2CPS1p = 2789 14076 Feature_IsThumb2 | Feature_IsNotMClass | 0, // t2CPS2p = 2790 14077 Feature_IsThumb2 | Feature_IsNotMClass | 0, // t2CPS3p = 2791 14078 Feature_IsThumb2 | Feature_HasV8 | Feature_HasCRC | 0, // t2CRC32B = 2792 14079 Feature_IsThumb2 | Feature_HasV8 | Feature_HasCRC | 0, // t2CRC32CB = 2793 14080 Feature_IsThumb2 | Feature_HasV8 | Feature_HasCRC | 0, // t2CRC32CH = 2794 14081 Feature_IsThumb2 | Feature_HasV8 | Feature_HasCRC | 0, // t2CRC32CW = 2795 14082 Feature_IsThumb2 | Feature_HasV8 | Feature_HasCRC | 0, // t2CRC32H = 2796 14083 Feature_IsThumb2 | Feature_HasV8 | Feature_HasCRC | 0, // t2CRC32W = 2797 14084 Feature_IsThumb2 | 0, // t2DBG = 2798 14085 Feature_IsThumb2 | Feature_HasV8 | 0, // t2DCPS1 = 2799 14086 Feature_IsThumb2 | Feature_HasV8 | 0, // t2DCPS2 = 2800 14087 Feature_IsThumb2 | Feature_HasV8 | 0, // t2DCPS3 = 2801 14088 Feature_IsThumb | Feature_HasDB | 0, // t2DMB = 2802 14089 Feature_IsThumb | Feature_HasDB | 0, // t2DSB = 2803 14090 Feature_IsThumb2 | 0, // t2EORri = 2804 14091 Feature_IsThumb2 | 0, // t2EORrr = 2805 14092 Feature_IsThumb2 | 0, // t2EORrs = 2806 14093 Feature_IsThumb2 | 0, // t2HINT = 2807 14094 Feature_IsThumb2 | Feature_HasVirtualization | 0, // t2HVC = 2808 14095 Feature_IsThumb | Feature_HasDB | 0, // t2ISB = 2809 14096 Feature_IsThumb2 | 0, // t2IT = 2810 14097 Feature_IsThumb2 | Feature_HasVFP2 | 0, // t2Int_eh_sjlj_setjmp = 2811 14098 Feature_IsThumb2 | 0, // t2Int_eh_sjlj_setjmp_nofp = 2812 14099 Feature_IsThumb | Feature_HasAcquireRelease | 0, // t2LDA = 2813 14100 Feature_IsThumb | Feature_HasAcquireRelease | 0, // t2LDAB = 2814 14101 Feature_IsThumb | Feature_HasAcquireRelease | Feature_HasV7Clrex | 0, // t2LDAEX = 2815 14102 Feature_IsThumb | Feature_HasAcquireRelease | Feature_HasV7Clrex | 0, // t2LDAEXB = 2816 14103 Feature_IsThumb | Feature_HasAcquireRelease | Feature_HasV7Clrex | Feature_IsNotMClass | 0, // t2LDAEXD = 2817 14104 Feature_IsThumb | Feature_HasAcquireRelease | Feature_HasV7Clrex | 0, // t2LDAEXH = 2818 14105 Feature_IsThumb | Feature_HasAcquireRelease | 0, // t2LDAH = 2819 14106 Feature_PreV8 | Feature_IsThumb2 | 0, // t2LDC2L_OFFSET = 2820 14107 Feature_PreV8 | Feature_IsThumb2 | 0, // t2LDC2L_OPTION = 2821 14108 Feature_PreV8 | Feature_IsThumb2 | 0, // t2LDC2L_POST = 2822 14109 Feature_PreV8 | Feature_IsThumb2 | 0, // t2LDC2L_PRE = 2823 14110 Feature_PreV8 | Feature_IsThumb2 | 0, // t2LDC2_OFFSET = 2824 14111 Feature_PreV8 | Feature_IsThumb2 | 0, // t2LDC2_OPTION = 2825 14112 Feature_PreV8 | Feature_IsThumb2 | 0, // t2LDC2_POST = 2826 14113 Feature_PreV8 | Feature_IsThumb2 | 0, // t2LDC2_PRE = 2827 14114 Feature_IsThumb2 | 0, // t2LDCL_OFFSET = 2828 14115 Feature_IsThumb2 | 0, // t2LDCL_OPTION = 2829 14116 Feature_IsThumb2 | 0, // t2LDCL_POST = 2830 14117 Feature_IsThumb2 | 0, // t2LDCL_PRE = 2831 14118 Feature_IsThumb2 | 0, // t2LDC_OFFSET = 2832 14119 Feature_IsThumb2 | 0, // t2LDC_OPTION = 2833 14120 Feature_IsThumb2 | 0, // t2LDC_POST = 2834 14121 Feature_IsThumb2 | 0, // t2LDC_PRE = 2835 14122 Feature_IsThumb2 | 0, // t2LDMDB = 2836 14123 Feature_IsThumb2 | 0, // t2LDMDB_UPD = 2837 14124 Feature_IsThumb2 | 0, // t2LDMIA = 2838 14125 Feature_IsThumb2 | 0, // t2LDMIA_UPD = 2839 14126 Feature_IsThumb2 | 0, // t2LDRBT = 2840 14127 Feature_IsThumb2 | 0, // t2LDRB_POST = 2841 14128 Feature_IsThumb2 | 0, // t2LDRB_PRE = 2842 14129 Feature_IsThumb2 | 0, // t2LDRBi12 = 2843 14130 Feature_IsThumb2 | 0, // t2LDRBi8 = 2844 14131 Feature_IsThumb2 | 0, // t2LDRBpci = 2845 14132 Feature_IsThumb2 | 0, // t2LDRBs = 2846 14133 Feature_IsThumb2 | 0, // t2LDRD_POST = 2847 14134 Feature_IsThumb2 | 0, // t2LDRD_PRE = 2848 14135 Feature_IsThumb2 | 0, // t2LDRDi8 = 2849 14136 Feature_IsThumb | Feature_HasV8MBaseline | 0, // t2LDREX = 2850 14137 Feature_IsThumb | Feature_HasV8MBaseline | 0, // t2LDREXB = 2851 14138 Feature_IsThumb2 | Feature_IsNotMClass | 0, // t2LDREXD = 2852 14139 Feature_IsThumb | Feature_HasV8MBaseline | 0, // t2LDREXH = 2853 14140 Feature_IsThumb2 | 0, // t2LDRHT = 2854 14141 Feature_IsThumb2 | 0, // t2LDRH_POST = 2855 14142 Feature_IsThumb2 | 0, // t2LDRH_PRE = 2856 14143 Feature_IsThumb2 | 0, // t2LDRHi12 = 2857 14144 Feature_IsThumb2 | 0, // t2LDRHi8 = 2858 14145 Feature_IsThumb2 | 0, // t2LDRHpci = 2859 14146 Feature_IsThumb2 | 0, // t2LDRHs = 2860 14147 Feature_IsThumb2 | 0, // t2LDRSBT = 2861 14148 Feature_IsThumb2 | 0, // t2LDRSB_POST = 2862 14149 Feature_IsThumb2 | 0, // t2LDRSB_PRE = 2863 14150 Feature_IsThumb2 | 0, // t2LDRSBi12 = 2864 14151 Feature_IsThumb2 | 0, // t2LDRSBi8 = 2865 14152 Feature_IsThumb2 | 0, // t2LDRSBpci = 2866 14153 Feature_IsThumb2 | 0, // t2LDRSBs = 2867 14154 Feature_IsThumb2 | 0, // t2LDRSHT = 2868 14155 Feature_IsThumb2 | 0, // t2LDRSH_POST = 2869 14156 Feature_IsThumb2 | 0, // t2LDRSH_PRE = 2870 14157 Feature_IsThumb2 | 0, // t2LDRSHi12 = 2871 14158 Feature_IsThumb2 | 0, // t2LDRSHi8 = 2872 14159 Feature_IsThumb2 | 0, // t2LDRSHpci = 2873 14160 Feature_IsThumb2 | 0, // t2LDRSHs = 2874 14161 Feature_IsThumb2 | 0, // t2LDRT = 2875 14162 Feature_IsThumb2 | 0, // t2LDR_POST = 2876 14163 Feature_IsThumb2 | 0, // t2LDR_PRE = 2877 14164 Feature_IsThumb2 | 0, // t2LDRi12 = 2878 14165 Feature_IsThumb2 | 0, // t2LDRi8 = 2879 14166 Feature_IsThumb2 | 0, // t2LDRpci = 2880 14167 Feature_IsThumb2 | 0, // t2LDRs = 2881 14168 Feature_IsThumb2 | 0, // t2LSLri = 2882 14169 Feature_IsThumb2 | 0, // t2LSLrr = 2883 14170 Feature_IsThumb2 | 0, // t2LSRri = 2884 14171 Feature_IsThumb2 | 0, // t2LSRrr = 2885 14172 Feature_IsThumb2 | 0, // t2MCR = 2886 14173 Feature_IsThumb2 | Feature_PreV8 | 0, // t2MCR2 = 2887 14174 Feature_IsThumb2 | 0, // t2MCRR = 2888 14175 Feature_IsThumb2 | Feature_PreV8 | 0, // t2MCRR2 = 2889 14176 Feature_IsThumb2 | 0, // t2MLA = 2890 14177 Feature_IsThumb2 | 0, // t2MLS = 2891 14178 Feature_IsThumb | Feature_HasV8MBaseline | 0, // t2MOVTi16 = 2892 14179 Feature_IsThumb2 | 0, // t2MOVi = 2893 14180 Feature_IsThumb | Feature_HasV8MBaseline | 0, // t2MOVi16 = 2894 14181 Feature_IsThumb2 | 0, // t2MOVr = 2895 14182 Feature_IsThumb2 | 0, // t2MOVsra_flag = 2896 14183 Feature_IsThumb2 | 0, // t2MOVsrl_flag = 2897 14184 Feature_IsThumb2 | 0, // t2MRC = 2898 14185 Feature_IsThumb2 | Feature_PreV8 | 0, // t2MRC2 = 2899 14186 Feature_IsThumb2 | 0, // t2MRRC = 2900 14187 Feature_IsThumb2 | Feature_PreV8 | 0, // t2MRRC2 = 2901 14188 Feature_IsThumb2 | Feature_IsNotMClass | 0, // t2MRS_AR = 2902 14189 Feature_IsThumb | Feature_IsMClass | 0, // t2MRS_M = 2903 14190 Feature_IsThumb | Feature_HasVirtualization | 0, // t2MRSbanked = 2904 14191 Feature_IsThumb2 | Feature_IsNotMClass | 0, // t2MRSsys_AR = 2905 14192 Feature_IsThumb2 | Feature_IsNotMClass | 0, // t2MSR_AR = 2906 14193 Feature_IsThumb | Feature_IsMClass | 0, // t2MSR_M = 2907 14194 Feature_IsThumb | Feature_HasVirtualization | 0, // t2MSRbanked = 2908 14195 Feature_IsThumb2 | 0, // t2MUL = 2909 14196 Feature_IsThumb2 | 0, // t2MVNi = 2910 14197 Feature_IsThumb2 | 0, // t2MVNr = 2911 14198 Feature_IsThumb2 | 0, // t2MVNs = 2912 14199 Feature_IsThumb2 | 0, // t2ORNri = 2913 14200 Feature_IsThumb2 | 0, // t2ORNrr = 2914 14201 Feature_IsThumb2 | 0, // t2ORNrs = 2915 14202 Feature_IsThumb2 | 0, // t2ORRri = 2916 14203 Feature_IsThumb2 | 0, // t2ORRrr = 2917 14204 Feature_IsThumb2 | 0, // t2ORRrs = 2918 14205 Feature_HasDSP | Feature_IsThumb2 | 0, // t2PKHBT = 2919 14206 Feature_HasDSP | Feature_IsThumb2 | 0, // t2PKHTB = 2920 14207 Feature_IsThumb2 | Feature_HasV7 | Feature_HasMP | 0, // t2PLDWi12 = 2921 14208 Feature_IsThumb2 | Feature_HasV7 | Feature_HasMP | 0, // t2PLDWi8 = 2922 14209 Feature_IsThumb2 | Feature_HasV7 | Feature_HasMP | 0, // t2PLDWs = 2923 14210 Feature_IsThumb2 | 0, // t2PLDi12 = 2924 14211 Feature_IsThumb2 | 0, // t2PLDi8 = 2925 14212 Feature_IsThumb2 | 0, // t2PLDpci = 2926 14213 Feature_IsThumb2 | 0, // t2PLDs = 2927 14214 Feature_IsThumb2 | Feature_HasV7 | 0, // t2PLIi12 = 2928 14215 Feature_IsThumb2 | Feature_HasV7 | 0, // t2PLIi8 = 2929 14216 Feature_IsThumb2 | Feature_HasV7 | 0, // t2PLIpci = 2930 14217 Feature_IsThumb2 | Feature_HasV7 | 0, // t2PLIs = 2931 14218 Feature_IsThumb2 | Feature_HasDSP | 0, // t2QADD = 2932 14219 Feature_IsThumb2 | Feature_HasDSP | 0, // t2QADD16 = 2933 14220 Feature_IsThumb2 | Feature_HasDSP | 0, // t2QADD8 = 2934 14221 Feature_IsThumb2 | Feature_HasDSP | 0, // t2QASX = 2935 14222 Feature_IsThumb2 | Feature_HasDSP | 0, // t2QDADD = 2936 14223 Feature_IsThumb2 | Feature_HasDSP | 0, // t2QDSUB = 2937 14224 Feature_IsThumb2 | Feature_HasDSP | 0, // t2QSAX = 2938 14225 Feature_IsThumb2 | Feature_HasDSP | 0, // t2QSUB = 2939 14226 Feature_IsThumb2 | Feature_HasDSP | 0, // t2QSUB16 = 2940 14227 Feature_IsThumb2 | Feature_HasDSP | 0, // t2QSUB8 = 2941 14228 Feature_IsThumb2 | 0, // t2RBIT = 2942 14229 Feature_IsThumb2 | 0, // t2REV = 2943 14230 Feature_IsThumb2 | 0, // t2REV16 = 2944 14231 Feature_IsThumb2 | 0, // t2REVSH = 2945 14232 Feature_IsThumb2 | Feature_IsNotMClass | 0, // t2RFEDB = 2946 14233 Feature_IsThumb2 | Feature_IsNotMClass | 0, // t2RFEDBW = 2947 14234 Feature_IsThumb2 | Feature_IsNotMClass | 0, // t2RFEIA = 2948 14235 Feature_IsThumb2 | Feature_IsNotMClass | 0, // t2RFEIAW = 2949 14236 Feature_IsThumb2 | 0, // t2RORri = 2950 14237 Feature_IsThumb2 | 0, // t2RORrr = 2951 14238 Feature_IsThumb2 | 0, // t2RRX = 2952 14239 Feature_IsThumb2 | 0, // t2RSBri = 2953 14240 Feature_IsThumb2 | 0, // t2RSBrr = 2954 14241 Feature_IsThumb2 | 0, // t2RSBrs = 2955 14242 Feature_IsThumb2 | Feature_HasDSP | 0, // t2SADD16 = 2956 14243 Feature_IsThumb2 | Feature_HasDSP | 0, // t2SADD8 = 2957 14244 Feature_IsThumb2 | Feature_HasDSP | 0, // t2SASX = 2958 14245 Feature_IsThumb2 | 0, // t2SBCri = 2959 14246 Feature_IsThumb2 | 0, // t2SBCrr = 2960 14247 Feature_IsThumb2 | 0, // t2SBCrs = 2961 14248 Feature_IsThumb2 | 0, // t2SBFX = 2962 14249 Feature_HasDivideInThumb | Feature_IsThumb | Feature_HasV8MBaseline | 0, // t2SDIV = 2963 14250 Feature_IsThumb2 | Feature_HasDSP | 0, // t2SEL = 2964 14251 Feature_IsThumb2 | Feature_HasV8 | Feature_HasV8_1a | 0, // t2SETPAN = 2965 14252 Feature_Has8MSecExt | 0, // t2SG = 2966 14253 Feature_IsThumb2 | Feature_HasDSP | 0, // t2SHADD16 = 2967 14254 Feature_IsThumb2 | Feature_HasDSP | 0, // t2SHADD8 = 2968 14255 Feature_IsThumb2 | Feature_HasDSP | 0, // t2SHASX = 2969 14256 Feature_IsThumb2 | Feature_HasDSP | 0, // t2SHSAX = 2970 14257 Feature_IsThumb2 | Feature_HasDSP | 0, // t2SHSUB16 = 2971 14258 Feature_IsThumb2 | Feature_HasDSP | 0, // t2SHSUB8 = 2972 14259 Feature_IsThumb2 | Feature_HasTrustZone | 0, // t2SMC = 2973 14260 Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMLABB = 2974 14261 Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMLABT = 2975 14262 Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMLAD = 2976 14263 Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMLADX = 2977 14264 Feature_IsThumb2 | 0, // t2SMLAL = 2978 14265 Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMLALBB = 2979 14266 Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMLALBT = 2980 14267 Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMLALD = 2981 14268 Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMLALDX = 2982 14269 Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMLALTB = 2983 14270 Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMLALTT = 2984 14271 Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMLATB = 2985 14272 Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMLATT = 2986 14273 Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMLAWB = 2987 14274 Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMLAWT = 2988 14275 Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMLSD = 2989 14276 Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMLSDX = 2990 14277 Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMLSLD = 2991 14278 Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMLSLDX = 2992 14279 Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMMLA = 2993 14280 Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMMLAR = 2994 14281 Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMMLS = 2995 14282 Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMMLSR = 2996 14283 Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMMUL = 2997 14284 Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMMULR = 2998 14285 Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMUAD = 2999 14286 Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMUADX = 3000 14287 Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMULBB = 3001 14288 Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMULBT = 3002 14289 Feature_IsThumb2 | 0, // t2SMULL = 3003 14290 Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMULTB = 3004 14291 Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMULTT = 3005 14292 Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMULWB = 3006 14293 Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMULWT = 3007 14294 Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMUSD = 3008 14295 Feature_IsThumb2 | Feature_HasDSP | 0, // t2SMUSDX = 3009 14296 Feature_IsThumb2 | Feature_IsNotMClass | 0, // t2SRSDB = 3010 14297 Feature_IsThumb2 | Feature_IsNotMClass | 0, // t2SRSDB_UPD = 3011 14298 Feature_IsThumb2 | Feature_IsNotMClass | 0, // t2SRSIA = 3012 14299 Feature_IsThumb2 | Feature_IsNotMClass | 0, // t2SRSIA_UPD = 3013 14300 Feature_IsThumb2 | 0, // t2SSAT = 3014 14301 Feature_IsThumb2 | Feature_HasDSP | 0, // t2SSAT16 = 3015 14302 Feature_IsThumb2 | Feature_HasDSP | 0, // t2SSAX = 3016 14303 Feature_IsThumb2 | Feature_HasDSP | 0, // t2SSUB16 = 3017 14304 Feature_IsThumb2 | Feature_HasDSP | 0, // t2SSUB8 = 3018 14305 Feature_PreV8 | Feature_IsThumb2 | 0, // t2STC2L_OFFSET = 3019 14306 Feature_PreV8 | Feature_IsThumb2 | 0, // t2STC2L_OPTION = 3020 14307 Feature_PreV8 | Feature_IsThumb2 | 0, // t2STC2L_POST = 3021 14308 Feature_PreV8 | Feature_IsThumb2 | 0, // t2STC2L_PRE = 3022 14309 Feature_PreV8 | Feature_IsThumb2 | 0, // t2STC2_OFFSET = 3023 14310 Feature_PreV8 | Feature_IsThumb2 | 0, // t2STC2_OPTION = 3024 14311 Feature_PreV8 | Feature_IsThumb2 | 0, // t2STC2_POST = 3025 14312 Feature_PreV8 | Feature_IsThumb2 | 0, // t2STC2_PRE = 3026 14313 Feature_IsThumb2 | 0, // t2STCL_OFFSET = 3027 14314 Feature_IsThumb2 | 0, // t2STCL_OPTION = 3028 14315 Feature_IsThumb2 | 0, // t2STCL_POST = 3029 14316 Feature_IsThumb2 | 0, // t2STCL_PRE = 3030 14317 Feature_IsThumb2 | 0, // t2STC_OFFSET = 3031 14318 Feature_IsThumb2 | 0, // t2STC_OPTION = 3032 14319 Feature_IsThumb2 | 0, // t2STC_POST = 3033 14320 Feature_IsThumb2 | 0, // t2STC_PRE = 3034 14321 Feature_IsThumb | Feature_HasAcquireRelease | 0, // t2STL = 3035 14322 Feature_IsThumb | Feature_HasAcquireRelease | 0, // t2STLB = 3036 14323 Feature_IsThumb | Feature_HasAcquireRelease | Feature_HasV7Clrex | 0, // t2STLEX = 3037 14324 Feature_IsThumb | Feature_HasAcquireRelease | Feature_HasV7Clrex | 0, // t2STLEXB = 3038 14325 Feature_IsThumb | Feature_HasAcquireRelease | Feature_HasV7Clrex | Feature_IsNotMClass | 0, // t2STLEXD = 3039 14326 Feature_IsThumb | Feature_HasAcquireRelease | Feature_HasV7Clrex | 0, // t2STLEXH = 3040 14327 Feature_IsThumb | Feature_HasAcquireRelease | 0, // t2STLH = 3041 14328 Feature_IsThumb2 | 0, // t2STMDB = 3042 14329 Feature_IsThumb2 | 0, // t2STMDB_UPD = 3043 14330 Feature_IsThumb2 | 0, // t2STMIA = 3044 14331 Feature_IsThumb2 | 0, // t2STMIA_UPD = 3045 14332 Feature_IsThumb2 | 0, // t2STRBT = 3046 14333 Feature_IsThumb2 | 0, // t2STRB_POST = 3047 14334 Feature_IsThumb2 | 0, // t2STRB_PRE = 3048 14335 Feature_IsThumb2 | 0, // t2STRBi12 = 3049 14336 Feature_IsThumb2 | 0, // t2STRBi8 = 3050 14337 Feature_IsThumb2 | 0, // t2STRBs = 3051 14338 Feature_IsThumb2 | 0, // t2STRD_POST = 3052 14339 Feature_IsThumb2 | 0, // t2STRD_PRE = 3053 14340 Feature_IsThumb2 | 0, // t2STRDi8 = 3054 14341 Feature_IsThumb | Feature_HasV8MBaseline | 0, // t2STREX = 3055 14342 Feature_IsThumb | Feature_HasV8MBaseline | 0, // t2STREXB = 3056 14343 Feature_IsThumb2 | Feature_IsNotMClass | 0, // t2STREXD = 3057 14344 Feature_IsThumb | Feature_HasV8MBaseline | 0, // t2STREXH = 3058 14345 Feature_IsThumb2 | 0, // t2STRHT = 3059 14346 Feature_IsThumb2 | 0, // t2STRH_POST = 3060 14347 Feature_IsThumb2 | 0, // t2STRH_PRE = 3061 14348 Feature_IsThumb2 | 0, // t2STRHi12 = 3062 14349 Feature_IsThumb2 | 0, // t2STRHi8 = 3063 14350 Feature_IsThumb2 | 0, // t2STRHs = 3064 14351 Feature_IsThumb2 | 0, // t2STRT = 3065 14352 Feature_IsThumb2 | 0, // t2STR_POST = 3066 14353 Feature_IsThumb2 | 0, // t2STR_PRE = 3067 14354 Feature_IsThumb2 | 0, // t2STRi12 = 3068 14355 Feature_IsThumb2 | 0, // t2STRi8 = 3069 14356 Feature_IsThumb2 | 0, // t2STRs = 3070 14357 Feature_IsThumb2 | Feature_IsNotMClass | 0, // t2SUBS_PC_LR = 3071 14358 Feature_IsThumb2 | 0, // t2SUBri = 3072 14359 Feature_IsThumb2 | 0, // t2SUBri12 = 3073 14360 Feature_IsThumb2 | 0, // t2SUBrr = 3074 14361 Feature_IsThumb2 | 0, // t2SUBrs = 3075 14362 Feature_HasDSP | Feature_IsThumb2 | 0, // t2SXTAB = 3076 14363 Feature_HasDSP | Feature_IsThumb2 | 0, // t2SXTAB16 = 3077 14364 Feature_HasDSP | Feature_IsThumb2 | 0, // t2SXTAH = 3078 14365 Feature_IsThumb2 | 0, // t2SXTB = 3079 14366 Feature_HasDSP | Feature_IsThumb2 | 0, // t2SXTB16 = 3080 14367 Feature_IsThumb2 | 0, // t2SXTH = 3081 14368 Feature_IsThumb2 | 0, // t2TBB = 3082 14369 Feature_IsThumb2 | 0, // t2TBH = 3083 14370 Feature_IsThumb2 | 0, // t2TEQri = 3084 14371 Feature_IsThumb2 | 0, // t2TEQrr = 3085 14372 Feature_IsThumb2 | 0, // t2TEQrs = 3086 14373 Feature_IsThumb | Feature_HasV8_4a | 0, // t2TSB = 3087 14374 Feature_IsThumb2 | 0, // t2TSTri = 3088 14375 Feature_IsThumb2 | 0, // t2TSTrr = 3089 14376 Feature_IsThumb2 | 0, // t2TSTrs = 3090 14377 Feature_IsThumb | Feature_Has8MSecExt | 0, // t2TT = 3091 14378 Feature_IsThumb | Feature_Has8MSecExt | 0, // t2TTA = 3092 14379 Feature_IsThumb | Feature_Has8MSecExt | 0, // t2TTAT = 3093 14380 Feature_IsThumb | Feature_Has8MSecExt | 0, // t2TTT = 3094 14381 Feature_IsThumb2 | Feature_HasDSP | 0, // t2UADD16 = 3095 14382 Feature_IsThumb2 | Feature_HasDSP | 0, // t2UADD8 = 3096 14383 Feature_IsThumb2 | Feature_HasDSP | 0, // t2UASX = 3097 14384 Feature_IsThumb2 | 0, // t2UBFX = 3098 14385 Feature_IsThumb2 | 0, // t2UDF = 3099 14386 Feature_HasDivideInThumb | Feature_IsThumb | Feature_HasV8MBaseline | 0, // t2UDIV = 3100 14387 Feature_IsThumb2 | Feature_HasDSP | 0, // t2UHADD16 = 3101 14388 Feature_IsThumb2 | Feature_HasDSP | 0, // t2UHADD8 = 3102 14389 Feature_IsThumb2 | Feature_HasDSP | 0, // t2UHASX = 3103 14390 Feature_IsThumb2 | Feature_HasDSP | 0, // t2UHSAX = 3104 14391 Feature_IsThumb2 | Feature_HasDSP | 0, // t2UHSUB16 = 3105 14392 Feature_IsThumb2 | Feature_HasDSP | 0, // t2UHSUB8 = 3106 14393 Feature_IsThumb2 | Feature_HasDSP | 0, // t2UMAAL = 3107 14394 Feature_IsThumb2 | 0, // t2UMLAL = 3108 14395 Feature_IsThumb2 | 0, // t2UMULL = 3109 14396 Feature_IsThumb2 | Feature_HasDSP | 0, // t2UQADD16 = 3110 14397 Feature_IsThumb2 | Feature_HasDSP | 0, // t2UQADD8 = 3111 14398 Feature_IsThumb2 | Feature_HasDSP | 0, // t2UQASX = 3112 14399 Feature_IsThumb2 | Feature_HasDSP | 0, // t2UQSAX = 3113 14400 Feature_IsThumb2 | Feature_HasDSP | 0, // t2UQSUB16 = 3114 14401 Feature_IsThumb2 | Feature_HasDSP | 0, // t2UQSUB8 = 3115 14402 Feature_IsThumb2 | Feature_HasDSP | 0, // t2USAD8 = 3116 14403 Feature_IsThumb2 | Feature_HasDSP | 0, // t2USADA8 = 3117 14404 Feature_IsThumb2 | 0, // t2USAT = 3118 14405 Feature_IsThumb2 | Feature_HasDSP | 0, // t2USAT16 = 3119 14406 Feature_IsThumb2 | Feature_HasDSP | 0, // t2USAX = 3120 14407 Feature_IsThumb2 | Feature_HasDSP | 0, // t2USUB16 = 3121 14408 Feature_IsThumb2 | Feature_HasDSP | 0, // t2USUB8 = 3122 14409 Feature_HasDSP | Feature_IsThumb2 | 0, // t2UXTAB = 3123 14410 Feature_HasDSP | Feature_IsThumb2 | 0, // t2UXTAB16 = 3124 14411 Feature_HasDSP | Feature_IsThumb2 | 0, // t2UXTAH = 3125 14412 Feature_IsThumb2 | 0, // t2UXTB = 3126 14413 Feature_HasDSP | Feature_IsThumb2 | 0, // t2UXTB16 = 3127 14414 Feature_IsThumb2 | 0, // t2UXTH = 3128 14415 Feature_IsThumb | 0, // tADC = 3129 14416 Feature_IsThumb | 0, // tADDhirr = 3130 14417 Feature_IsThumb | 0, // tADDi3 = 3131 14418 Feature_IsThumb | 0, // tADDi8 = 3132 14419 Feature_IsThumb | 0, // tADDrSP = 3133 14420 Feature_IsThumb | 0, // tADDrSPi = 3134 14421 Feature_IsThumb | 0, // tADDrr = 3135 14422 Feature_IsThumb | 0, // tADDspi = 3136 14423 Feature_IsThumb | 0, // tADDspr = 3137 14424 Feature_IsThumb | 0, // tADR = 3138 14425 Feature_IsThumb | 0, // tAND = 3139 14426 Feature_IsThumb | 0, // tASRri = 3140 14427 Feature_IsThumb | 0, // tASRrr = 3141 14428 Feature_IsThumb | 0, // tB = 3142 14429 Feature_IsThumb | 0, // tBIC = 3143 14430 Feature_IsThumb | 0, // tBKPT = 3144 14431 Feature_IsThumb | 0, // tBL = 3145 14432 Feature_IsThumb | Feature_Has8MSecExt | 0, // tBLXNSr = 3146 14433 Feature_IsThumb | Feature_HasV5T | Feature_IsNotMClass | 0, // tBLXi = 3147 14434 Feature_IsThumb | Feature_HasV5T | 0, // tBLXr = 3148 14435 Feature_IsThumb | 0, // tBX = 3149 14436 Feature_IsThumb | Feature_Has8MSecExt | 0, // tBXNS = 3150 14437 Feature_IsThumb | 0, // tBcc = 3151 14438 Feature_IsThumb | Feature_HasV8MBaseline | 0, // tCBNZ = 3152 14439 Feature_IsThumb | Feature_HasV8MBaseline | 0, // tCBZ = 3153 14440 Feature_IsThumb | 0, // tCMNz = 3154 14441 Feature_IsThumb | 0, // tCMPhir = 3155 14442 Feature_IsThumb | 0, // tCMPi8 = 3156 14443 Feature_IsThumb | 0, // tCMPr = 3157 14444 Feature_IsThumb | 0, // tCPS = 3158 14445 Feature_IsThumb | 0, // tEOR = 3159 14446 Feature_IsThumb | Feature_HasV6M | 0, // tHINT = 3160 14447 Feature_IsThumb | Feature_HasV8 | 0, // tHLT = 3161 14448 Feature_IsThumb | 0, // tInt_WIN_eh_sjlj_longjmp = 3162 14449 Feature_IsThumb | 0, // tInt_eh_sjlj_longjmp = 3163 14450 Feature_IsThumb | 0, // tInt_eh_sjlj_setjmp = 3164 14451 Feature_IsThumb | 0, // tLDMIA = 3165 14452 Feature_IsThumb | 0, // tLDRBi = 3166 14453 Feature_IsThumb | 0, // tLDRBr = 3167 14454 Feature_IsThumb | 0, // tLDRHi = 3168 14455 Feature_IsThumb | 0, // tLDRHr = 3169 14456 Feature_IsThumb | 0, // tLDRSB = 3170 14457 Feature_IsThumb | 0, // tLDRSH = 3171 14458 Feature_IsThumb | 0, // tLDRi = 3172 14459 Feature_IsThumb | 0, // tLDRpci = 3173 14460 Feature_IsThumb | 0, // tLDRr = 3174 14461 Feature_IsThumb | 0, // tLDRspi = 3175 14462 Feature_IsThumb | 0, // tLSLri = 3176 14463 Feature_IsThumb | 0, // tLSLrr = 3177 14464 Feature_IsThumb | 0, // tLSRri = 3178 14465 Feature_IsThumb | 0, // tLSRrr = 3179 14466 Feature_IsThumb | 0, // tMOVSr = 3180 14467 Feature_IsThumb | 0, // tMOVi8 = 3181 14468 Feature_IsThumb | 0, // tMOVr = 3182 14469 Feature_IsThumb | 0, // tMUL = 3183 14470 Feature_IsThumb | 0, // tMVN = 3184 14471 Feature_IsThumb | 0, // tORR = 3185 14472 Feature_IsThumb | 0, // tPICADD = 3186 14473 Feature_IsThumb | 0, // tPOP = 3187 14474 Feature_IsThumb | 0, // tPUSH = 3188 14475 Feature_IsThumb | Feature_HasV6 | 0, // tREV = 3189 14476 Feature_IsThumb | Feature_HasV6 | 0, // tREV16 = 3190 14477 Feature_IsThumb | Feature_HasV6 | 0, // tREVSH = 3191 14478 Feature_IsThumb | 0, // tROR = 3192 14479 Feature_IsThumb | 0, // tRSB = 3193 14480 Feature_IsThumb | 0, // tSBC = 3194 14481 Feature_IsThumb | Feature_IsNotMClass | 0, // tSETEND = 3195 14482 Feature_IsThumb | 0, // tSTMIA_UPD = 3196 14483 Feature_IsThumb | 0, // tSTRBi = 3197 14484 Feature_IsThumb | 0, // tSTRBr = 3198 14485 Feature_IsThumb | 0, // tSTRHi = 3199 14486 Feature_IsThumb | 0, // tSTRHr = 3200 14487 Feature_IsThumb | 0, // tSTRi = 3201 14488 Feature_IsThumb | 0, // tSTRr = 3202 14489 Feature_IsThumb | 0, // tSTRspi = 3203 14490 Feature_IsThumb | 0, // tSUBi3 = 3204 14491 Feature_IsThumb | 0, // tSUBi8 = 3205 14492 Feature_IsThumb | 0, // tSUBrr = 3206 14493 Feature_IsThumb | 0, // tSUBspi = 3207 14494 Feature_IsThumb | 0, // tSVC = 3208 14495 Feature_IsThumb | Feature_HasV6 | 0, // tSXTB = 3209 14496 Feature_IsThumb | Feature_HasV6 | 0, // tSXTH = 3210 14497 Feature_IsThumb | 0, // tTRAP = 3211 14498 Feature_IsThumb | 0, // tTST = 3212 14499 Feature_IsThumb | 0, // tUDF = 3213 14500 Feature_IsThumb | Feature_HasV6 | 0, // tUXTB = 3214 14501 Feature_IsThumb | Feature_HasV6 | 0, // tUXTH = 3215 14502 Feature_IsThumb | 0, // t__brkdiv0 = 3216 14503 }; 14504 14505 assert(Inst.getOpcode() < 3217); 14506 uint64_t MissingFeatures = 14507 (AvailableFeatures & RequiredFeatures[Inst.getOpcode()]) ^ 14508 RequiredFeatures[Inst.getOpcode()]; 14509 if (MissingFeatures) { 14510 std::ostringstream Msg; 14511 Msg << "Attempting to emit " << MCII.getName(Inst.getOpcode()).str() 14512 << " instruction but the "; 14513 for (unsigned i = 0; i < 8 * sizeof(MissingFeatures); ++i) 14514 if (MissingFeatures & (1ULL << i)) 14515 Msg << SubtargetFeatureNames[i] << " "; 14516 Msg << "predicate(s) are not met"; 14517 report_fatal_error(Msg.str()); 14518 } 14519#else 14520// Silence unused variable warning on targets that don't use MCII for other purposes (e.g. BPF). 14521(void)MCII; 14522#endif // NDEBUG 14523} 14524#endif 14525