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Searched refs:AsRegisterPairLow (Results 1 – 24 of 24) sorted by relevance

/art/compiler/utils/mips/
Dmanaged_register_mips.cc30 Register low = AsRegisterPairLow(); in Overlaps()
82 os << "Pair: " << AsRegisterPairLow() << ", " << AsRegisterPairHigh(); in Print()
Dmanaged_register_mips.h116 constexpr Register AsRegisterPairLow() const { in AsRegisterPairLow() function
Dassembler_mips.cc4739 LoadFromOffset(kLoadDoubleword, dst.AsRegisterPairLow(), src_register, src_offset); in EmitLoad()
4888 StoreToOffset(kStoreWord, src.AsRegisterPairLow(), SP, dest.Int32Value()); in Store()
5015 if (src.AsRegisterPairHigh() != dest.AsRegisterPairLow()) { in Move()
5016 Move(dest.AsRegisterPairLow(), src.AsRegisterPairLow()); in Move()
5020 Move(dest.AsRegisterPairLow(), src.AsRegisterPairLow()); in Move()
/art/compiler/utils/arm/
Dmanaged_register_arm.cc29 Register low = AsRegisterPairLow(); in Overlaps()
81 os << "Pair: " << static_cast<int>(AsRegisterPairLow()) << ", " in Print()
Dmanaged_register_arm.h117 Register reg_low = AsRegisterPairLow(); in AsRegisterPair()
125 constexpr Register AsRegisterPairLow() const { in AsRegisterPairLow() function
Dmanaged_register_arm_test.cc235 EXPECT_EQ(R0, reg.AsRegisterPairLow()); in TEST()
247 EXPECT_EQ(R1, reg.AsRegisterPairLow()); in TEST()
259 EXPECT_EQ(R2, reg.AsRegisterPairLow()); in TEST()
271 EXPECT_EQ(R4, reg.AsRegisterPairLow()); in TEST()
283 EXPECT_EQ(R6, reg.AsRegisterPairLow()); in TEST()
Djni_macro_assembler_arm_vixl.cc56 return vixl::aarch32::Register(reg.AsRegisterPairLow()); in AsVIXLRegisterPairLow()
410 if (src.AsRegisterPairHigh() != dst.AsRegisterPairLow()) { in Move()
/art/compiler/utils/x86/
Dmanaged_register_x86.cc68 Register low = AsRegisterPairLow(); in Overlaps()
108 os << "Pair: " << AsRegisterPairLow() << ", " << AsRegisterPairHigh(); in Print()
Dmanaged_register_x86_test.cc124 EXPECT_EQ(EAX, reg.AsRegisterPairLow()); in TEST()
133 EXPECT_EQ(EAX, reg.AsRegisterPairLow()); in TEST()
142 EXPECT_EQ(EAX, reg.AsRegisterPairLow()); in TEST()
151 EXPECT_EQ(EAX, reg.AsRegisterPairLow()); in TEST()
160 EXPECT_EQ(EDX, reg.AsRegisterPairLow()); in TEST()
169 EXPECT_EQ(EDX, reg.AsRegisterPairLow()); in TEST()
178 EXPECT_EQ(EDX, reg.AsRegisterPairLow()); in TEST()
187 EXPECT_EQ(ECX, reg.AsRegisterPairLow()); in TEST()
196 EXPECT_EQ(ECX, reg.AsRegisterPairLow()); in TEST()
205 EXPECT_EQ(EBX, reg.AsRegisterPairLow()); in TEST()
Dmanaged_register_x86.h113 constexpr Register AsRegisterPairLow() const { in AsRegisterPairLow() function
Djni_macro_assembler_x86.cc132 __ movl(Address(ESP, offs), src.AsRegisterPairLow()); in Store()
195 __ movl(dest.AsRegisterPairLow(), Address(ESP, src)); in Load()
226 __ fs()->movl(dest.AsRegisterPairLow(), Address::Absolute(src)); in LoadFromThread()
/art/compiler/utils/x86_64/
Dmanaged_register_x86_64.cc63 Register low = AsRegisterPairLow().AsRegister(); in Overlaps()
103 os << "Pair: " << AsRegisterPairLow() << ", " << AsRegisterPairHigh(); in Print()
Dmanaged_register_x86_64_test.cc123 EXPECT_EQ(RAX, reg.AsRegisterPairLow()); in TEST()
132 EXPECT_EQ(RAX, reg.AsRegisterPairLow()); in TEST()
141 EXPECT_EQ(RAX, reg.AsRegisterPairLow()); in TEST()
150 EXPECT_EQ(RAX, reg.AsRegisterPairLow()); in TEST()
159 EXPECT_EQ(RDX, reg.AsRegisterPairLow()); in TEST()
168 EXPECT_EQ(RDX, reg.AsRegisterPairLow()); in TEST()
177 EXPECT_EQ(RDX, reg.AsRegisterPairLow()); in TEST()
186 EXPECT_EQ(RCX, reg.AsRegisterPairLow()); in TEST()
195 EXPECT_EQ(RCX, reg.AsRegisterPairLow()); in TEST()
204 EXPECT_EQ(RBX, reg.AsRegisterPairLow()); in TEST()
Dmanaged_register_x86_64.h106 constexpr CpuRegister AsRegisterPairLow() const { in AsRegisterPairLow() function
Djni_macro_assembler_x86_64.cc168 __ movq(Address(CpuRegister(RSP), offs), src.AsRegisterPairLow()); in Store()
239 __ movq(dest.AsRegisterPairLow(), Address(CpuRegister(RSP), src)); in Load()
271 __ gs()->movq(dest.AsRegisterPairLow(), Address::Absolute(src, true)); in LoadFromThread()
/art/compiler/optimizing/
Dintrinsics_mips.cc170 Register out_lo = locations->Out().AsRegisterPairLow<Register>(); in MoveFPToInt()
211 Register in_lo = locations->InAt(0).AsRegisterPairLow<Register>(); in MoveIntToFP()
321 Register in_lo = locations->InAt(0).AsRegisterPairLow<Register>(); in GenReverse()
323 Register out_lo = locations->Out().AsRegisterPairLow<Register>(); in GenReverse()
452 Register in_lo = locations->InAt(0).AsRegisterPairLow<Register>(); in GenNumberOfLeadingZeroes()
505 in_lo = locations->InAt(0).AsRegisterPairLow<Register>(); in GenNumberOfTrailingZeroes()
653 Register in_lo = locations->InAt(0).AsRegisterPairLow<Register>(); in GenBitCount()
686 Register in_lo = locations->InAt(0).AsRegisterPairLow<Register>(); in GenBitCount()
788 Register adr = invoke->GetLocations()->InAt(0).AsRegisterPairLow<Register>(); in VisitMemoryPeekByte()
801 Register adr = invoke->GetLocations()->InAt(0).AsRegisterPairLow<Register>(); in VisitMemoryPeekShortNative()
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Dcode_generator_x86.cc1201 return Location::RegisterPairLocation(pair.AsRegisterPairLow(), pair.AsRegisterPairHigh()); in GetNextLocation()
1286 Location::RegisterLocation(source.AsRegisterPairLow<Register>()), in Move64()
1287 Location::RegisterLocation(destination.AsRegisterPairLow<Register>()), in Move64()
1291 __ movd(destination.AsRegisterPairLow<Register>(), src_reg); in Move64()
1297 __ movl(destination.AsRegisterPairLow<Register>(), Address(ESP, source.GetStackIndex())); in Move64()
1310 __ movl(Address(ESP, 0), source.AsRegisterPairLow<Register>()); in Move64()
1322 __ movl(Address(ESP, destination.GetStackIndex()), source.AsRegisterPairLow<Register>()); in Move64()
1367 locations->AddTemp(Location::RegisterLocation(location.AsRegisterPairLow<Register>())); in AddLocationAsTemp()
1451 Register left_low = left.AsRegisterPairLow<Register>(); in GenerateLongComparesAndJumps()
1507 Register right_low = right.AsRegisterPairLow<Register>(); in GenerateLongComparesAndJumps()
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Dintrinsics_x86.cc201 __ movd(output.AsRegisterPairLow<Register>(), temp); in MoveFPToInt()
216 __ movd(temp1, input.AsRegisterPairLow<Register>()); in MoveIntToFP()
309 Register input_lo = input.AsRegisterPairLow<Register>(); in VisitLongReverseBytes()
312 Register output_lo = output.AsRegisterPairLow<Register>(); in VisitLongReverseBytes()
572 __ xorl(out_loc.AsRegisterPairLow<Register>(), out_loc.AsRegisterPairLow<Register>()); in GenLowestOneBit()
585 codegen->Load32BitValue(out_loc.AsRegisterPairLow<Register>(), 0); in GenLowestOneBit()
588 codegen->Load32BitValue(out_loc.AsRegisterPairLow<Register>(), 1 << value); in GenLowestOneBit()
599 Register src_lo = src.AsRegisterPairLow<Register>(); in GenLowestOneBit()
602 Register out_lo = out_loc.AsRegisterPairLow<Register>(); in GenLowestOneBit()
1518 Register address = locations->InAt(0).AsRegisterPairLow<Register>(); in GenPeek()
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Dcode_generator_mips.cc707 Register offset = field_offset_.AsRegisterPairLow<Register>(); in EmitNativeCode()
1140 Register r1 = loc1.AsRegisterPairLow<Register>(); in EmitSwap()
1141 Register r2 = loc2.AsRegisterPairLow<Register>(); in EmitSwap()
1156 Register r2_l = loc1.IsRegisterPair() ? loc1.AsRegisterPairLow<Register>() in EmitSwap()
1157 : loc2.AsRegisterPairLow<Register>(); in EmitSwap()
1184 Register reg_l = loc1.IsRegisterPair() ? loc1.AsRegisterPairLow<Register>() in EmitSwap()
1185 : loc2.AsRegisterPairLow<Register>(); in EmitSwap()
1438 __ Move(destination.AsRegisterPairLow<Register>(), source.AsRegisterPairLow<Register>()); in MoveLocation()
1441 Register dst_low = destination.AsRegisterPairLow<Register>(); in MoveLocation()
1449 Register r = destination.AsRegisterPairLow<Register>(); in MoveLocation()
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Dcommon_arm.h61 return vixl::aarch32::Register(location.AsRegisterPairLow<vixl::aarch32::Register>()); in LowRegisterFrom()
Dlocations.h193 T AsRegisterPairLow() const { in AsRegisterPairLow() function
Dcode_generator_vector_x86.cc97 __ movd(dst, locations->InAt(0).AsRegisterPairLow<Register>()); in VisitVecReplicateScalar()
165 __ movd(locations->Out().AsRegisterPairLow<Register>(), src); in VisitVecExtractScalar()
1073 __ movd(dst, locations->InAt(0).AsRegisterPairLow<Register>()); in VisitVecSetScalars()
Dcode_generator_vector_mips.cc72 locations->InAt(0).AsRegisterPairLow<Register>(), in VisitVecReplicateScalar()
131 __ Copy_sW(locations->Out().AsRegisterPairLow<Register>(), src, 0); in VisitVecExtractScalar()
1004 __ InsertW(dst, locations->InAt(0).AsRegisterPairLow<Register>(), 0); in VisitVecSetScalars()
Dcode_generator.cc850 DCHECK(is_out || !blocked_core_registers_[location.AsRegisterPairLow<int>()]); in BlockIfInRegister()
851 blocked_core_registers_[location.AsRegisterPairLow<int>()] = true; in BlockIfInRegister()