| /art/compiler/utils/mips/ |
| D | assembler_mips_test.cc | 2187 TEST_F(AssemblerMIPSTest, Beq) { in TEST_F() argument
2188 BranchCondTwoRegsHelper(&mips::MipsAssembler::Beq, "Beq"); in TEST_F()
2252 BranchCondTwoRegsHelper(&mips::MipsAssembler::Beq, "Beq", /* is_bare= */ true); in TEST_F()
2368 __ Beq(mips::T1, mips::T2, &label2); // No preceding or target instruction for the delay slot. in TEST_F() local
2743 __ Beq(mips::A0, mips::A1, &label1); in TEST_F() local
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| D | assembler_mips32r6_test.cc | 1152 TEST_F(AssemblerMIPS32r6Test, Beq) { in TEST_F() argument
1153 BranchCondTwoRegsHelper(&mips::MipsAssembler::Beq, "Beqc"); in TEST_F()
1273 BranchCondTwoRegsHelper(&mips::MipsAssembler::Beq, "Beq", /* is_bare= */ true); in TEST_F()
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| D | assembler_mips.h | 396 void Beq(Register rs, Register rt, uint16_t imm16);
801 void Beq(Register rs, Register rt, MipsLabel* label, bool is_bare = false);
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| D | assembler_mips.cc | 876 void MipsAssembler::Beq(Register rs, Register rt, uint16_t imm16) { in Beq() function in art::mips::MipsAssembler
885 Beq(rt, ZERO, imm16); in Beqz()
1127 Beq(rs, rt, imm16); in EmitBcondR2()
4310 void MipsAssembler::Beq(Register rs, Register rt, MipsLabel* label, bool is_bare) { in Beq() function in art::mips::MipsAssembler
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| /art/compiler/optimizing/ |
| D | intrinsics_mips.cc | 1571 __ Beq(str, arg, &return_true); in VisitStringEquals() local
2148 __ Beq(srcEnd, srcBegin, &done); // No characters to move. in VisitStringGetCharsNoCheck() local
2528 __ Beq(src, dest, slow_path->GetEntryLabel()); in VisitSystemArrayCopyChar() local
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| D | code_generator_mips.cc | 694 __ Beq(temp1_, ref_reg, &done); in EmitNativeCode() local
3160 __ Beq(temp1, temp2, &do_put); in VisitArraySet() local
3508 __ Beq(temp, cls.AsRegister<Register>(), &done); in VisitCheckCast() local
3531 __ Beq(temp, cls.AsRegister<Register>(), &done); in VisitCheckCast() local
4699 __ Beq(lhs, rhs_reg, label); in GenerateIntCompareAndBranch() local
4734 __ Beq(lhs, TMP, label); in GenerateIntCompareAndBranch() local
7651 __ Beq(out, cls.AsRegister<Register>(), &success); in VisitInstanceOf() local
7678 __ Beq(out, cls.AsRegister<Register>(), &success); in VisitInstanceOf() local
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| /art/compiler/utils/mips64/ |
| D | assembler_mips64.cc | 829 void Mips64Assembler::Beq(GpuRegister rs, GpuRegister rt, uint16_t imm16) { in Beq() function in art::mips64::Mips64Assembler
838 Beq(rt, ZERO, imm16); in Beqz()
950 Beq(rs, rt, imm16); in EmitBcondR2()
3356 void Mips64Assembler::Beq(GpuRegister rs, GpuRegister rt, Mips64Label* label, bool is_bare) { in Beq() function in art::mips64::Mips64Assembler
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| D | assembler_mips64.h | 571 void Beq(GpuRegister rs, GpuRegister rt, uint16_t imm16); // R2
1031 void Beq(GpuRegister rs, GpuRegister rt, Mips64Label* label, bool is_bare = false); // R2
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| D | assembler_mips64_test.cc | 943 BranchCondTwoRegsHelper(&mips64::Mips64Assembler::Beq, "Beq", /* is_bare= */ true); in TEST_F()
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