| /art/compiler/utils/arm64/ |
| D | assembler_arm64.cc | 106 static inline dwarf::Reg DWARFReg(CPURegister reg) { in DWARFReg() function
124 cfi_.RelOffset(DWARFReg(dst0), offset); in SpillRegisters()
131 cfi_.RelOffset(DWARFReg(dst0), offset); in SpillRegisters()
132 cfi_.RelOffset(DWARFReg(dst1), offset + size); in SpillRegisters()
138 cfi_.RelOffset(DWARFReg(dst0), offset); in SpillRegisters()
150 cfi_.Restore(DWARFReg(dst0)); in UnspillRegisters()
157 cfi_.Restore(DWARFReg(dst0)); in UnspillRegisters()
158 cfi_.Restore(DWARFReg(dst1)); in UnspillRegisters()
164 cfi_.Restore(DWARFReg(dst0)); in UnspillRegisters()
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| /art/compiler/utils/x86_64/ |
| D | jni_macro_assembler_x86_64.cc | 27 static dwarf::Reg DWARFReg(Register reg) { in DWARFReg() function
30 static dwarf::Reg DWARFReg(FloatRegister reg) { in DWARFReg() function
52 cfi().RelOffset(DWARFReg(spill.AsCpuRegister().AsRegister()), 0); in BuildFrame()
69 cfi().RelOffset(DWARFReg(spill.AsXmmRegister().AsFloatRegister()), offset); in BuildFrame()
116 cfi().Restore(DWARFReg(spill.AsXmmRegister().AsFloatRegister())); in RemoveFrame()
129 cfi().Restore(DWARFReg(spill.AsCpuRegister().AsRegister())); in RemoveFrame()
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| /art/compiler/optimizing/ |
| D | common_arm.h | 41 inline dwarf::Reg DWARFReg(vixl::aarch32::Register reg) { in DWARFReg() function
45 inline dwarf::Reg DWARFReg(vixl::aarch32::SRegister reg) { in DWARFReg() function
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| D | code_generator_mips64.cc | 1081 static dwarf::Reg DWARFReg(GpuRegister reg) { in DWARFReg() function
1085 static dwarf::Reg DWARFReg(FpuRegister reg) { in DWARFReg() function
1130 __ cfi().RelOffset(DWARFReg(reg), ofs); in GenerateFrameEntry()
1139 __ cfi().RelOffset(DWARFReg(reg), ofs); in GenerateFrameEntry()
1169 __ cfi().Restore(DWARFReg(reg)); in GenerateFrameExit()
1178 __ cfi().Restore(DWARFReg(reg)); in GenerateFrameExit()
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| D | code_generator_x86_64.cc | 1332 static dwarf::Reg DWARFReg(Register reg) { in DWARFReg() function
1336 static dwarf::Reg DWARFReg(FloatRegister reg) { in DWARFReg() function
1368 __ cfi().RelOffset(DWARFReg(reg), 0); in GenerateFrameEntry()
1382 __ cfi().RelOffset(DWARFReg(kFpuCalleeSaves[i]), offset); in GenerateFrameEntry()
1409 __ cfi().Restore(DWARFReg(kFpuCalleeSaves[i])); in GenerateFrameExit()
1422 __ cfi().Restore(DWARFReg(reg)); in GenerateFrameExit()
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| D | code_generator_arm_vixl.cc | 50 using helpers::DWARFReg;
2130 GetAssembler()->cfi().RelOffsetForMany(DWARFReg(kMethodRegister), in GenerateFrameEntry()
2142 GetAssembler()->cfi().RelOffsetForMany(DWARFReg(s0), 0, fpu_spill_mask_, kArmWordSize); in GenerateFrameEntry()
2185 GetAssembler()->cfi().RestoreMany(DWARFReg(vixl32::SRegister(0)), fpu_spill_mask_); in GenerateFrameExit()
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| D | code_generator_x86.cc | 1069 static dwarf::Reg DWARFReg(Register reg) { in DWARFReg() function
1100 __ cfi().RelOffset(DWARFReg(reg), 0); in GenerateFrameEntry()
1132 __ cfi().Restore(DWARFReg(reg)); in GenerateFrameExit()
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| D | code_generator_mips.cc | 1282 static dwarf::Reg DWARFReg(Register reg) { in DWARFReg() function
1333 __ cfi().RelOffset(DWARFReg(reg), ofs); in GenerateFrameEntry()
1373 __ cfi().Restore(DWARFReg(reg)); in GenerateFrameExit()
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| /art/compiler/utils/arm/ |
| D | jni_macro_assembler_arm_vixl.cc | 71 static dwarf::Reg DWARFReg(vixl32::Register reg) { in DWARFReg() function
75 static dwarf::Reg DWARFReg(vixl32::SRegister reg) { in DWARFReg() function
100 cfi().RelOffsetForMany(DWARFReg(r0), 0, core_spill_mask, kFramePointerSize); in BuildFrame()
109 cfi().RelOffsetForMany(DWARFReg(s0), 0, fp_spill_mask, kFramePointerSize); in BuildFrame()
171 cfi().RestoreMany(DWARFReg(s0), fp_spill_mask); in RemoveFrame()
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| /art/compiler/utils/x86/ |
| D | jni_macro_assembler_x86.cc | 36 static dwarf::Reg DWARFReg(Register reg) { in DWARFReg() function
57 cfi().RelOffset(DWARFReg(spill), 0); in BuildFrame()
99 cfi().Restore(DWARFReg(spill)); in RemoveFrame()
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| /art/compiler/utils/mips64/ |
| D | assembler_mips64.cc | 3604 static dwarf::Reg DWARFReg(GpuRegister reg) { in DWARFReg() function
3623 cfi_.RelOffset(DWARFReg(RA), stack_offset); in BuildFrame()
3628 cfi_.RelOffset(DWARFReg(reg), stack_offset); in BuildFrame()
3666 cfi_.Restore(DWARFReg(reg)); in RemoveFrame()
3670 cfi_.Restore(DWARFReg(RA)); in RemoveFrame()
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| /art/compiler/utils/mips/ |
| D | assembler_mips.cc | 4772 static dwarf::Reg DWARFReg(Register reg) { in DWARFReg() function
4791 cfi_.RelOffset(DWARFReg(RA), stack_offset); in BuildFrame()
4796 cfi_.RelOffset(DWARFReg(reg), stack_offset); in BuildFrame()
4833 cfi_.Restore(DWARFReg(reg)); in RemoveFrame()
4837 cfi_.Restore(DWARFReg(RA)); in RemoveFrame()
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