| /art/compiler/optimizing/ |
| D | intrinsics_mips.cc | 1886 __ Srlv(out_hi, AT, TMP); in GenHighestOneBit() local
1893 __ Srlv(out_lo, AT, TMP); in GenHighestOneBit() local
1910 __ Srlv(AT, AT, TMP); // Srlv shifts in the range of [0;31] bits (lower 5 bits of arg). in GenHighestOneBit() local
|
| D | code_generator_mips.cc | 2464 __ Srlv(dst, lhs, rhs_reg); in HandleShift() local
2476 __ Srlv(dst, lhs, rhs_reg); in HandleShift() local
2577 __ Srlv(TMP, TMP, AT); in HandleShift() local
2594 __ Srlv(dst_low, lhs_low, rhs_reg); in HandleShift() local
2607 __ Srlv(dst_high, lhs_high, rhs_reg); in HandleShift() local
2611 __ Srlv(dst_low, lhs_low, rhs_reg); in HandleShift() local
2624 __ Srlv(TMP, lhs_low, rhs_reg); in HandleShift() local
2628 __ Srlv(TMP, lhs_high, rhs_reg); in HandleShift() local
|
| D | intrinsics_mips64.cc | 1990 __ Srlv(AT, AT, TMP); in GenHighestOneBit() local
|
| D | code_generator_mips64.cc | 2234 __ Srlv(dst, lhs, rhs_reg); in HandleShift() local
|
| /art/compiler/utils/mips/ |
| D | assembler_mips_test.cc | 474 TEST_F(AssemblerMIPSTest, Srlv) { in TEST_F() argument
475 DriverStr(RepeatRRR(&mips::MipsAssembler::Srlv, "srlv ${reg1}, ${reg2}, ${reg3}"), "Srlv"); in TEST_F()
|
| D | assembler_mips.h | 348 void Srlv(Register rd, Register rt, Register rs);
|
| D | assembler_mips.cc | 666 void MipsAssembler::Srlv(Register rd, Register rt, Register rs) { in Srlv() function in art::mips::MipsAssembler
|
| /art/compiler/utils/mips64/ |
| D | assembler_mips64_test.cc | 1444 TEST_F(AssemblerMIPS64Test, Srlv) { in TEST_F() argument
1445 DriverStr(RepeatRRR(&mips64::Mips64Assembler::Srlv, "srlv ${reg1}, ${reg2}, ${reg3}"), "srlv"); in TEST_F()
|
| D | assembler_mips64.h | 499 void Srlv(GpuRegister rd, GpuRegister rt, GpuRegister rs);
|
| D | assembler_mips64.cc | 531 void Mips64Assembler::Srlv(GpuRegister rd, GpuRegister rt, GpuRegister rs) { in Srlv() function in art::mips64::Mips64Assembler
|