| /art/compiler/trampolines/ |
| D | trampoline_compiler.cc | 146 __ LoadFromOffset(kLoadWord, T9, A0, offset.Int32Value()); in CreateTrampoline()
149 __ LoadFromOffset(kLoadWord, T9, A0, JNIEnvExt::SelfOffset(4).Int32Value()); in CreateTrampoline()
150 __ LoadFromOffset(kLoadWord, T9, T9, offset.Int32Value()); in CreateTrampoline()
153 __ LoadFromOffset(kLoadWord, T9, S1, offset.Int32Value()); in CreateTrampoline()
155 __ Jr(T9); in CreateTrampoline()
178 __ LoadFromOffset(kLoadDoubleword, T9, A0, offset.Int32Value()); in CreateTrampoline()
181 __ LoadFromOffset(kLoadDoubleword, T9, A0, JNIEnvExt::SelfOffset(8).Int32Value()); in CreateTrampoline()
182 __ LoadFromOffset(kLoadDoubleword, T9, T9, offset.Int32Value()); in CreateTrampoline()
185 __ LoadFromOffset(kLoadDoubleword, T9, S1, offset.Int32Value()); in CreateTrampoline()
187 __ Jr(T9); in CreateTrampoline()
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| /art/runtime/arch/mips/ |
| D | context_mips.cc | 32 gprs_[T9] = &t9_; in Reset()
36 t9_ = MipsContext::kBadGprBase + T9; in Reset()
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| D | context_mips.h | 45 SetGPR(T9, new_pc); in SetPC()
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| D | registers_mips.h | 53 T9 = 25, enumerator
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| D | fault_handler_mips.cc | 143 sc->sc_regs[mips::T9] = sc->sc_pc; // make sure T9 points to the function in Action()
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| D | callee_save_frame_mips.h | 62 (1 << art::mips::S0) | (1 << art::mips::S1) | (1 << art::mips::T8) | (1 << art::mips::T9);
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| /art/runtime/arch/mips64/ |
| D | context_mips64.cc | 32 gprs_[T9] = &t9_; in Reset()
36 t9_ = Mips64Context::kBadGprBase + T9; in Reset()
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| D | context_mips64.h | 45 SetGPR(T9, new_pc); in SetPC()
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| D | registers_mips64.h | 53 T9 = 25, enumerator
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| D | fault_handler_mips64.cc | 145 sc->sc_regs[mips64::T9] = sc->sc_pc; // make sure T9 points to the function in Action()
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| D | callee_save_frame_mips64.h | 50 (1 << art::mips64::T9);
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| /art/compiler/jni/quick/mips64/ |
| D | calling_convention_mips64.cc | 68 return Mips64ManagedRegister::FromGpuRegister(T9); in InterproceduralScratchRegister()
72 return Mips64ManagedRegister::FromGpuRegister(T9); in InterproceduralScratchRegister()
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| /art/compiler/jni/quick/mips/ |
| D | calling_convention_mips.cc | 79 return MipsManagedRegister::FromCoreRegister(T9); in InterproceduralScratchRegister()
83 return MipsManagedRegister::FromCoreRegister(T9); in InterproceduralScratchRegister()
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| /art/compiler/utils/mips/ |
| D | assembler_mips_test.cc | 97 registers_.push_back(new mips::Register(mips::T9)); in SetUpHelpers()
130 secondary_register_names_.emplace(mips::Register(mips::T9), "t9"); in SetUpHelpers()
2342 __ LlR2(mips::T9, mips::T0, 0); in TEST_F()
2343 __ Jalr(mips::T9); // T9 dependency. in TEST_F()
2346 __ Jalr(mips::T9); // RA dependency. in TEST_F()
2349 __ Jalr(mips::T1, mips::T9); // T1 dependency. in TEST_F()
2351 __ ScR2(mips::T9, mips::T0, 0); in TEST_F()
2352 __ Jr(mips::T9); // T9 dependency. in TEST_F()
2364 __ Jalr(mips::T9); // No preceding instruction for the delay slot. in TEST_F()
2486 __ Jalr(mips::T9); in TEST_F()
[all …]
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| D | assembler_mips32r5_test.cc | 116 registers_.push_back(new mips::Register(mips::T9)); in SetUpHelpers()
149 secondary_register_names_.emplace(mips::Register(mips::T9), "t9"); in SetUpHelpers()
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| D | assembler_mips32r6_test.cc | 129 registers_.push_back(new mips::Register(mips::T9)); in SetUpHelpers()
162 secondary_register_names_.emplace(mips::Register(mips::T9), "t9"); in SetUpHelpers()
1570 __ Jalr(mips::T9); in TEST_F()
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| D | assembler_mips.cc | 5250 LoadFromOffset(kLoadWord, T9, S1, in EmitExceptionPoll()
5252 Jr(T9); in EmitExceptionPoll()
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| /art/compiler/optimizing/ |
| D | code_generator_mips.cc | 580 DCHECK_EQ(entrypoint_.AsRegister<Register>(), T9); in EmitNativeCode()
1923 blocked_core_registers_[T9] = true; in SetupBlockedRegisters()
2004 __ LoadFromOffset(kLoadWord, T9, TR, entry_point_offset); in GenerateInvokeRuntime()
2005 __ Jalr(T9); in GenerateInvokeRuntime()
7057 __ LoadFromOffset(kLoadWord, T9, TR, entry_point_offset); in GenerateGcRootFieldLoad()
7064 __ Beqz(T9, &skip_call, /* is_bare= */ true); in GenerateGcRootFieldLoad()
7073 __ Jialc(T9, thunk_disp); in GenerateGcRootFieldLoad()
7075 __ Addiu(T9, T9, thunk_disp); in GenerateGcRootFieldLoad()
7076 __ Jalr(T9); in GenerateGcRootFieldLoad()
7112 Location temp = Location::RegisterLocation(T9); in GenerateGcRootFieldLoad()
[all …]
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| D | code_generator_mips64.cc | 537 DCHECK_EQ(entrypoint_.AsRegister<GpuRegister>(), T9); in EmitNativeCode()
1790 blocked_core_registers_[T9] = true; in SetupBlockedRegisters()
1859 __ LoadFromOffset(kLoadDoubleword, T9, TR, entry_point_offset); in GenerateInvokeRuntime()
1860 __ Jalr(T9); in GenerateInvokeRuntime()
5227 __ LoadFromOffset(kLoadDoubleword, T9, TR, entry_point_offset); in GenerateGcRootFieldLoad()
5233 __ Beqz(T9, &skip_call, /* is_bare= */ true); in GenerateGcRootFieldLoad()
5241 __ Jialc(T9, thunk_disp); in GenerateGcRootFieldLoad()
5270 Location temp = Location::RegisterLocation(T9); in GenerateGcRootFieldLoad()
5359 __ LoadFromOffset(kLoadDoubleword, T9, TR, entry_point_offset); in GenerateFieldLoadWithBakerReadBarrier()
5363 __ Beqzc(T9, &skip_call, /* is_bare= */ true); in GenerateFieldLoadWithBakerReadBarrier()
[all …]
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| /art/compiler/utils/mips64/ |
| D | assembler_mips64_test.cc | 127 registers_.push_back(new mips64::GpuRegister(mips64::T9)); in SetUpHelpers()
160 secondary_register_names_.emplace(mips64::GpuRegister(mips64::T9), "t9"); in SetUpHelpers()
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| D | assembler_mips64.cc | 4090 T9, in EmitExceptionPoll()
4093 Jr(T9); in EmitExceptionPoll()
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