| /art/disassembler/ |
| D | disassembler_arm64.cc | 37 TR = 19, enumerator
48 if (reg.GetCode() == TR) { in AppendRegisterNameToOutput()
103 if (instr->GetRn() == TR) { in VisitLoadStoreUnsignedOffset()
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| D | disassembler_arm.cc | 40 static const vixl::aarch32::Register tr(TR);
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| /art/cmdline/detail/ |
| D | cmdline_parser_detail.h | 54 template <typename TL, typename TR>
55 static std::true_type EqualityOperatorTest(const TL& left, const TR& right,
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| /art/compiler/utils/arm64/ |
| D | jni_macro_assembler_arm64.cc | 51 ___ Mov(reg_x(tr.AsArm64().AsXRegister()), reg_x(TR)); in GetCurrentThread()
55 StoreToOffset(TR, SP, offset.Int32Value()); in GetCurrentThread()
173 StoreToOffset(scratch.AsXRegister(), TR, tr_offs.Int32Value()); in StoreStackOffsetToThread()
180 ___ Str(temp, MEM_OP(reg_x(TR), tr_offs.Int32Value())); in StoreStackPointerToThread()
288 return Load(m_dst.AsArm64(), TR, src.Int32Value(), size); in LoadFromThread()
327 LoadFromOffset(dst.AsXRegister(), TR, offs.Int32Value()); in LoadRawPtrFromThread()
365 LoadFromOffset(scratch.AsXRegister(), TR, tr_offs.Int32Value()); in CopyRawPtrFromThread()
375 StoreToOffset(scratch.AsXRegister(), TR, tr_offs.Int32Value()); in CopyRawPtrToThread()
627 TR, in ExceptionPoll()
678 MEM_OP(reg_x(TR), in EmitExceptionPoll()
[all …]
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| D | assembler_arm64.cc | 199 vixl::aarch64::Register tr = reg_x(TR); // Thread Register. in GenerateMarkingRegisterCheck()
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| D | managed_register_arm64_test.cc | 627 EXPECT_TRUE(vixl::aarch64::x19.Is(Arm64Assembler::reg_x(TR))); in TEST()
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| /art/runtime/arch/arm/ |
| D | registers_arm.h | 44 TR = 9, // ART Thread Register enumerator
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| D | context_arm.cc | 112 DCHECK_EQ(reinterpret_cast<uintptr_t>(Thread::Current()), gprs[TR]); in DoLongJump()
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| /art/runtime/arch/mips/ |
| D | registers_mips.h | 60 TR = S1, // ART Thread Register enumerator
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| /art/runtime/arch/mips64/ |
| D | registers_mips64.h | 60 TR = S1, // ART Thread Register enumerator
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| /art/runtime/arch/arm64/ |
| D | registers_arm64.h | 63 TR = X19, // ART Thread Register - Managed Runtime (Callee Saved Reg) enumerator
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| D | context_arm64.cc | 147 DCHECK_EQ(reinterpret_cast<uintptr_t>(Thread::Current()), gprs[TR]); in DoLongJump()
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| /art/compiler/trampolines/ |
| D | trampoline_compiler.cc | 121 __ JumpTo(Arm64ManagedRegister::FromXRegister(TR), Offset(offset.Int32Value()), in CreateTrampoline()
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| /art/compiler/utils/arm/ |
| D | assembler_arm_vixl.cc | 39 extern const vixl32::Register tr(TR);
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| /art/compiler/optimizing/ |
| D | code_generator_mips64.cc | 1496 TR, in MarkGCCard()
1787 blocked_core_registers_[TR] = true; in SetupBlockedRegisters()
1859 __ LoadFromOffset(kLoadDoubleword, T9, TR, entry_point_offset); in GenerateInvokeRuntime()
1931 TR, in GenerateSuspendCheck()
5227 __ LoadFromOffset(kLoadDoubleword, T9, TR, entry_point_offset); in GenerateGcRootFieldLoad()
5282 __ LoadFromOffset(kLoadDoubleword, temp.AsRegister<GpuRegister>(), TR, entry_point_offset); in GenerateGcRootFieldLoad()
5359 __ LoadFromOffset(kLoadDoubleword, T9, TR, entry_point_offset); in GenerateFieldLoadWithBakerReadBarrier()
5448 __ LoadFromOffset(kLoadDoubleword, T9, TR, entry_point_offset); in GenerateArrayLoadWithBakerReadBarrier()
6081 TR, in GenerateStaticOrDirectCall()
6383 __ LoadFromOffset(kLoadUnsignedWord, out, TR, GetExceptionTlsOffset()); in VisitLoadException()
[all …]
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| D | intrinsics_mips64.cc | 836 TR, in VisitThreadCurrentThread()
2338 __ LoadFromOffset(kLoadWord, out, TR, offset); in VisitThreadInterrupted()
2342 __ StoreToOffset(kStoreWord, ZERO, TR, offset); in VisitThreadInterrupted()
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| D | intrinsics_mips.cc | 961 TR, in VisitThreadCurrentThread()
2677 __ LoadFromOffset(kLoadWord, out, TR, offset); in VisitThreadInterrupted()
2681 __ StoreToOffset(kStoreWord, ZERO, TR, offset); in VisitThreadInterrupted()
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| D | code_generator_mips.cc | 1874 TR, in MarkGCCard()
1920 blocked_core_registers_[TR] = true; in SetupBlockedRegisters()
2004 __ LoadFromOffset(kLoadWord, T9, TR, entry_point_offset); in GenerateInvokeRuntime()
2085 TR, in GenerateSuspendCheck()
7057 __ LoadFromOffset(kLoadWord, T9, TR, entry_point_offset); in GenerateGcRootFieldLoad()
7124 __ LoadFromOffset(kLoadWord, temp.AsRegister<Register>(), TR, entry_point_offset); in GenerateGcRootFieldLoad()
7213 __ LoadFromOffset(kLoadWord, T9, TR, entry_point_offset); in GenerateFieldLoadWithBakerReadBarrier()
7317 __ LoadFromOffset(kLoadWord, T9, TR, entry_point_offset); in GenerateArrayLoadWithBakerReadBarrier()
7990 TR, in GenerateStaticOrDirectCall()
8345 __ LoadFromOffset(kLoadWord, out, TR, GetExceptionTlsOffset()); in VisitLoadException()
[all …]
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| D | code_generator_arm_vixl.cc | 2038 blocked_core_registers_[TR] = true; in SetupBlockedRegisters()
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