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Searched refs:core_spill_mask_ (Results 1 – 11 of 11) sorted by relevance

/art/runtime/quick/
Dquick_method_frame_info.h30 core_spill_mask_(0u), in QuickMethodFrameInfo()
37 core_spill_mask_(core_spill_mask), in QuickMethodFrameInfo()
46 return core_spill_mask_; in CoreSpillMask()
59 uint32_t core_spill_mask_; variable
/art/compiler/jni/quick/
Djni_compiler.h42 core_spill_mask_(core_spill_mask), in JniCompiledMethod()
52 uint32_t GetCoreSpillMask() const { return core_spill_mask_; } in GetCoreSpillMask()
60 uint32_t core_spill_mask_; variable
/art/compiler/optimizing/
Dstack_map_stream.h103 uint32_t core_spill_mask_ = 0; variable
Dcode_generator.h236 uint32_t GetCoreSpillMask() const { return core_spill_mask_; } in GetCoreSpillMask()
244 core_spill_mask_ = allocated_registers_.GetCoreRegisters() & core_callee_save_mask_; in ComputeSpillMask()
245 DCHECK_NE(core_spill_mask_, 0u) << "At least the return address register must be saved"; in ComputeSpillMask()
680 return POPCOUNT(core_spill_mask_) * GetWordSize(); in GetCoreSpillSize()
732 uint32_t core_spill_mask_; variable
Dstack_map_stream.cc52 core_spill_mask_ = core_spill_mask; in BeginMethod()
300 out.WriteVarint(core_spill_mask_); in Encode()
Dcode_generator.cc395 core_spill_mask_, in Compile()
938 core_spill_mask_(0), in CodeGenerator()
Dcode_generator_arm_vixl.cc2062 core_spill_mask_ = allocated_registers_.GetCoreRegisters() & core_callee_save_mask_; in ComputeSpillMask()
2063 DCHECK_NE(core_spill_mask_, 0u) << "At least the return address register must be saved"; in ComputeSpillMask()
2066 core_spill_mask_ |= (1 << kCoreAlwaysSpillRegister.GetCode()); in ComputeSpillMask()
2128 __ Push(RegisterList(core_spill_mask_)); in GenerateFrameEntry()
2129 GetAssembler()->cfi().AdjustCFAOffset(kArmWordSize * POPCOUNT(core_spill_mask_)); in GenerateFrameEntry()
2132 core_spill_mask_, in GenerateFrameEntry()
2188 DCHECK_NE(core_spill_mask_ & (1 << kLrCode), 0U); in GenerateFrameExit()
2189 uint32_t pop_mask = (core_spill_mask_ & (~(1 << kLrCode))) | 1 << kPcCode; in GenerateFrameExit()
Dcode_generator_mips.cc1263 core_spill_mask_ = allocated_registers_.GetCoreRegisters() & core_callee_save_mask_; in ComputeSpillMask()
1265 DCHECK_NE(core_spill_mask_, 0u) << "At least the return address register must be saved"; in ComputeSpillMask()
1269 if ((fpu_spill_mask_ != 0) && (POPCOUNT(core_spill_mask_) % 2 != 0)) { in ComputeSpillMask()
1270 core_spill_mask_ |= (1 << ZERO); in ComputeSpillMask()
1310 CHECK_EQ(core_spill_mask_, 1u << RA); in GenerateFrameEntry()
1326 for (uint32_t mask = core_spill_mask_; mask != 0; ) { in GenerateFrameEntry()
1366 for (uint32_t mask = core_spill_mask_; mask != 0; ) { in GenerateFrameExit()
Dcode_generator_arm64.cc1141 DCHECK(ArtVixlRegCodeCoherentForRegSet(core_spill_mask_, GetNumberOfCoreRegisters(), 0, 0)); in GetFramePreservedCoreRegisters()
1143 core_spill_mask_); in GetFramePreservedCoreRegisters()
/art/runtime/
Dstack_map.h465 callback(&CodeInfo::core_spill_mask_); in ForEachHeaderField()
490 uint32_t core_spill_mask_ = 0; variable
Dstack_map.cc231 << " CoreSpillMask:" << std::hex << core_spill_mask_ in Dump()