| /art/runtime/interpreter/ |
| D | interpreter_common.h | 423 int32_t dividend, int32_t divisor) in DoIntDivide() argument
430 if (UNLIKELY(dividend == kMinInt && divisor == -1)) { in DoIntDivide()
433 shadow_frame.SetVReg(result_reg, dividend / divisor); in DoIntDivide()
441 int32_t dividend, int32_t divisor) in DoIntRemainder() argument
448 if (UNLIKELY(dividend == kMinInt && divisor == -1)) { in DoIntRemainder()
451 shadow_frame.SetVReg(result_reg, dividend % divisor); in DoIntRemainder()
460 int64_t dividend, in DoLongDivide() argument
468 if (UNLIKELY(dividend == kMinLong && divisor == -1)) { in DoLongDivide()
471 shadow_frame.SetVRegLong(result_reg, dividend / divisor); in DoLongDivide()
480 int64_t dividend, in DoLongRemainder() argument
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| /art/compiler/optimizing/ |
| D | code_generator_mips64.cc | 3361 GpuRegister dividend = locations->InAt(0).AsRegister<GpuRegister>(); in DivRemOneOrMinusOne() local
3370 __ Subu(out, ZERO, dividend); in DivRemOneOrMinusOne()
3373 __ Dsubu(out, ZERO, dividend); in DivRemOneOrMinusOne()
3375 } else if (out != dividend) { in DivRemOneOrMinusOne()
3376 __ Move(out, dividend); in DivRemOneOrMinusOne()
3390 GpuRegister dividend = locations->InAt(0).AsRegister<GpuRegister>(); in DivRemByPowerOfTwo() local
3399 __ Srl(TMP, dividend, 31); in DivRemByPowerOfTwo()
3401 __ Sra(TMP, dividend, 31); in DivRemByPowerOfTwo()
3404 __ Addu(out, dividend, TMP); in DivRemByPowerOfTwo()
3413 __ Dsrl32(TMP, dividend, 31); in DivRemByPowerOfTwo()
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| D | code_generator_arm64.cc | 2890 Register dividend = InputRegisterAt(instruction, 0); in FOR_EACH_CONDITION_INSTRUCTION() local
2894 __ Add(out, dividend, Operand(dividend, LSR, bits - 1)); in FOR_EACH_CONDITION_INSTRUCTION()
2898 __ Add(temp, dividend, abs_imm - 1); in FOR_EACH_CONDITION_INSTRUCTION()
2899 __ Cmp(dividend, 0); in FOR_EACH_CONDITION_INSTRUCTION()
2900 __ Csel(out, temp, dividend, lt); in FOR_EACH_CONDITION_INSTRUCTION()
2919 Register dividend = InputRegisterAt(instruction, 0); in GenerateDivRemWithAnyConstant() local
2936 __ Smulh(temp, dividend, temp); in GenerateDivRemWithAnyConstant()
2938 __ Smull(temp.X(), dividend, temp); in GenerateDivRemWithAnyConstant()
2943 __ Add(temp, temp, dividend); in GenerateDivRemWithAnyConstant()
2945 __ Sub(temp, temp, dividend); in GenerateDivRemWithAnyConstant()
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| D | code_generator_mips.cc | 3853 Register dividend = locations->InAt(0).AsRegister<Register>(); in DivRemOneOrMinusOne() local
3859 __ Subu(out, ZERO, dividend); in DivRemOneOrMinusOne()
3860 } else if (out != dividend) { in DivRemOneOrMinusOne()
3861 __ Move(out, dividend); in DivRemOneOrMinusOne()
3899 Register dividend = locations->InAt(0).AsRegister<Register>(); in DivRemByPowerOfTwo() local
3907 __ Srl(TMP, dividend, 31); in DivRemByPowerOfTwo()
3909 __ Sra(TMP, dividend, 31); in DivRemByPowerOfTwo()
3912 __ Addu(out, dividend, TMP); in DivRemByPowerOfTwo()
3920 __ Sra(TMP, dividend, 31); in DivRemByPowerOfTwo()
3921 __ Subu(out, dividend, TMP); in DivRemByPowerOfTwo()
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| D | code_generator_arm_vixl.cc | 3953 vixl32::Register dividend = InputRegisterAt(instruction, 0); in DivRemOneOrMinusOne() local
3961 __ Mov(out, dividend); in DivRemOneOrMinusOne()
3963 __ Rsb(out, dividend, 0); in DivRemOneOrMinusOne()
3977 vixl32::Register dividend = InputRegisterAt(instruction, 0); in DivRemByPowerOfTwo() local
3984 __ Lsr(temp, dividend, 32 - ctz_imm); in DivRemByPowerOfTwo()
3986 __ Asr(temp, dividend, 31); in DivRemByPowerOfTwo()
3989 __ Add(out, temp, dividend); in DivRemByPowerOfTwo()
4011 vixl32::Register dividend = InputRegisterAt(instruction, 0); in GenerateDivRemWithAnyConstant() local
4022 __ Smull(temp2, temp1, dividend, temp1); in GenerateDivRemWithAnyConstant()
4025 __ Add(temp1, temp1, dividend); in GenerateDivRemWithAnyConstant()
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