Searched refs:fpu_spill_mask_ (Results 1 – 5 of 5) sorted by relevance
237 uint32_t GetFpuSpillMask() const { return fpu_spill_mask_; } in GetFpuSpillMask()246 fpu_spill_mask_ = allocated_registers_.GetFloatingPointRegisters() & fpu_callee_save_mask_; in ComputeSpillMask()676 return POPCOUNT(fpu_spill_mask_) * GetFloatingPointSpillSlotSize(); in GetFpuSpillSize()733 uint32_t fpu_spill_mask_; variable
2067 fpu_spill_mask_ = allocated_registers_.GetFloatingPointRegisters() & fpu_callee_save_mask_; in ComputeSpillMask()2072 if (fpu_spill_mask_ != 0) { in ComputeSpillMask()2073 uint32_t least_significant_bit = LeastSignificantBit(fpu_spill_mask_); in ComputeSpillMask()2074 uint32_t most_significant_bit = MostSignificantBit(fpu_spill_mask_); in ComputeSpillMask()2076 fpu_spill_mask_ |= (1 << i); in ComputeSpillMask()2134 if (fpu_spill_mask_ != 0) { in GenerateFrameEntry()2135 uint32_t first = LeastSignificantBit(fpu_spill_mask_); in GenerateFrameEntry()2138 DCHECK_EQ(fpu_spill_mask_ >> CTZ(fpu_spill_mask_), ~0u >> (32 - POPCOUNT(fpu_spill_mask_))); in GenerateFrameEntry()2140 __ Vpush(SRegisterList(vixl32::SRegister(first), POPCOUNT(fpu_spill_mask_))); in GenerateFrameEntry()2141 GetAssembler()->cfi().AdjustCFAOffset(kArmWordSize * POPCOUNT(fpu_spill_mask_)); in GenerateFrameEntry()[all …]
396 fpu_spill_mask_, in Compile()939 fpu_spill_mask_(0), in CodeGenerator()
1264 fpu_spill_mask_ = allocated_registers_.GetFloatingPointRegisters() & fpu_callee_save_mask_; in ComputeSpillMask()1269 if ((fpu_spill_mask_ != 0) && (POPCOUNT(core_spill_mask_) % 2 != 0)) { in ComputeSpillMask()1309 CHECK_EQ(fpu_spill_mask_, 0u); in GenerateFrameEntry()1337 for (uint32_t mask = fpu_spill_mask_; mask != 0; ) { in GenerateFrameEntry()1377 for (uint32_t mask = fpu_spill_mask_; mask != 0; ) { in GenerateFrameExit()
1147 DCHECK(ArtVixlRegCodeCoherentForRegSet(0, 0, fpu_spill_mask_, in GetFramePreservedFPRegisters()1150 fpu_spill_mask_); in GetFramePreservedFPRegisters()