1 /*******************************************************************************
2 * Copyright (C) 2018 Cadence Design Systems, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining
5 * a copy of this software and associated documentation files (the
6 * "Software"), to use this Software with Cadence processor cores only and
7 * not with any other processors and platforms, subject to
8 * the following conditions:
9 *
10 * The above copyright notice and this permission notice shall be included
11 * in all copies or substantial portions of the Software.
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
14 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
15 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
16 * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
17 * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
18 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
19 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20
21 ******************************************************************************/
22
23 /*******************************************************************************
24 * board-hikey/xf-board.h
25 *
26 * HiKey960-specific definitions
27 *
28 *******************************************************************************/
29
30 #ifndef __XF_H
31 #error "xf-board.h mustn't be included directly"
32 #endif
33
34 /*******************************************************************************
35 * Global constants definitions
36 ******************************************************************************/
37
38 /* ...shared memory interface address */
39 #define XF_CFG_SHMEM_ADDRESS(core) HIFI_HIKEY_SHARE_MEM_ADDR
40
41 /* ...tracing buffer configuration (place at the end of memory) */
42 #define XF_CFG_TRACE_START(core) 0x78000000
43 #define XF_CFG_TRACE_END(core) 0x7FFFFFFF
44 #if 1
45 #define DSP_IPC_FROM_AP_INT_NO (3)
46 #define DSP_SYS_IPC_BASE_ADDR_NS (0xe896b000)
47 #define DSP_AP_TO_DSP_MAILBOX_NO (18)
48 #define DSP_DSP_TO_AP_MAILBOX_NO (2)
49 #define IPC_BUSY_RETRY_COUNT (1000)
50 #define IPC_ACPU_INT_SRC_HIFI_MSG (1)
51 #define BIT_MASK(n) (1 << (n))
52
53 #define WORD_REF(address) (* ((unsigned int volatile *) (address)))
54
55 #define SYS_IPC_LOCK(base) WORD_REF(base + 0xA00)
56 #define SYS_IPC_ICLR(base, box) WORD_REF(base + ((box) << 6) + 0x18)
57 #define SYS_IPC_DATA(base, box, num) WORD_REF(base + ((box) << 6) + 0x20 + ((num) << 2))
58 #define SYS_IPC_CPUIRST(base, core) WORD_REF(base + 0x804 + ((core) << 3))
59 #define SYS_IPC_MODE(base, box) WORD_REF(base + ((box) << 6) + 0x10)
60 #define SYS_IPC_SOURCE(base, box) WORD_REF(base + ((box) << 6))
61 #define SYS_IPC_DEST(base, box) WORD_REF(base + ((box) * 64) + 0x04)
62 #define SYS_IPC_SEND(base, box) WORD_REF(base + ((box) << 6) + 0x1c)
63 #define SYS_IPC_IMASK(base, box) WORD_REF(base + ((box) << 6) + 0x14)
64 #define SYS_IPC_DCLR(base, box) WORD_REF(base + ((box) * 64) + 0x08)
65 #define SYS_IPC_CPUIMST(base, core) WORD_REF(base + 0x800 + ((core) * 8))
66 #define SYS_IPC_MODE_ACK (7)
67 #define SYS_IPC_MODE_IDLE (4)
68 #define SYS_IPC_MODE_AUTOACK (0)
69
70 #define SYS_IPC_CORE_HIFI (4)
71 #define SYS_IPC_CORE_A15 (0)
72 #define SYS_IPC_CORE_LPM3 (3)
73 #endif
74 /* ...inter-processor interrupt number (SEL:10 - LEVEL:15) */
75 #define XF_PROXY_IPI_NUM(core) 15
76
77 /*******************************************************************************
78 * External functions
79 ******************************************************************************/
80
81 /* ...gdb stub initialization */
82 extern void init_gdbstub(void);
83
84 /* ...emit breakpoint */
85 extern void breakpoint(void);
86 #if 0// def HIKEY_XAF_IPC_COMMENT_OUT
87 /*******************************************************************************
88 * Public proxy API
89 ******************************************************************************/
90
91 /* ...notify remote side about status change */
92 #define XF_PROXY_NOTIFY_PEER(core) h2_wake_core()
93
94 /* ...clear pending interrupt mask */
95 #define XF_PROXY_SYNC_PEER(core) h2_local_ack()
96
97 /*******************************************************************************
98 * Auxiliary helper functions
99 ******************************************************************************/
100
101 /* ...generate inter-processor interrupt for remote core */
102 static inline void h2_wake_core(void)
103 {
104 /* ...we have single INPUT-interrupt pin */
105 *(volatile unsigned int *)0xec800044 = 1;
106 }
107
108 /* ...acknowledge pending IPI interrupt */
109 static inline void h2_local_ack(void)
110 {
111 /* ...asserted interrupt cannot be cleared */
112 }
113
114 /*******************************************************************************
115 * Board specific init
116 ******************************************************************************/
117
118 static inline void xf_board_init(void)
119 {
120 /* ...initialize GDB debugging interface */
121 init_gdbstub();
122
123 /* ...indicate the board has started */
124 *(volatile unsigned int *)0xec800100 = 1;
125 }
126 #else
127 //#define XF_PROXY_NOTIFY_PEER(core) dsp_ipc_send_irq_to_ap()
128 #define XF_PROXY_NOTIFY_PEER(core) h2_wake_core()
129 /* ...clear pending interrupt mask */
130 #define XF_PROXY_SYNC_PEER(core) h2_local_ack()
131
132 /* ...generate inter-processor interrupt for remote core */
h2_wake_core(void)133 static inline void h2_wake_core(void)
134 {
135 unsigned int mode = 0;
136 unsigned int mode_1 = 0;
137
138 // mode = SYS_IPC_MODE(DSP_SYS_IPC_BASE_ADDR_NS, DSP_DSP_TO_AP_MAILBOX_NO);
139 //mode = (* ((unsigned int volatile *) (0xe896b000 + ((2) << 6) + 0x10)));
140 mode = * (volatile unsigned int*) 0xe896b090;
141
142 //if (mode & BIT_MASK(SYS_IPC_MODE_IDLE)) {
143 //if (mode & (1 << (4))) {
144 if (mode & 0x10) {
145 mode_1=0;
146 } else {
147 return;
148 }
149
150 //SYS_IPC_SOURCE(DSP_SYS_IPC_BASE_ADDR_NS, DSP_DSP_TO_AP_MAILBOX_NO) = BIT_MASK(SYS_IPC_CORE_HIFI);
151 //(* ((unsigned int volatile *) (0xe896b000 + ((2) << 6))))= (1 << (4));
152 * (volatile unsigned int *) 0xe896b080 = (0x10);
153
154 //SYS_IPC_IMASK(DSP_SYS_IPC_BASE_ADDR_NS, DSP_DSP_TO_AP_MAILBOX_NO) = ~((unsigned int)(BIT_MASK(SYS_IPC_CORE_HIFI)|BIT_MASK(SYS_IPC_CORE_A15)));
155 //(* ((unsigned int volatile *) (0xe896b000 + ((2) << 6) + 0x14))) = ~ ((unsigned int)((1 << (4))|(1 << (0))));
156 * (volatile unsigned int *)0xe896b094 = ~ ((unsigned int)(0x11));
157
158 //SYS_IPC_DATA(DSP_SYS_IPC_BASE_ADDR_NS, DSP_DSP_TO_AP_MAILBOX_NO, 0) = IPC_ACPU_INT_SRC_HIFI_MSG;
159 //(* ((unsigned int volatile *) (0xe896b000 + ((2) << 6) + 0x20 + ((0) << 2)))) = 1;
160 * (volatile unsigned int *) 0xe896b0A0 = 1;
161
162 //SYS_IPC_MODE(DSP_SYS_IPC_BASE_ADDR_NS, DSP_DSP_TO_AP_MAILBOX_NO) = BIT_MASK(SYS_IPC_MODE_AUTOACK);
163 //(* ((unsigned int volatile *) (0xe896b000 + ((2) << 6) + 0x10))) = (1 << (0));
164 * (volatile unsigned int *) 0xe896b090 = 1;
165
166 //SYS_IPC_SEND(DSP_SYS_IPC_BASE_ADDR_NS, DSP_DSP_TO_AP_MAILBOX_NO) = BIT_MASK(SYS_IPC_CORE_HIFI);
167 //(* ((unsigned int volatile *) (0xe896b000 + ((2) << 6) + 0x1c))) = (1 << (4));
168 * (volatile unsigned int *) 0xe896b09C = 0x10;
169
170 return;
171 }
172
173 /* ...acknowledge pending IPI interrupt */
h2_local_ack(void)174 static inline void h2_local_ack(void)
175 {
176 /* ...asserted interrupt cannot be cleared */
177 }
178
179 #endif
180
181