/device/linaro/bootloader/arm-trusted-firmware/bl1/aarch32/ |
D | bl1_context_mgmt.c | 72 next_smc_ctx->r0 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R0); in copy_cpu_ctx_to_smc_ctx() 73 next_smc_ctx->r1 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R1); in copy_cpu_ctx_to_smc_ctx() 74 next_smc_ctx->r2 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R2); in copy_cpu_ctx_to_smc_ctx() 75 next_smc_ctx->r3 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R3); in copy_cpu_ctx_to_smc_ctx() 76 next_smc_ctx->lr_mon = read_ctx_reg(cpu_reg_ctx, CTX_LR); in copy_cpu_ctx_to_smc_ctx() 77 next_smc_ctx->spsr_mon = read_ctx_reg(cpu_reg_ctx, CTX_SPSR); in copy_cpu_ctx_to_smc_ctx() 78 next_smc_ctx->scr = read_ctx_reg(cpu_reg_ctx, CTX_SCR); in copy_cpu_ctx_to_smc_ctx() 159 ns_sctlr = read_ctx_reg(get_regs_ctx(ctx), CTX_NS_SCTLR); in bl1_prepare_next_image()
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/device/linaro/bootloader/arm-trusted-firmware/bl32/sp_min/ |
D | sp_min_main.c | 102 next_smc_ctx->r0 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R0); in copy_cpu_ctx_to_smc_stx() 103 next_smc_ctx->lr_mon = read_ctx_reg(cpu_reg_ctx, CTX_LR); in copy_cpu_ctx_to_smc_stx() 104 next_smc_ctx->spsr_mon = read_ctx_reg(cpu_reg_ctx, CTX_SPSR); in copy_cpu_ctx_to_smc_stx() 105 next_smc_ctx->scr = read_ctx_reg(cpu_reg_ctx, CTX_SCR); in copy_cpu_ctx_to_smc_stx() 136 ns_sctlr = read_ctx_reg(get_regs_ctx(ctx), CTX_NS_SCTLR); in sp_min_prepare_next_image_entry() 215 ns_sctlr = read_ctx_reg(get_regs_ctx(ctx), CTX_NS_SCTLR); in sp_min_warm_boot()
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/device/linaro/bootloader/arm-trusted-firmware/include/lib/aarch64/ |
D | smcc_helpers.h | 57 read_ctx_reg((get_gpregs_ctx(_h)), (_g)) 66 read_ctx_reg((get_el3state_ctx(_h)), (_e)) 83 _x1 = read_ctx_reg(regs, CTX_GPREG_X1); \ 84 _x2 = read_ctx_reg(regs, CTX_GPREG_X2); \ 85 _x3 = read_ctx_reg(regs, CTX_GPREG_X3); \ 86 _x4 = read_ctx_reg(regs, CTX_GPREG_X4); \
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/device/linaro/bootloader/arm-trusted-firmware/plat/nvidia/tegra/common/ |
D | tegra_fiq_glue.c | 55 fiq_state[cpu].elr_el3 = read_ctx_reg((el3state_ctx), (uint32_t)(CTX_ELR_EL3)); in tegra_fiq_interrupt_handler() 56 fiq_state[cpu].spsr_el3 = read_ctx_reg((el3state_ctx), (uint32_t)(CTX_SPSR_EL3)); in tegra_fiq_interrupt_handler() 132 val = read_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_SP_EL0)); in tegra_fiq_get_intr_context() 135 val = read_ctx_reg((el1state_ctx), (uint32_t)(CTX_SP_EL1)); in tegra_fiq_get_intr_context()
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/device/linaro/bootloader/arm-trusted-firmware/services/spd/opteed/ |
D | opteed_main.c | 250 read_ctx_reg(get_gpregs_ctx(handle), in opteed_smc_handler() 254 read_ctx_reg(get_gpregs_ctx(handle), in opteed_smc_handler() 258 read_ctx_reg(get_gpregs_ctx(handle), in opteed_smc_handler() 263 read_ctx_reg(get_gpregs_ctx(handle), in opteed_smc_handler()
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/device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/rk3399/ |
D | plat_sip_calls.c | 66 x5 = read_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X5); in rockchip_plat_sip_handler() 67 x6 = read_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X6); in rockchip_plat_sip_handler()
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/device/linaro/bootloader/arm-trusted-firmware/lib/el3_runtime/aarch64/ |
D | context_mgmt.c | 252 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); in cm_prepare_el3_exit() 255 sctlr_elx = read_ctx_reg(get_sysregs_ctx(ctx), in cm_prepare_el3_exit() 532 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); in cm_write_scr_el3_bit() 552 return read_ctx_reg(state, CTX_SCR_EL3); in cm_get_scr_el3()
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/device/linaro/bootloader/arm-trusted-firmware/plat/arm/common/ |
D | execution_state_switch.c | 56 spsr = read_ctx_reg(el3_ctx, CTX_SPSR_EL3); in arm_execution_state_switch() 90 scr = read_ctx_reg(el3_ctx, CTX_SCR_EL3); in arm_execution_state_switch()
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/device/linaro/bootloader/arm-trusted-firmware/lib/el3_runtime/aarch32/ |
D | context_mgmt.c | 168 scr = read_ctx_reg(get_regs_ctx(ctx), CTX_SCR); in cm_prepare_el3_exit() 171 hsctlr = read_ctx_reg(get_regs_ctx(ctx), in cm_prepare_el3_exit()
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/device/linaro/bootloader/arm-trusted-firmware/include/lib/el3_runtime/aarch32/ |
D | context.h | 47 #define read_ctx_reg(ctx, offset) ((ctx)->_regs[offset >> WORD_SHIFT]) macro
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/device/linaro/bootloader/arm-trusted-firmware/services/spd/trusty/ |
D | trusty.c | 154 ctx->fiq_sp_el1 = read_ctx_reg(get_sysregs_ctx(handle), CTX_SP_EL1); in trusty_fiq_handler() 183 uint64_t sp_el0 = read_ctx_reg(&ctx->fiq_gpregs, CTX_GPREG_SP_EL0); in trusty_get_fiq_regs() 292 int reg_width = GET_RW(read_ctx_reg(get_el3state_ctx(&ctx->cpu_ctx), in trusty_init()
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/device/linaro/bootloader/arm-trusted-firmware/plat/nvidia/tegra/soc/t186/drivers/mce/ |
D | mce.c | 184 arg3 = read_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X4)); in mce_command_handler() 185 arg4 = read_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X5)); in mce_command_handler() 186 arg5 = read_ctx_reg((gp_regs), (uint32_t)(CTX_GPREG_X6)); in mce_command_handler()
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/device/linaro/bootloader/arm-trusted-firmware/include/lib/el3_runtime/aarch64/ |
D | context.h | 226 #define read_ctx_reg(ctx, offset) ((ctx)->_regs[offset >> DWORD_SHIFT]) macro
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