1 /*
2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <arch_helpers.h>
8 #include <assert.h>
9 #include <context.h>
10 #include <context_mgmt.h>
11 #include <debug.h>
12 #include <platform.h>
13 #include <smcc_helpers.h>
14 #include "../bl1_private.h"
15
16 /*
17 * Following arrays will be used for context management.
18 * There are 2 instances, for the Secure and Non-Secure contexts.
19 */
20 static cpu_context_t bl1_cpu_context[2];
21 static smc_ctx_t bl1_smc_context[2];
22
23 /* Following contains the next cpu context pointer. */
24 static void *bl1_next_cpu_context_ptr;
25
26 /* Following contains the next smc context pointer. */
27 static void *bl1_next_smc_context_ptr;
28
29 /* Following functions are used for SMC context handling */
smc_get_ctx(unsigned int security_state)30 void *smc_get_ctx(unsigned int security_state)
31 {
32 assert(sec_state_is_valid(security_state));
33 return &bl1_smc_context[security_state];
34 }
35
smc_set_next_ctx(unsigned int security_state)36 void smc_set_next_ctx(unsigned int security_state)
37 {
38 assert(sec_state_is_valid(security_state));
39 bl1_next_smc_context_ptr = &bl1_smc_context[security_state];
40 }
41
smc_get_next_ctx(void)42 void *smc_get_next_ctx(void)
43 {
44 return bl1_next_smc_context_ptr;
45 }
46
47 /* Following functions are used for CPU context handling */
cm_get_context(uint32_t security_state)48 void *cm_get_context(uint32_t security_state)
49 {
50 assert(sec_state_is_valid(security_state));
51 return &bl1_cpu_context[security_state];
52 }
53
cm_set_next_context(void * cpu_context)54 void cm_set_next_context(void *cpu_context)
55 {
56 assert(cpu_context);
57 bl1_next_cpu_context_ptr = cpu_context;
58 }
59
cm_get_next_context(void)60 void *cm_get_next_context(void)
61 {
62 return bl1_next_cpu_context_ptr;
63 }
64
65 /*******************************************************************************
66 * Following function copies GP regs r0-r4, lr and spsr,
67 * from the CPU context to the SMC context structures.
68 ******************************************************************************/
copy_cpu_ctx_to_smc_ctx(const regs_t * cpu_reg_ctx,smc_ctx_t * next_smc_ctx)69 static void copy_cpu_ctx_to_smc_ctx(const regs_t *cpu_reg_ctx,
70 smc_ctx_t *next_smc_ctx)
71 {
72 next_smc_ctx->r0 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R0);
73 next_smc_ctx->r1 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R1);
74 next_smc_ctx->r2 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R2);
75 next_smc_ctx->r3 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R3);
76 next_smc_ctx->lr_mon = read_ctx_reg(cpu_reg_ctx, CTX_LR);
77 next_smc_ctx->spsr_mon = read_ctx_reg(cpu_reg_ctx, CTX_SPSR);
78 next_smc_ctx->scr = read_ctx_reg(cpu_reg_ctx, CTX_SCR);
79 }
80
81 /*******************************************************************************
82 * Following function flushes the SMC & CPU context pointer and its data.
83 ******************************************************************************/
flush_smc_and_cpu_ctx(void)84 static void flush_smc_and_cpu_ctx(void)
85 {
86 flush_dcache_range((uintptr_t)&bl1_next_smc_context_ptr,
87 sizeof(bl1_next_smc_context_ptr));
88 flush_dcache_range((uintptr_t)bl1_next_smc_context_ptr,
89 sizeof(smc_ctx_t));
90
91 flush_dcache_range((uintptr_t)&bl1_next_cpu_context_ptr,
92 sizeof(bl1_next_cpu_context_ptr));
93 flush_dcache_range((uintptr_t)bl1_next_cpu_context_ptr,
94 sizeof(cpu_context_t));
95 }
96
97 /*******************************************************************************
98 * This function prepares the context for Secure/Normal world images.
99 * Normal world images are transitioned to HYP(if supported) else SVC.
100 ******************************************************************************/
bl1_prepare_next_image(unsigned int image_id)101 void bl1_prepare_next_image(unsigned int image_id)
102 {
103 unsigned int security_state;
104 image_desc_t *image_desc;
105 entry_point_info_t *next_bl_ep;
106
107 /* Get the image descriptor. */
108 image_desc = bl1_plat_get_image_desc(image_id);
109 assert(image_desc);
110
111 /* Get the entry point info. */
112 next_bl_ep = &image_desc->ep_info;
113
114 /* Get the image security state. */
115 security_state = GET_SECURITY_STATE(next_bl_ep->h.attr);
116
117 /* Prepare the SPSR for the next BL image. */
118 if (security_state == SECURE) {
119 next_bl_ep->spsr = SPSR_MODE32(MODE32_svc, SPSR_T_ARM,
120 SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
121 } else {
122 /* Use HYP mode if supported else use SVC. */
123 if (GET_VIRT_EXT(read_id_pfr1())) {
124 next_bl_ep->spsr = SPSR_MODE32(MODE32_hyp, SPSR_T_ARM,
125 SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
126 } else {
127 next_bl_ep->spsr = SPSR_MODE32(MODE32_svc, SPSR_T_ARM,
128 SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
129 }
130 }
131
132 /* Allow platform to make change */
133 bl1_plat_set_ep_info(image_id, next_bl_ep);
134
135 /* Prepare the cpu context for the next BL image. */
136 cm_init_my_context(next_bl_ep);
137 cm_prepare_el3_exit(security_state);
138 cm_set_next_context(cm_get_context(security_state));
139
140 /* Prepare the smc context for the next BL image. */
141 smc_set_next_ctx(security_state);
142 copy_cpu_ctx_to_smc_ctx(get_regs_ctx(cm_get_next_context()),
143 smc_get_next_ctx());
144
145 /*
146 * If the next image is non-secure, then we need to program the banked
147 * non secure sctlr. This is not required when the next image is secure
148 * because in AArch32, we expect the secure world to have the same
149 * SCTLR settings.
150 */
151 if (security_state == NON_SECURE) {
152 cpu_context_t *ctx = cm_get_context(security_state);
153 u_register_t ns_sctlr;
154
155 /* Temporarily set the NS bit to access NS SCTLR */
156 write_scr(read_scr() | SCR_NS_BIT);
157 isb();
158
159 ns_sctlr = read_ctx_reg(get_regs_ctx(ctx), CTX_NS_SCTLR);
160 write_sctlr(ns_sctlr);
161 isb();
162
163 write_scr(read_scr() & ~SCR_NS_BIT);
164 isb();
165 }
166
167 /*
168 * Flush the SMC & CPU context and the (next)pointers,
169 * to access them after caches are disabled.
170 */
171 flush_smc_and_cpu_ctx();
172
173 /* Indicate that image is in execution state. */
174 image_desc->state = IMAGE_STATE_EXECUTED;
175
176 print_entry_point_info(next_bl_ep);
177 }
178