| /device/linaro/bootloader/arm-trusted-firmware/plat/nvidia/tegra/common/aarch64/ |
| D | tegra_helpers.S | 60 mrs x0, midr_el1
62 and x0, x0, x1
63 lsr x0, x0, #MIDR_PN_SHIFT
64 cmp x0, #MIDR_PN_CORTEX_A57
71 mrs x0, CORTEX_A57_L2ECTLR_EL1
73 bic x0, x0, #CORTEX_A57_L2ECTLR_RET_CTRL_MASK
74 orr x0, x0, x1
75 msr CORTEX_A57_L2ECTLR_EL1, x0
78 mrs x0, CORTEX_A57_ECTLR_EL1
80 bic x0, x0, #CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK
[all …]
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| /device/linaro/bootloader/edk2/ArmPkg/Library/ArmLib/AArch64/ |
| D | AArch64Support.S | 28 dc ivac, x0 // Invalidate single data cache line
33 dc cvac, x0 // Clean single data cache line
38 dc cvau, x0 // Clean single data cache line to PoU
42 ic ivau, x0 // Invalidate single instruction cache line to PoU
47 dc civac, x0 // Clean and invalidate single data cache line
52 dc isw, x0 // Invalidate this line
57 dc cisw, x0 // Clean and Invalidate this line
62 dc csw, x0 // Clean this line
75 1: mrs x0, sctlr_el1 // Read System control register EL1
77 2: mrs x0, sctlr_el2 // Read System control register EL2
[all …]
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| D | ArmLibSupport.S | 23 mrs x0, midr_el1 // Read from Main ID Register (MIDR)
27 mrs x0, ctr_el0 // Read from Cache Type Regiter (CTR)
31 mrs x0, daif
37 mrs x0, daif
43 msr cpacr_el1, x0 // Coprocessor Access Control Reg (CPACR)
48 1:msr actlr_el1, x0 // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3
50 2:msr actlr_el2, x0 // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3
55 1:mrs x0, actlr_el1 // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3
57 2:mrs x0, actlr_el2 // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3
62 1:msr ttbr0_el1, x0 // Translation Table Base Reg 0 (TTBR0)
[all …]
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| D | AArch64ArchTimerSupport.S | 19 mrs x0, cntfrq_el0 // Read CNTFRQ
25 msr cntfrq_el0, x0 // Write to CNTFRQ
30 mrs x0, cntpct_el0 // Read CNTPCT (Physical counter register)
35 mrs x0, cntkctl_el1 // Read CNTK_CTL (Timer PL1 Control Register)
40 msr cntkctl_el1, x0 // Write to CNTK_CTL (Timer PL1 Control Register)
45 mrs x0, cntp_tval_el0 // Read CNTP_TVAL (PL1 physical timer value register)
50 msr cntp_tval_el0, x0 // Write to CNTP_TVAL (PL1 physical timer value register)
55 mrs x0, cntp_ctl_el0 // Read CNTP_CTL (PL1 Physical Timer Control Register)
60 msr cntp_ctl_el0, x0 // Write to CNTP_CTL (PL1 Physical Timer Control Register)
65 mrs x0, cntv_tval_el0 // Read CNTV_TVAL (Virtual Timer Value register)
[all …]
|
| /device/linaro/bootloader/OpenPlatformPkg/Platforms/AMD/Styx/OverdriveBoard/FdtBlob/ |
| D | styx-overdrive.dts | 32 reg = <0x0 0xe1110000 0x0 0x1000>,
33 <0x0 0xe112f000 0x0 0x2000>,
34 <0x0 0xe1140000 0x0 0x10000>,
35 <0x0 0xe1160000 0x0 0x10000>;
37 ranges = <0x0 0x0 0x0 0xe1100000 0x0 0x100000>;
44 reg = <0x0 0x80000 0x0 0x1000>;
60 interrupts = <0x0 0x7 0x4>,
61 <0x0 0x8 0x4>,
62 <0x0 0x9 0x4>,
63 <0x0 0xa 0x4>,
[all …]
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| /device/linaro/bootloader/OpenPlatformPkg/Platforms/AMD/Styx/Overdrive1000Board/FdtBlob/ |
| D | styx-overdrive1000.dts | 32 reg = <0x0 0xe1110000 0x0 0x1000>,
33 <0x0 0xe112f000 0x0 0x2000>,
34 <0x0 0xe1140000 0x0 0x10000>,
35 <0x0 0xe1160000 0x0 0x10000>;
37 ranges = <0x0 0x0 0x0 0xe1100000 0x0 0x100000>;
44 reg = <0x0 0x80000 0x0 0x1000>;
60 interrupts = <0x0 0x7 0x4>,
61 <0x0 0x8 0x4>,
62 <0x0 0x9 0x4>,
63 <0x0 0xa 0x4>,
[all …]
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| /device/linaro/bootloader/arm-trusted-firmware/lib/el3_runtime/aarch64/ |
| D | context.S | 35 stp x9, x10, [x0, #CTX_SPSR_EL1]
39 stp x15, x16, [x0, #CTX_SCTLR_EL1]
43 stp x17, x9, [x0, #CTX_CPACR_EL1]
47 stp x10, x11, [x0, #CTX_SP_EL1]
51 stp x12, x13, [x0, #CTX_TTBR0_EL1]
55 stp x14, x15, [x0, #CTX_MAIR_EL1]
59 stp x16, x17, [x0, #CTX_TCR_EL1]
63 stp x9, x10, [x0, #CTX_TPIDR_EL0]
67 stp x13, x14, [x0, #CTX_PAR_EL1]
71 stp x15, x16, [x0, #CTX_AFSR0_EL1]
[all …]
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| /device/linaro/bootloader/arm-trusted-firmware/plat/hisilicon/hikey/ |
| D | hisi_pwrc_sram.S | 19 mov x0, 0
20 msr oslar_el1, x0
22 mrs x0, CORTEX_A53_CPUACTLR_EL1
23 bic x0, x0, #(CORTEX_A53_CPUACTLR_EL1_RADIS | \
25 orr x0, x0, #0x180000
26 orr x0, x0, #0xe000
27 msr CORTEX_A53_CPUACTLR_EL1, x0
38 mrs x0, mpidr_el1
39 and x1, x0, #MPIDR_CPU_MASK
40 and x0, x0, #MPIDR_CLUSTER_MASK
[all …]
|
| /device/linaro/bootloader/arm-trusted-firmware/include/common/aarch64/ |
| D | el3_common_macros.S | 35 mrs x0, sctlr_el3
36 orr x0, x0, x1
37 msr sctlr_el3, x0
56 adr x0, \_exception_vectors
57 msr vbar_el3, x0
83 mov x0, #((SCR_RESET_VAL | SCR_EA_BIT | SCR_SIF_BIT) \
85 msr scr_el3, x0
113 mov_imm x0, ((MDCR_EL3_RESET_VAL | MDCR_SDD_BIT | MDCR_SPD32(MDCR_SPD32_DISABLE)) \
124 orr x0, x0, #MDCR_NSPB(MDCR_NSPB_EL1)
128 msr mdcr_el3, x0
[all …]
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| /device/linaro/bootloader/arm-trusted-firmware/lib/cpus/aarch64/ |
| D | cortex_a72.S | 30 mrs x0, CORTEX_A72_ECTLR_EL1
31 orr x0, x0, #CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT
34 bic x0, x0, x1
35 msr CORTEX_A72_ECTLR_EL1, x0
45 mrs x0, CORTEX_A72_CPUACTLR_EL1
46 orr x0, x0, #CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH
47 msr CORTEX_A72_CPUACTLR_EL1, x0
58 mrs x0, CORTEX_A72_ECTLR_EL1
59 bic x0, x0, #CORTEX_A72_ECTLR_SMP_BIT
60 msr CORTEX_A72_ECTLR_EL1, x0
[all …]
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| D | cpu_helpers.S | 35 cmp x0, #0
40 ldr x2, [x0, #CPU_RESET_FUNC]
68 cmp x0, x2
69 csel x2, x2, x0, hi
72 ldr x0, [x1, #CPU_DATA_CPU_OPS_PTR]
74 cmp x0, #0
81 ldr x1, [x0, x1]
95 ldr x0, [x6, #CPU_DATA_CPU_OPS_PTR]
96 cbnz x0, 1f
100 cmp x0, #0
[all …]
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| D | cortex_a57.S | 32 mrs x0, CORTEX_A57_ECTLR_EL1
33 orr x0, x0, #CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT
36 bic x0, x0, x1
37 msr CORTEX_A57_ECTLR_EL1, x0
48 mrs x0, CORTEX_A57_ECTLR_EL1
49 bic x0, x0, #CORTEX_A57_ECTLR_SMP_BIT
50 msr CORTEX_A57_ECTLR_EL1, x0
59 mov x0, #1
60 msr osdlr_el1, x0
80 cbz x0, 1f
[all …]
|
| /device/linaro/bootloader/arm-trusted-firmware/plat/arm/board/fvp/aarch64/ |
| D | fvp_helpers.S | 50 mrs x0, mpidr_el1
59 mrs x0, id_aa64pfr0_el1
60 ubfx x0, x0, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_WIDTH
61 cmp x0, #1
75 ldr x0, =VE_GICC_BASE
77 fvp_choose_gicmmap x0, x1, x2, w2, x1
93 mov_imm x0, PLAT_ARM_TRUSTED_MAILBOX_BASE
97 ldr x1, [x0]
141 mov x0, #0
151 mov_imm x0, PLAT_ARM_TRUSTED_MAILBOX_BASE
[all …]
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| /device/linaro/bootloader/arm-trusted-firmware/plat/arm/board/juno/aarch64/ |
| D | juno_helpers.S | 38 cmp x0, #\_revision
50 mrs x0, midr_el1
51 ubfx x0, x0, MIDR_PN_SHIFT, #12
75 mov x0, #(0xf << EVNTI_SHIFT)
76 orr x0, x0, #EVNTEN_BIT
77 msr CNTKCTL_EL1, x0
89 mov x0, #((CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES << CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT) | \
91 msr CORTEX_A57_L2CTLR_EL1, x0
126 mov x0, #(CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES << CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT)
127 msr CORTEX_A57_L2CTLR_EL1, x0
[all …]
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| /device/linaro/bootloader/arm-trusted-firmware/bl32/tsp/aarch64/ |
| D | tsp_entrypoint.S | 25 ldp x6, x7, [x0, #TSP_ARG6]
26 ldp x4, x5, [x0, #TSP_ARG4]
27 ldp x2, x3, [x0, #TSP_ARG2]
28 ldp x0, x1, [x0, #TSP_ARG0]
52 adr x0, tsp_exceptions
53 msr vbar_el1, x0
69 mrs x0, sctlr_el1
70 orr x0, x0, x1
71 msr sctlr_el1, x0
83 adr x0, __RW_START__
[all …]
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| /device/linaro/bootloader/arm-trusted-firmware/common/aarch64/ |
| D | debug.S | 39 udiv x0, x4, x5 /* Get the quotient */
40 msub x4, x0, x5, x4 /* Find the remainder */
41 add x0, x0, #ASCII_OFFSET_NUM /* Convert to ascii */
63 mov x5, x0
68 cbz x0, _assert_loop
97 cbz x0, 2f
114 lsrv x0, x4, x5
115 and x0, x0, #0xf
116 cmp x0, #0xA
121 add x0, x0, #0x27
[all …]
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| /device/linaro/bootloader/arm-trusted-firmware/bl31/aarch64/ |
| D | crash_reporting.S | 63 mov x0, '\n'
116 mrs x0, tpidr_el3
117 stp x8, x9, [x0]
118 stp x10, x11, [x0, #REG_SIZE * 2]
119 stp x12, x13, [x0, #REG_SIZE * 4]
120 stp x14, x15, [x0, #REG_SIZE * 6]
133 mov sp, x0
135 mrs x0, tpidr_el3
137 add x0, x0, #CPU_DATA_CRASH_BUF_OFFSET
139 msr tpidr_el3, x0
[all …]
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| D | bl31_entrypoint.S | 31 mov x20, x0
55 mov x0, x20
78 mov x0, 0
102 adr x0, __DATA_START__
104 sub x1, x1, x0
107 adr x0, __BSS_START__
109 sub x1, x1, x0
131 str x1, [x0]
175 mov x0, #DISABLE_DCACHE
179 mrs x0, sctlr_el3
[all …]
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| /device/linaro/bootloader/arm-trusted-firmware/plat/qemu/aarch64/ |
| D | plat_helpers.S | 24 mrs x0, mpidr_el1
33 and x1, x0, #MPIDR_CPU_MASK
34 and x0, x0, #MPIDR_CLUSTER_MASK
35 add x0, x1, x0, LSR #6
47 mrs x0, mpidr_el1
48 and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
49 cmp x0, #QEMU_PRIMARY_CPU
66 lsl x0, x0, #PLAT_QEMU_HOLD_ENTRY_SHIFT
71 ldr x1, [x2, x0]
73 mov_imm x0, PLAT_QEMU_TRUSTED_MAILBOX_BASE
[all …]
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| /device/linaro/bootloader/OpenPlatformPkg/Platforms/Marvell/ |
| D | Marvell.dec | 66 gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x0 }|VOID*|0x30000005
67 gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x0 }|VOID*|0x30000006
68 gMarvellTokenSpaceGuid.PcdChip0MppSel2|{ 0x0 }|VOID*|0x30000007
69 gMarvellTokenSpaceGuid.PcdChip0MppSel3|{ 0x0 }|VOID*|0x30000008
70 gMarvellTokenSpaceGuid.PcdChip0MppSel4|{ 0x0 }|VOID*|0x30000009
71 gMarvellTokenSpaceGuid.PcdChip0MppSel5|{ 0x0 }|VOID*|0x30000010
72 gMarvellTokenSpaceGuid.PcdChip0MppSel6|{ 0x0 }|VOID*|0x30000011
73 gMarvellTokenSpaceGuid.PcdChip0MppSel7|{ 0x0 }|VOID*|0x30000012
78 gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0x0 }|VOID*|0x30000016
79 gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0x0 }|VOID*|0x30000017
[all …]
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| /device/linaro/bootloader/OpenPlatformPkg/Platforms/Marvell/Armada/ |
| D | Armada70x0.dsc | 64 gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3 }
71 gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0x4, 0x4, 0x0, 0x3, 0x3, 0x3, 0x3, 0x0, 0x0, 0x0 }
72 gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x9, 0xA }
73 gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0xA, 0x0, 0x7, 0x0, 0x7, 0x7, 0x7, 0x2, 0x2, 0x0 }
74 gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x0, 0x0, 0x0, 0x0, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 }
76 gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0xE, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
80 gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x0 }
83 gMarvellTokenSpaceGuid.PcdEepromI2cBuses|{ 0x0, 0x0 }
113 gMarvellTokenSpaceGuid.PcdUtmiPhyUtmiPort|L"0x0;0x1"
122 gMarvellTokenSpaceGuid.PcdPhyConnectionTypes|{ 0x4, 0x4, 0x0 }
[all …]
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| /device/linaro/bootloader/arm-trusted-firmware/plat/arm/css/common/aarch64/ |
| D | css_helpers.S | 35 mov_imm x0, PLAT_ARM_TRUSTED_MAILBOX_BASE
39 ldr x1, [x0]
63 mov_imm x0, PLAT_ARM_TRUSTED_MAILBOX_BASE
64 ldr x0, [x0]
77 and x1, x0, #MPIDR_CPU_MASK
78 and x0, x0, #MPIDR_CLUSTER_MASK
79 eor x0, x0, #(1 << MPIDR_AFFINITY_BITS) // swap cluster order
80 add x0, x1, x0, LSR #6
95 mov x4, x0
99 cmp x0, x1
[all …]
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| /device/linaro/bootloader/arm-trusted-firmware/plat/rockchip/common/aarch64/ |
| D | plat_helpers.S | 35 mrs x0, midr_el1
36 ubfx x0, x0, MIDR_PN_SHIFT, #12
46 mov x0, #((5 << CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT) | \
48 msr CORTEX_A72_L2CTLR_EL1, x0
55 mrs x0, mpidr_el1
56 and x1, x0, #MPIDR_CPU_MASK
57 and x0, x0, #MPIDR_CLUSTER_MASK
58 add x0, x1, x0, LSR #PLAT_RK_CLST_TO_CPUID_SHIFT
78 and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
79 cmp x0, #PLAT_RK_PRIMARY_CPU
[all …]
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| /device/linaro/bootloader/arm-trusted-firmware/plat/hisilicon/hikey960/aarch64/ |
| D | hikey960_helpers.S | 25 mrs x0, mpidr_el1
26 and x1, x0, #MPIDR_CPU_MASK
27 and x0, x0, #MPIDR_CLUSTER_MASK
28 add x0, x1, x0, LSR #6
51 mov_imm x0, CRASH_CONSOLE_BASE
82 and x1, x0, #1
84 and x1, x0, #2
86 and x1, x0, #4
88 and x1, x0, #8
147 mrs x0, CORTEX_A53_ECTLR_EL1
[all …]
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| /device/linaro/bootloader/arm-trusted-firmware/plat/arm/common/aarch64/ |
| D | arm_helpers.S | 25 mrs x0, mpidr_el1
37 and x1, x0, #MPIDR_CPU_MASK
38 and x0, x0, #MPIDR_CLUSTER_MASK
39 add x0, x1, x0, LSR #6
51 mov_imm x0, PLAT_ARM_CRASH_UART_BASE
98 mrs x0, id_aa64dfr0_el1
99 ubfx x0, x0, #ID_AA64DFR0_PMS_SHIFT, #ID_AA64DFR0_PMS_LENGTH
100 cmp x0, #0x1
109 mrs x0, pmblimitr_el1
110 bic x0, x0, #1
[all …]
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