1#Copyright (C) 2016 Marvell International Ltd. 2# 3#Marvell BSD License Option 4# 5#If you received this File from Marvell, you may opt to use, redistribute and/or 6#modify this File under the following licensing terms. 7#Redistribution and use in source and binary forms, with or without modification, 8#are permitted provided that the following conditions are met: 9# 10# * Redistributions of source code must retain the above copyright notice, 11# this list of conditions and the following disclaimer. 12# 13# * Redistributions in binary form must reproduce the above copyright 14# notice, this list of conditions and the following disclaimer in the 15# documentation and/or other materials provided with the distribution. 16# 17# * Neither the name of Marvell nor the names of its contributors may be 18# used to endorse or promote products derived from this software without 19# specific prior written permission. 20# 21#THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 22#ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23#WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24#DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 25#ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26#(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 27#LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 28#ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29#(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 30#SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31# 32################################################################################ 33# 34# Defines Section - statements that will be processed to create a Makefile. 35# 36################################################################################ 37[Defines] 38 PLATFORM_NAME = Armada70x0 39 PLATFORM_GUID = f837e231-cfc7-4f56-9a0f-5b218d746ae3 40 PLATFORM_VERSION = 0.1 41 DSC_SPECIFICATION = 0x00010005 42 OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) 43 SUPPORTED_ARCHITECTURES = AARCH64 44 BUILD_TARGETS = DEBUG|RELEASE 45 SKUID_IDENTIFIER = DEFAULT 46 FLASH_DEFINITION = OpenPlatformPkg/Platforms/Marvell/Armada/Armada70x0.fdf 47 48!include Armada.dsc.inc 49 50################################################################################ 51# 52# Pcd Section - list of all EDK II PCD Entries defined by this Platform 53# 54################################################################################ 55[PcdsFixedAtBuild.common] 56 #MPP 57 gMarvellTokenSpaceGuid.PcdMppChipCount|2 58 59 # APN806-A0 MPP SET 60 gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE 61 gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000 62 gMarvellTokenSpaceGuid.PcdChip0MppPinCount|20 63 gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 } 64 gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3 } 65 66 # CP110 MPP SET - Router configuration 67 gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE 68 gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000 69 gMarvellTokenSpaceGuid.PcdChip1MppPinCount|64 70 gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4 } 71 gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0x4, 0x4, 0x0, 0x3, 0x3, 0x3, 0x3, 0x0, 0x0, 0x0 } 72 gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x9, 0xA } 73 gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0xA, 0x0, 0x7, 0x0, 0x7, 0x7, 0x7, 0x2, 0x2, 0x0 } 74 gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x0, 0x0, 0x0, 0x0, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 } 75 gMarvellTokenSpaceGuid.PcdChip1MppSel5|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0xE, 0xE, 0xE, 0xE } 76 gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0xE, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 } 77 78 # I2C 79 gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x50, 0x57, 0x60 } 80 gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x0 } 81 gMarvellTokenSpaceGuid.PcdI2cBaseAddresses|L"0xF2701000;0xF2701100" 82 gMarvellTokenSpaceGuid.PcdEepromI2cAddresses|{ 0x50, 0x57 } 83 gMarvellTokenSpaceGuid.PcdEepromI2cBuses|{ 0x0, 0x0 } 84 gMarvellTokenSpaceGuid.PcdI2cClockFrequency|250000000 85 gMarvellTokenSpaceGuid.PcdI2cBaudRate|100000 86 gMarvellTokenSpaceGuid.PcdI2cBusCount|2 87 88 #SPI 89 gMarvellTokenSpaceGuid.PcdSpiRegBase|0xF2700680 90 gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|10000000 91 gMarvellTokenSpaceGuid.PcdSpiClockFrequency|200000000 92 93 gMarvellTokenSpaceGuid.PcdSpiFlashPollCmd|0x70 94 gMarvellTokenSpaceGuid.PcdSpiFlashAddressCycles|3 95 gMarvellTokenSpaceGuid.PcdSpiFlashEraseSize|65536 96 gMarvellTokenSpaceGuid.PcdSpiFlashPageSize|256 97 gMarvellTokenSpaceGuid.PcdSpiFlashId|0x20BA18 98 99 #ComPhy 100 gMarvellTokenSpaceGuid.PcdComPhyChipCount|1 101 102 gMarvellTokenSpaceGuid.PcdChip0ComPhyMaxLanes|6 103 gMarvellTokenSpaceGuid.PcdChip0ComPhyBaseAddress|0xF2441000 104 gMarvellTokenSpaceGuid.PcdChip0Hpipe3BaseAddress|0xF2120000 105 gMarvellTokenSpaceGuid.PcdChip0ComPhyMuxBitCount|4 106 gMarvellTokenSpaceGuid.PcdChip0Compatible|L"Cp110" 107 108 #UtmiPhy 109 gMarvellTokenSpaceGuid.PcdUtmiPhyCount|2 110 gMarvellTokenSpaceGuid.PcdUtmiPhyRegUsbCfg|L"0xF2440420;0xF2440420" 111 gMarvellTokenSpaceGuid.PcdUtmiPhyRegUtmiCfg|L"0xF2440440;0xF2440444" 112 gMarvellTokenSpaceGuid.PcdUtmiPhyRegUtmiUnit|L"0xF2580000;0xF2581000" 113 gMarvellTokenSpaceGuid.PcdUtmiPhyUtmiPort|L"0x0;0x1" 114 115 gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|L"SGMII2;USB3_HOST0;SGMII0;SATA1;USB3_HOST1;PCIE2" 116 gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|L"3125;5000;1250;5000;5000;5000" 117 118 #MDIO 119 gMarvellTokenSpaceGuid.PcdMdioBaseAddress|0xF212A200 120 121 #PHY 122 gMarvellTokenSpaceGuid.PcdPhyConnectionTypes|{ 0x4, 0x4, 0x0 } 123 gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 } 124 gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE 125 126 #NET 127 gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0xff, 0x0, 0x1 } 128 gMarvellTokenSpaceGuid.PcdPp2ClockFrequency|333333333 129 gMarvellTokenSpaceGuid.PcdPp2GmacBaseAddress|0xf2130e00 130 gMarvellTokenSpaceGuid.PcdPp2GmacDevSize|0x1000 131 gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3 } 132 gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x1, 0x1, 0x0 } 133 gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ 0x3, 0x4, 0x3 } 134 gMarvellTokenSpaceGuid.PcdPp2NumPorts|3 135 gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2 } 136 gMarvellTokenSpaceGuid.PcdPp2Rfu1BaseAddress|0xf2441000 137 gMarvellTokenSpaceGuid.PcdPp2SharedAddress|0xf2000000 138 gMarvellTokenSpaceGuid.PcdPp2SmiBaseAddress|0xf212A200 139 gMarvellTokenSpaceGuid.PcdPp2XlgBaseAddress|0xf2130f00 140 gMarvellTokenSpaceGuid.PcdPp2XlgDevSize|0x1000 141 142 #PciEmulation 143 gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1 } 144 gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1 } 145 gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 } 146 147 #ResetLib 148 gMarvellTokenSpaceGuid.PcdResetRegAddress|0xf06f0084 149 gMarvellTokenSpaceGuid.PcdResetRegMask|0x1 150 151 #SATA 152 gMarvellTokenSpaceGuid.PcdSataBaseAddress|0xF2540000 153