| /external/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.h | 32 case AArch64::X0: return AArch64::W0; in getWRegFromXReg()
33 case AArch64::X1: return AArch64::W1; in getWRegFromXReg()
34 case AArch64::X2: return AArch64::W2; in getWRegFromXReg()
35 case AArch64::X3: return AArch64::W3; in getWRegFromXReg()
36 case AArch64::X4: return AArch64::W4; in getWRegFromXReg()
37 case AArch64::X5: return AArch64::W5; in getWRegFromXReg()
38 case AArch64::X6: return AArch64::W6; in getWRegFromXReg()
39 case AArch64::X7: return AArch64::W7; in getWRegFromXReg()
40 case AArch64::X8: return AArch64::W8; in getWRegFromXReg()
41 case AArch64::X9: return AArch64::W9; in getWRegFromXReg()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.h | 32 case AArch64::X0: return AArch64::W0; in getWRegFromXReg()
33 case AArch64::X1: return AArch64::W1; in getWRegFromXReg()
34 case AArch64::X2: return AArch64::W2; in getWRegFromXReg()
35 case AArch64::X3: return AArch64::W3; in getWRegFromXReg()
36 case AArch64::X4: return AArch64::W4; in getWRegFromXReg()
37 case AArch64::X5: return AArch64::W5; in getWRegFromXReg()
38 case AArch64::X6: return AArch64::W6; in getWRegFromXReg()
39 case AArch64::X7: return AArch64::W7; in getWRegFromXReg()
40 case AArch64::X8: return AArch64::W8; in getWRegFromXReg()
41 case AArch64::X9: return AArch64::W9; in getWRegFromXReg()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/Disassembler/ |
| D | AArch64Disassembler.cpp | 297 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4,
298 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9,
299 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14,
300 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19,
301 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24,
302 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29,
303 AArch64::Q30, AArch64::Q31
326 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4,
327 AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9,
328 AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14,
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64FalkorHWPFFix.cpp | 247 case AArch64::LD1i64: in getLoadInfo()
248 case AArch64::LD2i64: in getLoadInfo()
255 case AArch64::LD1i8: in getLoadInfo()
256 case AArch64::LD1i16: in getLoadInfo()
257 case AArch64::LD1i32: in getLoadInfo()
258 case AArch64::LD2i8: in getLoadInfo()
259 case AArch64::LD2i16: in getLoadInfo()
260 case AArch64::LD2i32: in getLoadInfo()
261 case AArch64::LD3i8: in getLoadInfo()
262 case AArch64::LD3i16: in getLoadInfo()
[all …]
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| D | AArch64MacroFusion.cpp | 26 if (SecondMI.getOpcode() == AArch64::Bcc) { in isArithmeticBccPair()
32 case AArch64::ADDSWri: in isArithmeticBccPair()
33 case AArch64::ADDSWrr: in isArithmeticBccPair()
34 case AArch64::ADDSXri: in isArithmeticBccPair()
35 case AArch64::ADDSXrr: in isArithmeticBccPair()
36 case AArch64::ANDSWri: in isArithmeticBccPair()
37 case AArch64::ANDSWrr: in isArithmeticBccPair()
38 case AArch64::ANDSXri: in isArithmeticBccPair()
39 case AArch64::ANDSXrr: in isArithmeticBccPair()
40 case AArch64::SUBSWri: in isArithmeticBccPair()
[all …]
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| D | AArch64InstrInfo.cpp | 69 : AArch64GenInstrInfo(AArch64::ADJCALLSTACKDOWN, AArch64::ADJCALLSTACKUP), in AArch64InstrInfo()
79 if (MI.getOpcode() == AArch64::INLINEASM) in getInstSizeInBytes()
107 case AArch64::TLSDESC_CALLSEQ: in getInstSizeInBytes()
122 case AArch64::Bcc: in parseCondBranch()
126 case AArch64::CBZW: in parseCondBranch()
127 case AArch64::CBZX: in parseCondBranch()
128 case AArch64::CBNZW: in parseCondBranch()
129 case AArch64::CBNZX: in parseCondBranch()
135 case AArch64::TBZW: in parseCondBranch()
136 case AArch64::TBZX: in parseCondBranch()
[all …]
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| D | AArch64SIMDInstrOpt.cpp | 104 RuleST2(AArch64::ST2Twov2d, AArch64::ZIP1v2i64, AArch64::ZIP2v2i64,
105 AArch64::STPQi, AArch64::FPR128RegClass),
106 RuleST2(AArch64::ST2Twov4s, AArch64::ZIP1v4i32, AArch64::ZIP2v4i32,
107 AArch64::STPQi, AArch64::FPR128RegClass),
108 RuleST2(AArch64::ST2Twov2s, AArch64::ZIP1v2i32, AArch64::ZIP2v2i32,
109 AArch64::STPDi, AArch64::FPR64RegClass),
110 RuleST2(AArch64::ST2Twov8h, AArch64::ZIP1v8i16, AArch64::ZIP2v8i16,
111 AArch64::STPQi, AArch64::FPR128RegClass),
112 RuleST2(AArch64::ST2Twov4h, AArch64::ZIP1v4i16, AArch64::ZIP2v4i16,
113 AArch64::STPDi, AArch64::FPR64RegClass),
[all …]
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| D | AArch64LoadStoreOptimizer.cpp | 197 case AArch64::STRBBui: in isNarrowStore()
198 case AArch64::STURBBi: in isNarrowStore()
199 case AArch64::STRHHui: in isNarrowStore()
200 case AArch64::STURHHi: in isNarrowStore()
210 case AArch64::LDRBBui: in getMemScale()
211 case AArch64::LDURBBi: in getMemScale()
212 case AArch64::LDRSBWui: in getMemScale()
213 case AArch64::LDURSBWi: in getMemScale()
214 case AArch64::STRBBui: in getMemScale()
215 case AArch64::STURBBi: in getMemScale()
[all …]
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| D | AArch64PBQPRegAlloc.cpp | 38 return AArch64::FPR32RegClass.contains(reg) || in isFPReg()
39 AArch64::FPR64RegClass.contains(reg) || in isFPReg()
40 AArch64::FPR128RegClass.contains(reg); in isFPReg()
48 case AArch64::S1: in isOdd()
49 case AArch64::S3: in isOdd()
50 case AArch64::S5: in isOdd()
51 case AArch64::S7: in isOdd()
52 case AArch64::S9: in isOdd()
53 case AArch64::S11: in isOdd()
54 case AArch64::S13: in isOdd()
[all …]
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| D | AArch64CondBrTuning.cpp | 95 if (MO.isReg() && MO.isDead() && MO.getReg() == AArch64::NZCV) in convertToFlagSetting()
104 NewDestReg = Is64Bit ? AArch64::XZR : AArch64::WZR; in convertToFlagSetting()
121 case AArch64::CBZW: in convertToCondBr()
122 case AArch64::CBZX: in convertToCondBr()
125 case AArch64::CBNZW: in convertToCondBr()
126 case AArch64::CBNZX: in convertToCondBr()
129 case AArch64::TBZW: in convertToCondBr()
130 case AArch64::TBZX: in convertToCondBr()
133 case AArch64::TBNZW: in convertToCondBr()
134 case AArch64::TBNZX: in convertToCondBr()
[all …]
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| /external/llvm/lib/Target/AArch64/Disassembler/ |
| D | AArch64Disassembler.cpp | 256 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4,
257 AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9,
258 AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14,
259 AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19,
260 AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24,
261 AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29,
262 AArch64::Q30, AArch64::Q31
285 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4,
286 AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9,
287 AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14,
[all …]
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| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| D | AArch64InstPrinter.cpp | 58 if (Opcode == AArch64::SYSxt) in printInst()
65 if (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri || in printInst()
66 Opcode == AArch64::UBFMXri || Opcode == AArch64::UBFMWri) { in printInst()
72 bool IsSigned = (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri); in printInst()
73 bool Is64Bit = (Opcode == AArch64::SBFMXri || Opcode == AArch64::UBFMXri); in printInst()
115 if (Opcode == AArch64::UBFMWri && imms != 0x1F && ((imms + 1) == immr)) { in printInst()
118 } else if (Opcode == AArch64::UBFMXri && imms != 0x3f && in printInst()
122 } else if (Opcode == AArch64::UBFMWri && imms == 0x1f) { in printInst()
125 } else if (Opcode == AArch64::UBFMXri && imms == 0x3f) { in printInst()
128 } else if (Opcode == AArch64::SBFMWri && imms == 0x1f) { in printInst()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/InstPrinter/ |
| D | AArch64InstPrinter.cpp | 67 if (Opcode == AArch64::SYSxt) in printInst()
74 if (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri || in printInst()
75 Opcode == AArch64::UBFMXri || Opcode == AArch64::UBFMWri) { in printInst()
81 bool IsSigned = (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri); in printInst()
82 bool Is64Bit = (Opcode == AArch64::SBFMXri || Opcode == AArch64::UBFMXri); in printInst()
124 if (Opcode == AArch64::UBFMWri && imms != 0x1F && ((imms + 1) == immr)) { in printInst()
127 } else if (Opcode == AArch64::UBFMXri && imms != 0x3f && in printInst()
131 } else if (Opcode == AArch64::UBFMWri && imms == 0x1f) { in printInst()
134 } else if (Opcode == AArch64::UBFMXri && imms == 0x3f) { in printInst()
137 } else if (Opcode == AArch64::SBFMWri && imms == 0x1f) { in printInst()
[all …]
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.cpp | 36 : AArch64GenInstrInfo(AArch64::ADJCALLSTACKDOWN, AArch64::ADJCALLSTACKUP), in AArch64InstrInfo()
46 if (MI.getOpcode() == AArch64::INLINEASM) in GetInstSizeInBytes()
70 case AArch64::Bcc: in parseCondBranch()
74 case AArch64::CBZW: in parseCondBranch()
75 case AArch64::CBZX: in parseCondBranch()
76 case AArch64::CBNZW: in parseCondBranch()
77 case AArch64::CBNZX: in parseCondBranch()
83 case AArch64::TBZW: in parseCondBranch()
84 case AArch64::TBZX: in parseCondBranch()
85 case AArch64::TBNZW: in parseCondBranch()
[all …]
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| D | AArch64LoadStoreOptimizer.cpp | 186 case AArch64::LDRBBui: in getBitExtrOpcode()
187 case AArch64::LDURBBi: in getBitExtrOpcode()
188 case AArch64::LDRHHui: in getBitExtrOpcode()
189 case AArch64::LDURHHi: in getBitExtrOpcode()
190 return AArch64::UBFMWri; in getBitExtrOpcode()
191 case AArch64::LDRSBWui: in getBitExtrOpcode()
192 case AArch64::LDURSBWi: in getBitExtrOpcode()
193 case AArch64::LDRSHWui: in getBitExtrOpcode()
194 case AArch64::LDURSHWi: in getBitExtrOpcode()
195 return AArch64::SBFMWri; in getBitExtrOpcode()
[all …]
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| D | AArch64PBQPRegAlloc.cpp | 38 return AArch64::FPR32RegClass.contains(reg) || in isFPReg()
39 AArch64::FPR64RegClass.contains(reg) || in isFPReg()
40 AArch64::FPR128RegClass.contains(reg); in isFPReg()
48 case AArch64::S1: in isOdd()
49 case AArch64::S3: in isOdd()
50 case AArch64::S5: in isOdd()
51 case AArch64::S7: in isOdd()
52 case AArch64::S9: in isOdd()
53 case AArch64::S11: in isOdd()
54 case AArch64::S13: in isOdd()
[all …]
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| D | AArch64RegisterBankInfo.cpp | 29 : RegisterBankInfo(AArch64::NumRegisterBanks) { in AArch64RegisterBankInfo()
31 createRegisterBank(AArch64::GPRRegBankID, "GPR"); in AArch64RegisterBankInfo()
34 addRegBankCoverage(AArch64::GPRRegBankID, AArch64::GPR64allRegClassID, TRI); in AArch64RegisterBankInfo()
35 const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID); in AArch64RegisterBankInfo()
37 assert(RBGPR.covers(*TRI.getRegClass(AArch64::GPR32RegClassID)) && in AArch64RegisterBankInfo()
42 createRegisterBank(AArch64::FPRRegBankID, "FPR"); in AArch64RegisterBankInfo()
45 addRegBankCoverage(AArch64::FPRRegBankID, AArch64::QQQQRegClassID, TRI); in AArch64RegisterBankInfo()
46 const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID); in AArch64RegisterBankInfo()
48 assert(RBFPR.covers(*TRI.getRegClass(AArch64::QQRegClassID)) && in AArch64RegisterBankInfo()
50 assert(RBFPR.covers(*TRI.getRegClass(AArch64::FPR64RegClassID)) && in AArch64RegisterBankInfo()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenCallingConv.inc | 81 if (unsigned Reg = State.AllocateReg(AArch64::X8, AArch64::W8)) {
94 if (unsigned Reg = State.AllocateReg(AArch64::X18)) {
102 if (unsigned Reg = State.AllocateReg(AArch64::X20, AArch64::W20)) {
111 if (unsigned Reg = State.AllocateReg(AArch64::X21, AArch64::W21)) {
137 …AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64…
140 …AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64…
151 AArch64::X0, AArch64::X2, AArch64::X4, AArch64::X6
154 AArch64::X0, AArch64::X1, AArch64::X3, AArch64::X5
166 AArch64::X7
176 …AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64…
[all …]
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| D | AArch64GenMCCodeEmitter.inc | 4536 case AArch64::ADDSWrr:
4537 case AArch64::ADDSXrr:
4538 case AArch64::ADDWrr:
4539 case AArch64::ADDXrr:
4540 case AArch64::ADDlowTLS:
4541 case AArch64::ADJCALLSTACKDOWN:
4542 case AArch64::ADJCALLSTACKUP:
4543 case AArch64::AESIMCrrTied:
4544 case AArch64::AESMCrrTied:
4545 case AArch64::ANDSWrr:
[all …]
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| D | AArch64GenRegisterInfo.inc | 18 namespace AArch64 {
683 } // end namespace AArch64
687 namespace AArch64 {
791 } // end namespace AArch64
796 namespace AArch64 {
803 } // end namespace AArch64
808 namespace AArch64 {
912 } // end namespace AArch64
2173 { AArch64::FFR },
2174 { AArch64::W29 },
[all …]
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| D | AArch64GenRegisterBank.inc | 12 namespace AArch64 {
19 } // end namespace AArch64
36 namespace AArch64 {
39 (1u << (AArch64::CCRRegClassID - 0)) |
50 (1u << (AArch64::FPR8RegClassID - 0)) |
51 (1u << (AArch64::FPR16RegClassID - 0)) |
52 (1u << (AArch64::FPR32RegClassID - 0)) |
53 (1u << (AArch64::FPR64RegClassID - 0)) |
54 (1u << (AArch64::DDRegClassID - 0)) |
55 (1u << (AArch64::FPR128RegClassID - 0)) |
[all …]
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| D | AArch64GenAsmMatcher.inc | 6122 Inst.addOperand(MCOperand::createReg(AArch64::WZR));
6125 Inst.addOperand(MCOperand::createReg(AArch64::XZR));
6302 Inst.addOperand(MCOperand::createReg(AArch64::LR));
8365 DiagnosticPredicate DP(Operand.isGPR64WithShiftExtend<AArch64::GPR64commonRegClassID, 16>());
8374 DiagnosticPredicate DP(Operand.isGPR64WithShiftExtend<AArch64::GPR64commonRegClassID, 32>());
8383 DiagnosticPredicate DP(Operand.isGPR64WithShiftExtend<AArch64::GPR64commonRegClassID, 64>());
8392 DiagnosticPredicate DP(Operand.isGPR64WithShiftExtend<AArch64::GPR64commonRegClassID, 8>());
8408 DiagnosticPredicate DP(Operand.isGPR64WithShiftExtend<AArch64::GPR64RegClassID, 16>());
8417 DiagnosticPredicate DP(Operand.isGPR64WithShiftExtend<AArch64::GPR64RegClassID, 32>());
8426 DiagnosticPredicate DP(Operand.isGPR64WithShiftExtend<AArch64::GPR64RegClassID, 64>());
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Support/ |
| D | AArch64TargetParser.def | 20 ARMBuildAttrs::CPUArch::v8_A, FK_NONE, AArch64::AEK_NONE)
23 (AArch64::AEK_CRYPTO | AArch64::AEK_FP | AArch64::AEK_SIMD))
26 (AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
27 AArch64::AEK_SIMD | AArch64::AEK_LSE | AArch64::AEK_RDM))
30 (AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
31 AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE |
32 AArch64::AEK_RDM))
35 (AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
36 AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE |
37 AArch64::AEK_RDM | AArch64::AEK_RCPC))
[all …]
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| /external/swiftshader/third_party/llvm-subzero/include/llvm/Support/ |
| D | AArch64TargetParser.def | 20 ARMBuildAttrs::CPUArch::v8_A, FK_NONE, AArch64::AEK_NONE)
23 (AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
24 AArch64::AEK_SIMD | AArch64::AEK_LSE))
27 (AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
28 AArch64::AEK_SIMD | AArch64::AEK_LSE))
31 (AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
32 AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE))
39 AARCH64_ARCH_EXT_NAME("invalid", AArch64::AEK_INVALID, nullptr, nullptr)
40 AARCH64_ARCH_EXT_NAME("none", AArch64::AEK_NONE, nullptr, nullptr)
41 AARCH64_ARCH_EXT_NAME("crc", AArch64::AEK_CRC, "+crc", "-crc")
[all …]
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| /external/llvm/include/llvm/Support/ |
| D | AArch64TargetParser.def | 20 ARMBuildAttrs::CPUArch::v8_A, FK_NONE, AArch64::AEK_NONE)
23 (AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
24 AArch64::AEK_SIMD | AArch64::AEK_FP16 | AArch64::AEK_PROFILE))
27 (AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
28 AArch64::AEK_SIMD | AArch64::AEK_FP16 | AArch64::AEK_PROFILE))
31 (AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
32 AArch64::AEK_SIMD | AArch64::AEK_FP16 | AArch64::AEK_PROFILE |
33 AArch64::AEK_RAS))
40 AARCH64_ARCH_EXT_NAME("invalid", AArch64::AEK_INVALID, nullptr, nullptr)
41 AARCH64_ARCH_EXT_NAME("none", AArch64::AEK_NONE, nullptr, nullptr)
[all …]
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