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1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|*                                                                            *|
3|* Calling Convention Implementation Fragment                                 *|
4|*                                                                            *|
5|* Automatically generated file, do not edit!                                 *|
6|*                                                                            *|
7\*===----------------------------------------------------------------------===*/
8
9static bool CC_AArch64_AAPCS(unsigned ValNo, MVT ValVT,
10                             MVT LocVT, CCValAssign::LocInfo LocInfo,
11                             ISD::ArgFlagsTy ArgFlags, CCState &State);
12static bool CC_AArch64_DarwinPCS(unsigned ValNo, MVT ValVT,
13                                 MVT LocVT, CCValAssign::LocInfo LocInfo,
14                                 ISD::ArgFlagsTy ArgFlags, CCState &State);
15static bool CC_AArch64_DarwinPCS_VarArg(unsigned ValNo, MVT ValVT,
16                                        MVT LocVT, CCValAssign::LocInfo LocInfo,
17                                        ISD::ArgFlagsTy ArgFlags, CCState &State);
18static bool CC_AArch64_GHC(unsigned ValNo, MVT ValVT,
19                           MVT LocVT, CCValAssign::LocInfo LocInfo,
20                           ISD::ArgFlagsTy ArgFlags, CCState &State);
21static bool CC_AArch64_WebKit_JS(unsigned ValNo, MVT ValVT,
22                                 MVT LocVT, CCValAssign::LocInfo LocInfo,
23                                 ISD::ArgFlagsTy ArgFlags, CCState &State);
24static bool CC_AArch64_Win64_VarArg(unsigned ValNo, MVT ValVT,
25                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
26                                    ISD::ArgFlagsTy ArgFlags, CCState &State);
27static bool RetCC_AArch64_AAPCS(unsigned ValNo, MVT ValVT,
28                                MVT LocVT, CCValAssign::LocInfo LocInfo,
29                                ISD::ArgFlagsTy ArgFlags, CCState &State);
30static bool RetCC_AArch64_WebKit_JS(unsigned ValNo, MVT ValVT,
31                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
32                                    ISD::ArgFlagsTy ArgFlags, CCState &State);
33
34
35static bool CC_AArch64_AAPCS(unsigned ValNo, MVT ValVT,
36                             MVT LocVT, CCValAssign::LocInfo LocInfo,
37                             ISD::ArgFlagsTy ArgFlags, CCState &State) {
38
39  if (LocVT == MVT::iPTR) {
40    LocVT = MVT::i64;
41    LocInfo = CCValAssign::BCvt;
42  }
43
44  if (LocVT == MVT::v2f32) {
45    LocVT = MVT::v2i32;
46    LocInfo = CCValAssign::BCvt;
47  }
48
49  if (LocVT == MVT::v2f64 ||
50      LocVT == MVT::v4f32) {
51    LocVT = MVT::v2i64;
52    LocInfo = CCValAssign::BCvt;
53  }
54
55  if (State.getMachineFunction().getDataLayout().isBigEndian()) {
56    if (LocVT == MVT::v2i32 ||
57        LocVT == MVT::v2f32 ||
58        LocVT == MVT::v4i16 ||
59        LocVT == MVT::v4f16 ||
60        LocVT == MVT::v8i8) {
61      LocVT = MVT::f64;
62      LocInfo = CCValAssign::BCvt;
63    }
64  }
65
66  if (State.getMachineFunction().getDataLayout().isBigEndian()) {
67    if (LocVT == MVT::v2i64 ||
68        LocVT == MVT::v2f64 ||
69        LocVT == MVT::v4i32 ||
70        LocVT == MVT::v4f32 ||
71        LocVT == MVT::v8i16 ||
72        LocVT == MVT::v8f16 ||
73        LocVT == MVT::v16i8) {
74      LocVT = MVT::f128;
75      LocInfo = CCValAssign::BCvt;
76    }
77  }
78
79  if (ArgFlags.isSRet()) {
80    if (LocVT == MVT::i64) {
81      if (unsigned Reg = State.AllocateReg(AArch64::X8, AArch64::W8)) {
82        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
83        return false;
84      }
85    }
86  }
87
88  if (ArgFlags.isByVal()) {
89    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, 8, ArgFlags);
90    return false;
91  }
92
93  if (ArgFlags.isNest()) {
94    if (unsigned Reg = State.AllocateReg(AArch64::X18)) {
95      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
96      return false;
97    }
98  }
99
100  if (ArgFlags.isSwiftSelf()) {
101    if (LocVT == MVT::i64) {
102      if (unsigned Reg = State.AllocateReg(AArch64::X20, AArch64::W20)) {
103        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
104        return false;
105      }
106    }
107  }
108
109  if (ArgFlags.isSwiftError()) {
110    if (LocVT == MVT::i64) {
111      if (unsigned Reg = State.AllocateReg(AArch64::X21, AArch64::W21)) {
112        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
113        return false;
114      }
115    }
116  }
117
118  if (ArgFlags.isInConsecutiveRegs()) {
119    if (CC_AArch64_Custom_Block(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
120        return false;
121  }
122
123  if (LocVT == MVT::i1 ||
124      LocVT == MVT::i8 ||
125      LocVT == MVT::i16) {
126    LocVT = MVT::i32;
127    if (ArgFlags.isSExt())
128        LocInfo = CCValAssign::SExt;
129    else if (ArgFlags.isZExt())
130        LocInfo = CCValAssign::ZExt;
131    else
132        LocInfo = CCValAssign::AExt;
133  }
134
135  if (LocVT == MVT::i32) {
136    static const MCPhysReg RegList1[] = {
137      AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7
138    };
139    static const MCPhysReg RegList2[] = {
140      AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
141    };
142    if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
143      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
144      return false;
145    }
146  }
147
148  if (LocVT == MVT::i64) {
149    if (ArgFlags.isSplit()) {
150      static const MCPhysReg RegList3[] = {
151        AArch64::X0, AArch64::X2, AArch64::X4, AArch64::X6
152      };
153      static const MCPhysReg RegList4[] = {
154        AArch64::X0, AArch64::X1, AArch64::X3, AArch64::X5
155      };
156      if (unsigned Reg = State.AllocateReg(RegList3, RegList4)) {
157        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
158        return false;
159      }
160    }
161  }
162
163  if (LocVT == MVT::i64) {
164    if (ArgFlags.isSplit()) {
165      static const MCPhysReg ShadowRegList5[] = {
166        AArch64::X7
167      };
168      unsigned Offset6 = State.AllocateStack(8, 16, ShadowRegList5);
169      State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo));
170      return false;
171    }
172  }
173
174  if (LocVT == MVT::i64) {
175    static const MCPhysReg RegList7[] = {
176      AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
177    };
178    static const MCPhysReg RegList8[] = {
179      AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7
180    };
181    if (unsigned Reg = State.AllocateReg(RegList7, RegList8)) {
182      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
183      return false;
184    }
185  }
186
187  if (LocVT == MVT::f16) {
188    static const MCPhysReg RegList9[] = {
189      AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7
190    };
191    static const MCPhysReg RegList10[] = {
192      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
193    };
194    if (unsigned Reg = State.AllocateReg(RegList9, RegList10)) {
195      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
196      return false;
197    }
198  }
199
200  if (LocVT == MVT::f32) {
201    static const MCPhysReg RegList11[] = {
202      AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7
203    };
204    static const MCPhysReg RegList12[] = {
205      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
206    };
207    if (unsigned Reg = State.AllocateReg(RegList11, RegList12)) {
208      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
209      return false;
210    }
211  }
212
213  if (LocVT == MVT::f64) {
214    static const MCPhysReg RegList13[] = {
215      AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
216    };
217    static const MCPhysReg RegList14[] = {
218      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
219    };
220    if (unsigned Reg = State.AllocateReg(RegList13, RegList14)) {
221      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
222      return false;
223    }
224  }
225
226  if (LocVT == MVT::v1i64 ||
227      LocVT == MVT::v2i32 ||
228      LocVT == MVT::v4i16 ||
229      LocVT == MVT::v8i8 ||
230      LocVT == MVT::v1f64 ||
231      LocVT == MVT::v2f32 ||
232      LocVT == MVT::v4f16) {
233    static const MCPhysReg RegList15[] = {
234      AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
235    };
236    static const MCPhysReg RegList16[] = {
237      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
238    };
239    if (unsigned Reg = State.AllocateReg(RegList15, RegList16)) {
240      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
241      return false;
242    }
243  }
244
245  if (LocVT == MVT::f128 ||
246      LocVT == MVT::v2i64 ||
247      LocVT == MVT::v4i32 ||
248      LocVT == MVT::v8i16 ||
249      LocVT == MVT::v16i8 ||
250      LocVT == MVT::v4f32 ||
251      LocVT == MVT::v2f64 ||
252      LocVT == MVT::v8f16) {
253    static const MCPhysReg RegList17[] = {
254      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
255    };
256    if (unsigned Reg = State.AllocateReg(RegList17)) {
257      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
258      return false;
259    }
260  }
261
262  if (LocVT == MVT::i1 ||
263      LocVT == MVT::i8 ||
264      LocVT == MVT::i16 ||
265      LocVT == MVT::f16) {
266    unsigned Offset18 = State.AllocateStack(8, 8);
267    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset18, LocVT, LocInfo));
268    return false;
269  }
270
271  if (LocVT == MVT::i32 ||
272      LocVT == MVT::f32) {
273    unsigned Offset19 = State.AllocateStack(8, 8);
274    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset19, LocVT, LocInfo));
275    return false;
276  }
277
278  if (LocVT == MVT::i64 ||
279      LocVT == MVT::f64 ||
280      LocVT == MVT::v1f64 ||
281      LocVT == MVT::v2f32 ||
282      LocVT == MVT::v1i64 ||
283      LocVT == MVT::v2i32 ||
284      LocVT == MVT::v4i16 ||
285      LocVT == MVT::v8i8 ||
286      LocVT == MVT::v4f16) {
287    unsigned Offset20 = State.AllocateStack(8, 8);
288    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset20, LocVT, LocInfo));
289    return false;
290  }
291
292  if (LocVT == MVT::f128 ||
293      LocVT == MVT::v2i64 ||
294      LocVT == MVT::v4i32 ||
295      LocVT == MVT::v8i16 ||
296      LocVT == MVT::v16i8 ||
297      LocVT == MVT::v4f32 ||
298      LocVT == MVT::v2f64 ||
299      LocVT == MVT::v8f16) {
300    unsigned Offset21 = State.AllocateStack(16, 16);
301    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset21, LocVT, LocInfo));
302    return false;
303  }
304
305  return true;  // CC didn't match.
306}
307
308
309static bool CC_AArch64_DarwinPCS(unsigned ValNo, MVT ValVT,
310                                 MVT LocVT, CCValAssign::LocInfo LocInfo,
311                                 ISD::ArgFlagsTy ArgFlags, CCState &State) {
312
313  if (LocVT == MVT::iPTR) {
314    LocVT = MVT::i64;
315    LocInfo = CCValAssign::BCvt;
316  }
317
318  if (LocVT == MVT::v2f32) {
319    LocVT = MVT::v2i32;
320    LocInfo = CCValAssign::BCvt;
321  }
322
323  if (LocVT == MVT::v2f64 ||
324      LocVT == MVT::v4f32 ||
325      LocVT == MVT::f128) {
326    LocVT = MVT::v2i64;
327    LocInfo = CCValAssign::BCvt;
328  }
329
330  if (ArgFlags.isSRet()) {
331    if (LocVT == MVT::i64) {
332      if (unsigned Reg = State.AllocateReg(AArch64::X8, AArch64::W8)) {
333        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
334        return false;
335      }
336    }
337  }
338
339  if (ArgFlags.isByVal()) {
340    State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, 8, ArgFlags);
341    return false;
342  }
343
344  if (ArgFlags.isSwiftSelf()) {
345    if (LocVT == MVT::i64) {
346      if (unsigned Reg = State.AllocateReg(AArch64::X20, AArch64::W20)) {
347        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
348        return false;
349      }
350    }
351  }
352
353  if (ArgFlags.isSwiftError()) {
354    if (LocVT == MVT::i64) {
355      if (unsigned Reg = State.AllocateReg(AArch64::X21, AArch64::W21)) {
356        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
357        return false;
358      }
359    }
360  }
361
362  if (ArgFlags.isInConsecutiveRegs()) {
363    if (CC_AArch64_Custom_Block(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
364        return false;
365  }
366
367  if (LocVT == MVT::i1 ||
368      LocVT == MVT::i8 ||
369      LocVT == MVT::i16) {
370    LocVT = MVT::i32;
371    if (ArgFlags.isSExt())
372        LocInfo = CCValAssign::SExt;
373    else if (ArgFlags.isZExt())
374        LocInfo = CCValAssign::ZExt;
375    else
376        LocInfo = CCValAssign::AExt;
377  }
378
379  if (LocVT == MVT::i32) {
380    static const MCPhysReg RegList1[] = {
381      AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7
382    };
383    static const MCPhysReg RegList2[] = {
384      AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
385    };
386    if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
387      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
388      return false;
389    }
390  }
391
392  if (LocVT == MVT::i64) {
393    if (ArgFlags.isSplit()) {
394      static const MCPhysReg RegList3[] = {
395        AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6
396      };
397      static const MCPhysReg RegList4[] = {
398        AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6
399      };
400      if (unsigned Reg = State.AllocateReg(RegList3, RegList4)) {
401        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
402        return false;
403      }
404    }
405  }
406
407  if (LocVT == MVT::i64) {
408    if (ArgFlags.isSplit()) {
409      static const MCPhysReg ShadowRegList5[] = {
410        AArch64::X7
411      };
412      unsigned Offset6 = State.AllocateStack(8, 16, ShadowRegList5);
413      State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo));
414      return false;
415    }
416  }
417
418  if (LocVT == MVT::i64) {
419    static const MCPhysReg RegList7[] = {
420      AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
421    };
422    static const MCPhysReg RegList8[] = {
423      AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7
424    };
425    if (unsigned Reg = State.AllocateReg(RegList7, RegList8)) {
426      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
427      return false;
428    }
429  }
430
431  if (LocVT == MVT::f16) {
432    static const MCPhysReg RegList9[] = {
433      AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7
434    };
435    static const MCPhysReg RegList10[] = {
436      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
437    };
438    if (unsigned Reg = State.AllocateReg(RegList9, RegList10)) {
439      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
440      return false;
441    }
442  }
443
444  if (LocVT == MVT::f32) {
445    static const MCPhysReg RegList11[] = {
446      AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7
447    };
448    static const MCPhysReg RegList12[] = {
449      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
450    };
451    if (unsigned Reg = State.AllocateReg(RegList11, RegList12)) {
452      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
453      return false;
454    }
455  }
456
457  if (LocVT == MVT::f64) {
458    static const MCPhysReg RegList13[] = {
459      AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
460    };
461    static const MCPhysReg RegList14[] = {
462      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
463    };
464    if (unsigned Reg = State.AllocateReg(RegList13, RegList14)) {
465      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
466      return false;
467    }
468  }
469
470  if (LocVT == MVT::v1i64 ||
471      LocVT == MVT::v2i32 ||
472      LocVT == MVT::v4i16 ||
473      LocVT == MVT::v8i8 ||
474      LocVT == MVT::v1f64 ||
475      LocVT == MVT::v2f32 ||
476      LocVT == MVT::v4f16) {
477    static const MCPhysReg RegList15[] = {
478      AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
479    };
480    static const MCPhysReg RegList16[] = {
481      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
482    };
483    if (unsigned Reg = State.AllocateReg(RegList15, RegList16)) {
484      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
485      return false;
486    }
487  }
488
489  if (LocVT == MVT::v2i64 ||
490      LocVT == MVT::v4i32 ||
491      LocVT == MVT::v8i16 ||
492      LocVT == MVT::v16i8 ||
493      LocVT == MVT::v4f32 ||
494      LocVT == MVT::v2f64 ||
495      LocVT == MVT::v8f16) {
496    static const MCPhysReg RegList17[] = {
497      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
498    };
499    if (unsigned Reg = State.AllocateReg(RegList17)) {
500      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
501      return false;
502    }
503  }
504
505  if (ValVT == MVT::i1 || ValVT == MVT::i8) {
506    unsigned Offset18 = State.AllocateStack(1, 1);
507    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset18, LocVT, LocInfo));
508    return false;
509  }
510
511  if (ValVT == MVT::i16 || ValVT == MVT::f16) {
512    unsigned Offset19 = State.AllocateStack(2, 2);
513    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset19, LocVT, LocInfo));
514    return false;
515  }
516
517  if (LocVT == MVT::i32 ||
518      LocVT == MVT::f32) {
519    unsigned Offset20 = State.AllocateStack(4, 4);
520    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset20, LocVT, LocInfo));
521    return false;
522  }
523
524  if (LocVT == MVT::i64 ||
525      LocVT == MVT::f64 ||
526      LocVT == MVT::v1f64 ||
527      LocVT == MVT::v2f32 ||
528      LocVT == MVT::v1i64 ||
529      LocVT == MVT::v2i32 ||
530      LocVT == MVT::v4i16 ||
531      LocVT == MVT::v8i8 ||
532      LocVT == MVT::v4f16) {
533    unsigned Offset21 = State.AllocateStack(8, 8);
534    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset21, LocVT, LocInfo));
535    return false;
536  }
537
538  if (LocVT == MVT::v2i64 ||
539      LocVT == MVT::v4i32 ||
540      LocVT == MVT::v8i16 ||
541      LocVT == MVT::v16i8 ||
542      LocVT == MVT::v4f32 ||
543      LocVT == MVT::v2f64 ||
544      LocVT == MVT::v8f16) {
545    unsigned Offset22 = State.AllocateStack(16, 16);
546    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset22, LocVT, LocInfo));
547    return false;
548  }
549
550  return true;  // CC didn't match.
551}
552
553
554static bool CC_AArch64_DarwinPCS_VarArg(unsigned ValNo, MVT ValVT,
555                                        MVT LocVT, CCValAssign::LocInfo LocInfo,
556                                        ISD::ArgFlagsTy ArgFlags, CCState &State) {
557
558  if (LocVT == MVT::iPTR) {
559    LocVT = MVT::i64;
560    LocInfo = CCValAssign::BCvt;
561  }
562
563  if (LocVT == MVT::v2f32) {
564    LocVT = MVT::v2i32;
565    LocInfo = CCValAssign::BCvt;
566  }
567
568  if (LocVT == MVT::v2f64 ||
569      LocVT == MVT::v4f32 ||
570      LocVT == MVT::f128) {
571    LocVT = MVT::v2i64;
572    LocInfo = CCValAssign::BCvt;
573  }
574
575  if (ArgFlags.isInConsecutiveRegs()) {
576    if (CC_AArch64_Custom_Stack_Block(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
577        return false;
578  }
579
580  if (LocVT == MVT::i8 ||
581      LocVT == MVT::i16 ||
582      LocVT == MVT::i32) {
583    LocVT = MVT::i64;
584    if (ArgFlags.isSExt())
585        LocInfo = CCValAssign::SExt;
586    else if (ArgFlags.isZExt())
587        LocInfo = CCValAssign::ZExt;
588    else
589        LocInfo = CCValAssign::AExt;
590  }
591
592  if (LocVT == MVT::f16 ||
593      LocVT == MVT::f32) {
594    LocVT = MVT::f64;
595    LocInfo = CCValAssign::FPExt;
596  }
597
598  if (LocVT == MVT::i64) {
599    if (ArgFlags.isSplit()) {
600      unsigned Offset1 = State.AllocateStack(8, 16);
601      State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo));
602      return false;
603    }
604  }
605
606  if (LocVT == MVT::i64 ||
607      LocVT == MVT::f64 ||
608      LocVT == MVT::v1i64 ||
609      LocVT == MVT::v2i32 ||
610      LocVT == MVT::v4i16 ||
611      LocVT == MVT::v8i8 ||
612      LocVT == MVT::v1f64 ||
613      LocVT == MVT::v2f32 ||
614      LocVT == MVT::v4f16) {
615    unsigned Offset2 = State.AllocateStack(8, 8);
616    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
617    return false;
618  }
619
620  if (LocVT == MVT::v2i64 ||
621      LocVT == MVT::v4i32 ||
622      LocVT == MVT::v8i16 ||
623      LocVT == MVT::v16i8 ||
624      LocVT == MVT::v4f32 ||
625      LocVT == MVT::v2f64 ||
626      LocVT == MVT::v8f16) {
627    unsigned Offset3 = State.AllocateStack(16, 16);
628    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo));
629    return false;
630  }
631
632  return true;  // CC didn't match.
633}
634
635
636static bool CC_AArch64_GHC(unsigned ValNo, MVT ValVT,
637                           MVT LocVT, CCValAssign::LocInfo LocInfo,
638                           ISD::ArgFlagsTy ArgFlags, CCState &State) {
639
640  if (LocVT == MVT::iPTR) {
641    LocVT = MVT::i64;
642    LocInfo = CCValAssign::BCvt;
643  }
644
645  if (LocVT == MVT::v1i64 ||
646      LocVT == MVT::v2i32 ||
647      LocVT == MVT::v4i16 ||
648      LocVT == MVT::v8i8 ||
649      LocVT == MVT::v2f32) {
650    LocVT = MVT::f64;
651    LocInfo = CCValAssign::BCvt;
652  }
653
654  if (LocVT == MVT::v2i64 ||
655      LocVT == MVT::v4i32 ||
656      LocVT == MVT::v8i16 ||
657      LocVT == MVT::v16i8 ||
658      LocVT == MVT::v4f32 ||
659      LocVT == MVT::f128) {
660    LocVT = MVT::v2f64;
661    LocInfo = CCValAssign::BCvt;
662  }
663
664  if (LocVT == MVT::v2f64) {
665    static const MCPhysReg RegList1[] = {
666      AArch64::Q4, AArch64::Q5
667    };
668    if (unsigned Reg = State.AllocateReg(RegList1)) {
669      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
670      return false;
671    }
672  }
673
674  if (LocVT == MVT::f32) {
675    static const MCPhysReg RegList2[] = {
676      AArch64::S8, AArch64::S9, AArch64::S10, AArch64::S11
677    };
678    if (unsigned Reg = State.AllocateReg(RegList2)) {
679      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
680      return false;
681    }
682  }
683
684  if (LocVT == MVT::f64) {
685    static const MCPhysReg RegList3[] = {
686      AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15
687    };
688    if (unsigned Reg = State.AllocateReg(RegList3)) {
689      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
690      return false;
691    }
692  }
693
694  if (LocVT == MVT::i8 ||
695      LocVT == MVT::i16 ||
696      LocVT == MVT::i32) {
697    LocVT = MVT::i64;
698    if (ArgFlags.isSExt())
699        LocInfo = CCValAssign::SExt;
700    else if (ArgFlags.isZExt())
701        LocInfo = CCValAssign::ZExt;
702    else
703        LocInfo = CCValAssign::AExt;
704  }
705
706  if (LocVT == MVT::i64) {
707    static const MCPhysReg RegList4[] = {
708      AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28
709    };
710    if (unsigned Reg = State.AllocateReg(RegList4)) {
711      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
712      return false;
713    }
714  }
715
716  return true;  // CC didn't match.
717}
718
719
720static bool CC_AArch64_WebKit_JS(unsigned ValNo, MVT ValVT,
721                                 MVT LocVT, CCValAssign::LocInfo LocInfo,
722                                 ISD::ArgFlagsTy ArgFlags, CCState &State) {
723
724  if (LocVT == MVT::i1 ||
725      LocVT == MVT::i8 ||
726      LocVT == MVT::i16) {
727    LocVT = MVT::i32;
728    if (ArgFlags.isSExt())
729        LocInfo = CCValAssign::SExt;
730    else if (ArgFlags.isZExt())
731        LocInfo = CCValAssign::ZExt;
732    else
733        LocInfo = CCValAssign::AExt;
734  }
735
736  if (LocVT == MVT::i32) {
737    if (unsigned Reg = State.AllocateReg(AArch64::W0, AArch64::X0)) {
738      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
739      return false;
740    }
741  }
742
743  if (LocVT == MVT::i64) {
744    if (unsigned Reg = State.AllocateReg(AArch64::X0, AArch64::W0)) {
745      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
746      return false;
747    }
748  }
749
750  if (LocVT == MVT::i32 ||
751      LocVT == MVT::f32) {
752    unsigned Offset1 = State.AllocateStack(4, 4);
753    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo));
754    return false;
755  }
756
757  if (LocVT == MVT::i64 ||
758      LocVT == MVT::f64) {
759    unsigned Offset2 = State.AllocateStack(8, 8);
760    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
761    return false;
762  }
763
764  return true;  // CC didn't match.
765}
766
767
768static bool CC_AArch64_Win64_VarArg(unsigned ValNo, MVT ValVT,
769                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
770                                    ISD::ArgFlagsTy ArgFlags, CCState &State) {
771
772  if (LocVT == MVT::f16 ||
773      LocVT == MVT::f32) {
774    LocVT = MVT::f64;
775    LocInfo = CCValAssign::FPExt;
776  }
777
778  if (LocVT == MVT::f64) {
779    LocVT = MVT::i64;
780    LocInfo = CCValAssign::BCvt;
781  }
782
783  if (!CC_AArch64_AAPCS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
784    return false;
785
786  return true;  // CC didn't match.
787}
788
789
790static bool RetCC_AArch64_AAPCS(unsigned ValNo, MVT ValVT,
791                                MVT LocVT, CCValAssign::LocInfo LocInfo,
792                                ISD::ArgFlagsTy ArgFlags, CCState &State) {
793
794  if (LocVT == MVT::iPTR) {
795    LocVT = MVT::i64;
796    LocInfo = CCValAssign::BCvt;
797  }
798
799  if (LocVT == MVT::v2f32) {
800    LocVT = MVT::v2i32;
801    LocInfo = CCValAssign::BCvt;
802  }
803
804  if (LocVT == MVT::v2f64 ||
805      LocVT == MVT::v4f32) {
806    LocVT = MVT::v2i64;
807    LocInfo = CCValAssign::BCvt;
808  }
809
810  if (ArgFlags.isSwiftError()) {
811    if (LocVT == MVT::i64) {
812      if (unsigned Reg = State.AllocateReg(AArch64::X21, AArch64::W21)) {
813        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
814        return false;
815      }
816    }
817  }
818
819  if (State.getMachineFunction().getDataLayout().isBigEndian()) {
820    if (LocVT == MVT::v2i32 ||
821        LocVT == MVT::v2f32 ||
822        LocVT == MVT::v4i16 ||
823        LocVT == MVT::v4f16 ||
824        LocVT == MVT::v8i8) {
825      LocVT = MVT::f64;
826      LocInfo = CCValAssign::BCvt;
827    }
828  }
829
830  if (State.getMachineFunction().getDataLayout().isBigEndian()) {
831    if (LocVT == MVT::v2i64 ||
832        LocVT == MVT::v2f64 ||
833        LocVT == MVT::v4i32 ||
834        LocVT == MVT::v4f32 ||
835        LocVT == MVT::v8i16 ||
836        LocVT == MVT::v8f16 ||
837        LocVT == MVT::v16i8) {
838      LocVT = MVT::f128;
839      LocInfo = CCValAssign::BCvt;
840    }
841  }
842
843  if (LocVT == MVT::i1 ||
844      LocVT == MVT::i8 ||
845      LocVT == MVT::i16) {
846    LocVT = MVT::i32;
847    if (ArgFlags.isSExt())
848        LocInfo = CCValAssign::SExt;
849    else if (ArgFlags.isZExt())
850        LocInfo = CCValAssign::ZExt;
851    else
852        LocInfo = CCValAssign::AExt;
853  }
854
855  if (LocVT == MVT::i32) {
856    static const MCPhysReg RegList1[] = {
857      AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7
858    };
859    static const MCPhysReg RegList2[] = {
860      AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
861    };
862    if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
863      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
864      return false;
865    }
866  }
867
868  if (LocVT == MVT::i64) {
869    static const MCPhysReg RegList3[] = {
870      AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
871    };
872    static const MCPhysReg RegList4[] = {
873      AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7
874    };
875    if (unsigned Reg = State.AllocateReg(RegList3, RegList4)) {
876      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
877      return false;
878    }
879  }
880
881  if (LocVT == MVT::f16) {
882    static const MCPhysReg RegList5[] = {
883      AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7
884    };
885    static const MCPhysReg RegList6[] = {
886      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
887    };
888    if (unsigned Reg = State.AllocateReg(RegList5, RegList6)) {
889      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
890      return false;
891    }
892  }
893
894  if (LocVT == MVT::f32) {
895    static const MCPhysReg RegList7[] = {
896      AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7
897    };
898    static const MCPhysReg RegList8[] = {
899      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
900    };
901    if (unsigned Reg = State.AllocateReg(RegList7, RegList8)) {
902      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
903      return false;
904    }
905  }
906
907  if (LocVT == MVT::f64) {
908    static const MCPhysReg RegList9[] = {
909      AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
910    };
911    static const MCPhysReg RegList10[] = {
912      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
913    };
914    if (unsigned Reg = State.AllocateReg(RegList9, RegList10)) {
915      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
916      return false;
917    }
918  }
919
920  if (LocVT == MVT::v1i64 ||
921      LocVT == MVT::v2i32 ||
922      LocVT == MVT::v4i16 ||
923      LocVT == MVT::v8i8 ||
924      LocVT == MVT::v1f64 ||
925      LocVT == MVT::v2f32 ||
926      LocVT == MVT::v4f16) {
927    static const MCPhysReg RegList11[] = {
928      AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
929    };
930    static const MCPhysReg RegList12[] = {
931      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
932    };
933    if (unsigned Reg = State.AllocateReg(RegList11, RegList12)) {
934      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
935      return false;
936    }
937  }
938
939  if (LocVT == MVT::f128 ||
940      LocVT == MVT::v2i64 ||
941      LocVT == MVT::v4i32 ||
942      LocVT == MVT::v8i16 ||
943      LocVT == MVT::v16i8 ||
944      LocVT == MVT::v4f32 ||
945      LocVT == MVT::v2f64 ||
946      LocVT == MVT::v8f16) {
947    static const MCPhysReg RegList13[] = {
948      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
949    };
950    if (unsigned Reg = State.AllocateReg(RegList13)) {
951      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
952      return false;
953    }
954  }
955
956  return true;  // CC didn't match.
957}
958
959
960static bool RetCC_AArch64_WebKit_JS(unsigned ValNo, MVT ValVT,
961                                    MVT LocVT, CCValAssign::LocInfo LocInfo,
962                                    ISD::ArgFlagsTy ArgFlags, CCState &State) {
963
964  if (LocVT == MVT::i32) {
965    static const MCPhysReg RegList1[] = {
966      AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7
967    };
968    static const MCPhysReg RegList2[] = {
969      AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
970    };
971    if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
972      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
973      return false;
974    }
975  }
976
977  if (LocVT == MVT::i64) {
978    static const MCPhysReg RegList3[] = {
979      AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
980    };
981    static const MCPhysReg RegList4[] = {
982      AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7
983    };
984    if (unsigned Reg = State.AllocateReg(RegList3, RegList4)) {
985      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
986      return false;
987    }
988  }
989
990  if (LocVT == MVT::f32) {
991    static const MCPhysReg RegList5[] = {
992      AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7
993    };
994    static const MCPhysReg RegList6[] = {
995      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
996    };
997    if (unsigned Reg = State.AllocateReg(RegList5, RegList6)) {
998      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
999      return false;
1000    }
1001  }
1002
1003  if (LocVT == MVT::f64) {
1004    static const MCPhysReg RegList7[] = {
1005      AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7
1006    };
1007    static const MCPhysReg RegList8[] = {
1008      AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
1009    };
1010    if (unsigned Reg = State.AllocateReg(RegList7, RegList8)) {
1011      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1012      return false;
1013    }
1014  }
1015
1016  return true;  // CC didn't match.
1017}
1018