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Searched refs:ADR (Results 1 – 25 of 95) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/
Dmacho-adrp-missing-reloc.s3 ; CHECK: error: ADR/ADRP relocations must be GOT relative
/external/llvm/lib/Target/AArch64/Disassembler/
DAArch64ExternalSymbolizer.cpp107 MI.getOpcode() == AArch64::ADR) { in tryAddingSymbolicOperand()
116 } else if (MI.getOpcode() == AArch64::ADR) { in tryAddingSymbolicOperand()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/Disassembler/
DAArch64ExternalSymbolizer.cpp107 MI.getOpcode() == AArch64::ADR) { in tryAddingSymbolicOperand()
116 } else if (MI.getOpcode() == AArch64::ADR) { in tryAddingSymbolicOperand()
/external/llvm/test/CodeGen/ARM/
Djump-table-islands-split.ll8 ; eliminate the entry calculation (ADD) and use the ADR as the base.
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Djump-table-islands-split.ll8 ; eliminate the entry calculation (ADD) and use the ADR as the base.
/external/vixl/src/aarch64/
Dinstructions-aarch64.cc302 VIXL_ASSERT(Mask(PCRelAddressingMask) == ADR); in GetImmPCOffsetTarget()
342 if ((Mask(PCRelAddressingMask) == ADR)) { in SetPCRelImmTarget()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Transforms/Scalar/
DLoopRerollPass.cpp892 const auto *ADR = dyn_cast<SCEVAddRecExpr>(SE->getSCEV(DRS.BaseInst)); in validateRootSet() local
893 if (!ADR) in validateRootSet()
896 const SCEV *StepSCEV = SE->getMinusSCEV(SE->getSCEV(DRS.Roots[0]), ADR); in validateRootSet()
898 if (ADR->getStepRecurrence(*SE) != SE->getMulExpr(StepSCEV, ScaleSCEV)) in validateRootSet()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64MacroFusion.cpp206 case AArch64::ADR: in isAddressLdStPair()
/external/llvm/lib/Transforms/Scalar/
DLoopRerollPass.cpp967 const auto *ADR = dyn_cast<SCEVAddRecExpr>(SE->getSCEV(V.BaseInst)); in findRoots() local
968 if (!ADR) in findRoots()
982 const SCEV *StepSCEV = SE->getMinusSCEV(SE->getSCEV(V.Roots[0]), ADR); in findRoots()
984 if (ADR->getStepRecurrence(*SE) != SE->getMulExpr(StepSCEV, ScaleSCEV)) { in findRoots()
/external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/
Dthumb1.txt55 # ADR
/external/llvm/test/MC/Disassembler/ARM/
Dthumb1.txt55 # ADR
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/
Dthumb1.txt55 # ADR
/external/tremolo/Tremolo/
Ddpen.s63 ADR r14,dpen_read_return
460 ADR r6,.Lcrc_lookup
DmdctARM.s1003 ADR r6, bitrev
1033 ADR r7, .Lsincos_lookup @ sincos_lookup0 +
1127 ADR r7, .Lsincos_lookup @ sincos_lookup0 +
/external/v8/src/arm64/
Dinstructions-arm64.h221 return Mask(PCRelAddressingMask) == ADR; in IsAdr()
/external/llvm/lib/Target/AArch64/MCTargetDesc/
DAArch64MCCodeEmitter.cpp229 MCFixupKind Kind = MI.getOpcode() == AArch64::ADR in getAdrLabelOpValue()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/
DSystemZInstrHFP.td135 def ADR : BinaryRR<"adr", 0x2A, null_frag, FP64, FP64>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/MCTargetDesc/
DAArch64MCCodeEmitter.cpp244 MCFixupKind Kind = MI.getOpcode() == AArch64::ADR in getAdrLabelOpValue()
/external/swiftshader/third_party/LLVM/test/MC/ARM/
Dbasic-thumb-instructions.s81 @ ADR
/external/llvm/test/MC/ARM/
Dbasic-thumb-instructions.s86 @ ADR
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/
Dbasic-thumb-instructions.s86 @ ADR
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMAsmPrinter.cpp1215 : ARM::ADR)); in EmitInstruction()
1229 : ARM::ADR)); in EmitInstruction()
/external/llvm/lib/Target/ARM/
DARMAsmPrinter.cpp1310 : ARM::ADR)) in EmitInstruction()
1326 : ARM::ADR)) in EmitInstruction()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMAsmPrinter.cpp1241 : ARM::ADR)) in EmitInstruction()
1257 : ARM::ADR)) in EmitInstruction()
/external/capstone/
DChangeLog273 CBNZ, ADR.

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