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Searched refs:ARM (Results 1 – 25 of 1676) sorted by relevance

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/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMBaseRegisterInfo.cpp59 : ARMGenRegisterInfo(ARM::LR), TII(tii), STI(sti), in ARMBaseRegisterInfo()
60 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11), in ARMBaseRegisterInfo()
61 BasePtr(ARM::R6) { in ARMBaseRegisterInfo()
74 ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8, in getCalleeSavedRegs()
75 ARM::R7, ARM::R6, ARM::R5, ARM::R4, in getCalleeSavedRegs()
77 ARM::D15, ARM::D14, ARM::D13, ARM::D12, in getCalleeSavedRegs()
78 ARM::D11, ARM::D10, ARM::D9, ARM::D8, in getCalleeSavedRegs()
85 ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, in getCalleeSavedRegs()
86 ARM::R11, ARM::R10, ARM::R8, in getCalleeSavedRegs()
88 ARM::D15, ARM::D14, ARM::D13, ARM::D12, in getCalleeSavedRegs()
[all …]
DARMExpandPseudoInsts.cpp125 { ARM::VLD1DUPq16Pseudo, ARM::VLD1DUPq16, true, false, SingleSpc, 2, 4},
126 { ARM::VLD1DUPq16Pseudo_UPD, ARM::VLD1DUPq16_UPD, true, true, SingleSpc, 2, 4},
127 { ARM::VLD1DUPq32Pseudo, ARM::VLD1DUPq32, true, false, SingleSpc, 2, 2},
128 { ARM::VLD1DUPq32Pseudo_UPD, ARM::VLD1DUPq32_UPD, true, true, SingleSpc, 2, 2},
129 { ARM::VLD1DUPq8Pseudo, ARM::VLD1DUPq8, true, false, SingleSpc, 2, 8},
130 { ARM::VLD1DUPq8Pseudo_UPD, ARM::VLD1DUPq8_UPD, true, true, SingleSpc, 2, 8},
132 { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, EvenDblSpc, 1, 4 },
133 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, EvenDblSpc, 1, 4 },
134 { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, EvenDblSpc, 1, 2 },
135 { ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, EvenDblSpc, 1, 2 },
[all …]
DARMBaseInstrInfo.cpp65 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
66 { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false },
67 { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false },
68 { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false },
69 { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false },
70 { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false },
71 { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false },
72 { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false },
75 { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false },
76 { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false },
[all …]
DThumb2SizeReduction.cpp59 { ARM::t2ADCrr, 0, ARM::tADC, 0, 0, 0, 1, 0,0, 0,0 },
60 { ARM::t2ADDri, ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 0,0, 0,1 },
61 { ARM::t2ADDrr, ARM::tADDrr, ARM::tADDhirr, 0, 0, 1, 0, 0,1, 0,0 },
62 { ARM::t2ADDSri,ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 2,2, 0,1 },
63 { ARM::t2ADDSrr,ARM::tADDrr, 0, 0, 0, 1, 0, 2,0, 0,1 },
64 { ARM::t2ANDrr, 0, ARM::tAND, 0, 0, 0, 1, 0,0, 1,0 },
65 { ARM::t2ASRri, ARM::tASRri, 0, 5, 0, 1, 0, 0,0, 1,0 },
66 { ARM::t2ASRrr, 0, ARM::tASRrr, 0, 0, 0, 1, 0,0, 1,0 },
67 { ARM::t2BICrr, 0, ARM::tBIC, 0, 0, 0, 1, 0,0, 1,0 },
70 { ARM::t2CMPri, ARM::tCMPi8, 0, 8, 0, 1, 0, 2,0, 0,0 },
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMExpandPseudoInsts.cpp153 { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, false, EvenDblSpc, 1, 4 ,true},
154 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, true, EvenDblSpc, 1, 4 ,true},
155 { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, false, EvenDblSpc, 1, 2 ,true},
156 { ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, true, EvenDblSpc, 1, 2 ,true},
157 { ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8, true, false, false, EvenDblSpc, 1, 8 ,true},
158 { ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD, true, true, true, EvenDblSpc, 1, 8 ,true},
160 { ARM::VLD1d16QPseudo, ARM::VLD1d16Q, true, false, false, SingleSpc, 4, 4 ,false},
161 { ARM::VLD1d16TPseudo, ARM::VLD1d16T, true, false, false, SingleSpc, 3, 4 ,false},
162 { ARM::VLD1d32QPseudo, ARM::VLD1d32Q, true, false, false, SingleSpc, 4, 2 ,false},
163 { ARM::VLD1d32TPseudo, ARM::VLD1d32T, true, false, false, SingleSpc, 3, 2 ,false},
[all …]
DARMFeatures.h29 case ARM::tADC: in isV8EligibleForIT()
30 case ARM::tADDi3: in isV8EligibleForIT()
31 case ARM::tADDi8: in isV8EligibleForIT()
32 case ARM::tADDrr: in isV8EligibleForIT()
33 case ARM::tAND: in isV8EligibleForIT()
34 case ARM::tASRri: in isV8EligibleForIT()
35 case ARM::tASRrr: in isV8EligibleForIT()
36 case ARM::tBIC: in isV8EligibleForIT()
37 case ARM::tEOR: in isV8EligibleForIT()
38 case ARM::tLSLri: in isV8EligibleForIT()
[all …]
DARMBaseInstrInfo.cpp90 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
91 { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false },
92 { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false },
93 { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false },
94 { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false },
95 { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false },
96 { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false },
97 { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false },
100 { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false },
101 { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false },
[all …]
DARMRegisterBankInfo.cpp31 namespace ARM { namespace
145 const RegisterBank &RBGPR = getRegBank(ARM::GPRRegBankID); in ARMRegisterBankInfo()
147 assert(&ARM::GPRRegBank == &RBGPR && "The order in RegBanks is messed up"); in ARMRegisterBankInfo()
150 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRRegClassID)) && in ARMRegisterBankInfo()
152 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRwithAPSRRegClassID)) && in ARMRegisterBankInfo()
154 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRnopcRegClassID)) && in ARMRegisterBankInfo()
156 assert(RBGPR.covers(*TRI.getRegClass(ARM::rGPRRegClassID)) && in ARMRegisterBankInfo()
158 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPRRegClassID)) && in ARMRegisterBankInfo()
160 assert(RBGPR.covers(*TRI.getRegClass(ARM::tcGPRRegClassID)) && in ARMRegisterBankInfo()
162 assert(RBGPR.covers(*TRI.getRegClass(ARM::tGPR_and_tcGPRRegClassID)) && in ARMRegisterBankInfo()
[all …]
DARMTargetTransformInfo.h58 ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureNEON, ARM::FeatureThumb2,
59 ARM::FeatureFP16, ARM::FeatureVFP4, ARM::FeatureFPARMv8,
60 ARM::FeatureFullFP16, ARM::FeatureHWDivThumb,
61 ARM::FeatureHWDivARM, ARM::FeatureDB, ARM::FeatureV7Clrex,
62 ARM::FeatureAcquireRelease, ARM::FeatureSlowFPBrcc,
63 ARM::FeaturePerfMon, ARM::FeatureTrustZone, ARM::Feature8MSecExt,
64 ARM::FeatureCrypto, ARM::FeatureCRC, ARM::FeatureRAS,
65 ARM::FeatureFPAO, ARM::FeatureFuseAES, ARM::FeatureZCZeroing,
66 ARM::FeatureProfUnpredicate, ARM::FeatureSlowVGETLNi32,
67 ARM::FeatureSlowVDUP32, ARM::FeaturePreferVMOVSR,
[all …]
DThumb2InstrInfo.cpp47 NopInst.setOpcode(ARM::tHINT); in getNoop()
89 if (MBBI->getOpcode() == ARM::t2IT) { in ReplaceTailWithBranchTo()
127 if (!ARM::GPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
130 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) in copyPhysReg()
149 if (RC == &ARM::GPRRegClass || RC == &ARM::tGPRRegClass || in storeRegToStackSlot()
150 RC == &ARM::tcGPRRegClass || RC == &ARM::rGPRRegClass || in storeRegToStackSlot()
151 RC == &ARM::GPRnopcRegClass) { in storeRegToStackSlot()
152 BuildMI(MBB, I, DL, get(ARM::t2STRi12)) in storeRegToStackSlot()
161 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
167 MRI->constrainRegClass(SrcReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass); in storeRegToStackSlot()
[all …]
/external/llvm/lib/Target/ARM/
DARMExpandPseudoInsts.cpp150 { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, false, EvenDblSpc, 1, 4 ,true},
151 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, true, EvenDblSpc, 1, 4 ,true},
152 { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, false, EvenDblSpc, 1, 2 ,true},
153 { ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, true, EvenDblSpc, 1, 2 ,true},
154 { ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8, true, false, false, EvenDblSpc, 1, 8 ,true},
155 { ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD, true, true, true, EvenDblSpc, 1, 8 ,true},
157 { ARM::VLD1d64QPseudo, ARM::VLD1d64Q, true, false, false, SingleSpc, 4, 1 ,false},
158 { ARM::VLD1d64QPseudoWB_fixed, ARM::VLD1d64Qwb_fixed, true, true, false, SingleSpc, 4, 1 ,fals…
159 { ARM::VLD1d64TPseudo, ARM::VLD1d64T, true, false, false, SingleSpc, 3, 1 ,false},
160 { ARM::VLD1d64TPseudoWB_fixed, ARM::VLD1d64Twb_fixed, true, true, false, SingleSpc, 3, 1 ,fals…
[all …]
DARMFeatures.h29 case ARM::tADC: in isV8EligibleForIT()
30 case ARM::tADDi3: in isV8EligibleForIT()
31 case ARM::tADDi8: in isV8EligibleForIT()
32 case ARM::tADDrr: in isV8EligibleForIT()
33 case ARM::tAND: in isV8EligibleForIT()
34 case ARM::tASRri: in isV8EligibleForIT()
35 case ARM::tASRrr: in isV8EligibleForIT()
36 case ARM::tBIC: in isV8EligibleForIT()
37 case ARM::tEOR: in isV8EligibleForIT()
38 case ARM::tLSLri: in isV8EligibleForIT()
[all …]
DARMBaseInstrInfo.cpp66 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
67 { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false },
68 { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false },
69 { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false },
70 { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false },
71 { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false },
72 { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false },
73 { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false },
76 { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false },
77 { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false },
[all …]
DThumb2SizeReduction.cpp64 { ARM::t2ADCrr, 0, ARM::tADC, 0, 0, 0, 1, 0,0, 0,0,0 },
65 { ARM::t2ADDri, ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 0,0, 0,1,0 },
66 { ARM::t2ADDrr, ARM::tADDrr, ARM::tADDhirr, 0, 0, 1, 0, 0,1, 0,0,0 },
67 { ARM::t2ADDSri,ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 2,2, 0,1,0 },
68 { ARM::t2ADDSrr,ARM::tADDrr, 0, 0, 0, 1, 0, 2,0, 0,1,0 },
69 { ARM::t2ANDrr, 0, ARM::tAND, 0, 0, 0, 1, 0,0, 1,0,0 },
70 { ARM::t2ASRri, ARM::tASRri, 0, 5, 0, 1, 0, 0,0, 1,0,1 },
71 { ARM::t2ASRrr, 0, ARM::tASRrr, 0, 0, 0, 1, 0,0, 1,0,1 },
72 { ARM::t2BICrr, 0, ARM::tBIC, 0, 0, 0, 1, 0,0, 1,0,0 },
75 { ARM::t2CMNzrr, ARM::tCMNz, 0, 0, 0, 1, 0, 2,0, 0,0,0 },
[all …]
DThumb2InstrInfo.cpp37 NopInst.setOpcode(ARM::tHINT); in getNoopForMachoTarget()
79 if (MBBI->getOpcode() == ARM::t2IT) { in ReplaceTailWithBranchTo()
117 if (!ARM::GPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
120 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) in copyPhysReg()
138 if (RC == &ARM::GPRRegClass || RC == &ARM::tGPRRegClass || in storeRegToStackSlot()
139 RC == &ARM::tcGPRRegClass || RC == &ARM::rGPRRegClass || in storeRegToStackSlot()
140 RC == &ARM::GPRnopcRegClass) { in storeRegToStackSlot()
141 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2STRi12)) in storeRegToStackSlot()
147 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
153 MRI->constrainRegClass(SrcReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass); in storeRegToStackSlot()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/unittests/Support/
DTargetParserTest.cpp36 ARM::ArchKind AK = ARM::parseCPUArch(CPUName); in testARMCPU()
37 bool pass = ARM::getArchName(AK).equals(ExpectedArch); in testARMCPU()
38 unsigned FPUKind = ARM::getDefaultFPU(CPUName, AK); in testARMCPU()
39 pass &= ARM::getFPUName(FPUKind).equals(ExpectedFPU); in testARMCPU()
41 unsigned ExtKind = ARM::getDefaultExtensions(CPUName, AK); in testARMCPU()
42 if (ExtKind > 1 && (ExtKind & ARM::AEK_NONE)) in testARMCPU()
43 pass &= ((ExtKind ^ ARM::AEK_NONE) == ExpectedFlags); in testARMCPU()
47 pass &= ARM::getCPUAttr(AK).equals(CPUAttr); in testARMCPU()
54 ARM::AEK_NONE, "")); in TEST()
56 ARM::AEK_NONE, "")); in TEST()
[all …]
/external/llvm/test/CodeGen/ARM/
Dsegmented-stacks.ll1 … < %s -mtriple=arm-linux-androideabi -verify-machineinstrs | FileCheck %s -check-prefix=ARM-android
2 … %s -mtriple=arm-linux-unknown-gnueabi -verify-machineinstrs | FileCheck %s -check-prefix=ARM-linux
17 ; ARM-linux: test_basic:
19 ; ARM-linux: push {r4, r5}
20 ; ARM-linux-NEXT: mrc p15, #0, r4, c13, c0, #3
21 ; ARM-linux-NEXT: mov r5, sp
22 ; ARM-linux-NEXT: ldr r4, [r4, #4]
23 ; ARM-linux-NEXT: cmp r4, r5
24 ; ARM-linux-NEXT: blo .LBB0_2
26 ; ARM-linux: mov r4, #48
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dsegmented-stacks.ll1 …le=arm-linux-androideabi -mattr=+v4t -verify-machineinstrs | FileCheck %s -check-prefix=ARM-android
2 …arm-linux-unknown-gnueabi -mattr=+v4t -verify-machineinstrs | FileCheck %s -check-prefix=ARM-linux
17 ; ARM-linux: test_basic:
19 ; ARM-linux: push {r4, r5}
20 ; ARM-linux-NEXT: mrc p15, #0, r4, c13, c0, #3
21 ; ARM-linux-NEXT: mov r5, sp
22 ; ARM-linux-NEXT: ldr r4, [r4, #4]
23 ; ARM-linux-NEXT: cmp r4, r5
24 ; ARM-linux-NEXT: blo .LBB0_2
26 ; ARM-linux: mov r4, #48
[all …]
Ddebug-frame-large-stack.ll1 …=asm -o - < %s -mtriple arm-arm-netbsd-eabi -disable-fp-elim| FileCheck %s --check-prefix=CHECK-ARM
2 …filetype=asm -o - < %s -mtriple arm-arm-netbsd-eabi | FileCheck %s --check-prefix=CHECK-ARM-FP-ELIM
9 ; CHECK-ARM-LABEL: test1:
10 ; CHECK-ARM: .cfi_startproc
11 ; CHECK-ARM: sub sp, sp, #256
12 ; CHECK-ARM: .cfi_endproc
14 ; CHECK-ARM-FP-ELIM-LABEL: test1:
15 ; CHECK-ARM-FP-ELIM: .cfi_startproc
16 ; CHECK-ARM-FP-ELIM: sub sp, sp, #256
17 ; CHECK-ARM-FP-ELIM: .cfi_endproc
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Support/
DARMTargetParser.def1 //===- ARMTargetParser.def - ARM target parsing defines ---------*- C++ -*-===//
10 // This file provides defines to build up the ARM target parser's logic.
48 ARMBuildAttrs::CPUArch::Pre_v4, FK_NONE, ARM::AEK_NONE)
50 FK_NONE, ARM::AEK_NONE)
52 FK_NONE, ARM::AEK_NONE)
54 FK_NONE, ARM::AEK_NONE)
56 FK_NONE, ARM::AEK_NONE)
58 FK_NONE, ARM::AEK_NONE)
60 FK_NONE, ARM::AEK_NONE)
62 FK_NONE, ARM::AEK_NONE)
[all …]
/external/llvm/unittests/Support/
DTargetParserTest.cpp47 {NAME, ARM::ARCH_FPU, ARCH_BASE_EXT, AArch64::ArchKind::ID, ARCH_ATTR},
51 ArchNames<ARM::ArchKind> kARMARCHNames[] = {
54 {NAME, ARM::ARCH_FPU, ARCH_BASE_EXT, ARM::ID, ARCH_ATTR},
67 {NAME, AArch64::ArchKind::ID, ARM::DEFAULT_FPU, DEFAULT_EXT},
71 CpuNames<ARM::ArchKind> kARMCPUNames[] = {
73 {NAME, ARM::ID, ARM::DEFAULT_FPU, DEFAULT_EXT},
97 for (ARM::ArchKind AK = static_cast<ARM::ArchKind>(0); in TEST()
98 AK <= ARM::ArchKind::AK_LAST; in TEST()
99 AK = static_cast<ARM::ArchKind>(static_cast<unsigned>(AK) + 1)) in TEST()
100 EXPECT_TRUE(AK == ARM::AK_LAST ? ARM::getArchName(AK).empty() in TEST()
[all …]
/external/llvm/include/llvm/Support/
DARMTargetParser.def1 //===- ARMTargetParser.def - ARM target parsing defines ---------*- C++ -*-===//
10 // This file provides defines to build up the ARM target parser's logic.
48 ARMBuildAttrs::CPUArch::Pre_v4, FK_NONE, ARM::AEK_NONE)
50 FK_NONE, ARM::AEK_NONE)
52 FK_NONE, ARM::AEK_NONE)
54 FK_NONE, ARM::AEK_NONE)
56 FK_NONE, ARM::AEK_NONE)
58 FK_NONE, ARM::AEK_NONE)
60 FK_NONE, ARM::AEK_NONE)
62 FK_NONE, ARM::AEK_NONE)
[all …]
/external/swiftshader/third_party/llvm-subzero/include/llvm/Support/
DARMTargetParser.def1 //===- ARMTargetParser.def - ARM target parsing defines ---------*- C++ -*-===//
10 // This file provides defines to build up the ARM target parser's logic.
48 ARMBuildAttrs::CPUArch::Pre_v4, FK_NONE, ARM::AEK_NONE)
50 FK_NONE, ARM::AEK_NONE)
52 FK_NONE, ARM::AEK_NONE)
54 FK_NONE, ARM::AEK_NONE)
56 FK_NONE, ARM::AEK_NONE)
58 FK_NONE, ARM::AEK_NONE)
60 FK_NONE, ARM::AEK_NONE)
62 FK_NONE, ARM::AEK_NONE)
[all …]
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/
DARMGenRegisterInfo.inc18 namespace ARM {
311 } // end namespace ARM
315 namespace ARM {
422 } // end namespace ARM
427 namespace ARM {
488 } // end namespace ARM
1432 { ARM::APSR },
1433 { ARM::APSR_NZCV },
1434 { ARM::CPSR },
1435 { ARM::FPEXC },
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Support/
DTargetParser.cpp22 using namespace ARM;
34 ARM::FPUKind ID;
35 ARM::FPUVersion FPUVersion;
36 ARM::NeonSupportLevel NeonSupport;
37 ARM::FPURestriction Restriction;
74 ArchNames<ARM::ArchKind> ARCHNames[] = {
77 sizeof(SUB_ARCH) - 1, ARCH_FPU, ARCH_BASE_EXT, ARM::ArchKind::ID, ARCH_ATTR},
137 CpuNames<ARM::ArchKind> CPUNames[] = {
139 { NAME, sizeof(NAME) - 1, ARM::ArchKind::ID, IS_DEFAULT, DEFAULT_EXT },
155 StringRef ARM::getFPUName(unsigned FPUKind) { in getFPUName()
[all …]

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