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Searched refs:ASR (Results 1 – 25 of 195) sorted by relevance

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/external/vixl/test/aarch32/
Dtest-assembler-cond-rd-operand-rn-shift-amount-1to32-a32.cc115 {{vc, r8, r11, ASR, 13}, false, al, "vc r8 r11 ASR 13", "vc_r8_r11_ASR_13"},
116 {{al, r9, r12, ASR, 1}, false, al, "al r9 r12 ASR 1", "al_r9_r12_ASR_1"},
117 {{vs, r10, r3, ASR, 31}, false, al, "vs r10 r3 ASR 31", "vs_r10_r3_ASR_31"},
118 {{pl, r2, r11, ASR, 14}, false, al, "pl r2 r11 ASR 14", "pl_r2_r11_ASR_14"},
125 {{vc, r6, r2, ASR, 9}, false, al, "vc r6 r2 ASR 9", "vc_r6_r2_ASR_9"},
126 {{al, r10, r10, ASR, 7}, false, al, "al r10 r10 ASR 7", "al_r10_r10_ASR_7"},
128 {{vs, r0, r6, ASR, 19}, false, al, "vs r0 r6 ASR 19", "vs_r0_r6_ASR_19"},
132 {{hi, r8, r1, ASR, 15}, false, al, "hi r8 r1 ASR 15", "hi_r8_r1_ASR_15"},
135 {{vs, r2, r2, ASR, 7}, false, al, "vs r2 r2 ASR 7", "vs_r2_r2_ASR_7"},
136 {{pl, r8, r8, ASR, 4}, false, al, "pl r8 r8 ASR 4", "pl_r8_r8_ASR_4"},
[all …]
Dtest-assembler-cond-rd-operand-rn-shift-amount-1to32-in-it-block-t32.cc101 {{eq, r7, r2, ASR, 14}, true, eq, "eq r7 r2 ASR 14", "eq_r7_r2_ASR_14"},
104 {{ge, r5, r0, ASR, 23}, true, ge, "ge r5 r0 ASR 23", "ge_r5_r0_ASR_23"},
108 {{pl, r6, r1, ASR, 12}, true, pl, "pl r6 r1 ASR 12", "pl_r6_r1_ASR_12"},
109 {{hi, r7, r1, ASR, 30}, true, hi, "hi r7 r1 ASR 30", "hi_r7_r1_ASR_30"},
110 {{mi, r7, r6, ASR, 20}, true, mi, "mi r7 r6 ASR 20", "mi_r7_r6_ASR_20"},
111 {{cc, r3, r6, ASR, 22}, true, cc, "cc r3 r6 ASR 22", "cc_r3_r6_ASR_22"},
112 {{vc, r2, r1, ASR, 29}, true, vc, "vc r2 r1 ASR 29", "vc_r2_r1_ASR_29"},
113 {{pl, r0, r1, ASR, 15}, true, pl, "pl r0 r1 ASR 15", "pl_r0_r1_ASR_15"},
115 {{pl, r6, r4, ASR, 6}, true, pl, "pl r6 r4 ASR 6", "pl_r6_r4_ASR_6"},
116 {{hi, r1, r3, ASR, 15}, true, hi, "hi r1 r3 ASR 15", "hi_r1_r3_ASR_15"},
[all …]
Dtest-assembler-cond-rd-operand-rn-shift-amount-1to32-t32.cc105 {{al, r0, r3, ASR, 30}, false, al, "al r0 r3 ASR 30", "al_r0_r3_ASR_30"},
106 {{al, r10, r5, ASR, 31}, false, al, "al r10 r5 ASR 31", "al_r10_r5_ASR_31"},
107 {{al, r12, r9, ASR, 16}, false, al, "al r12 r9 ASR 16", "al_r12_r9_ASR_16"},
108 {{al, r5, r3, ASR, 31}, false, al, "al r5 r3 ASR 31", "al_r5_r3_ASR_31"},
109 {{al, r10, r8, ASR, 10}, false, al, "al r10 r8 ASR 10", "al_r10_r8_ASR_10"},
111 {{al, r13, r12, ASR, 31},
116 {{al, r4, r0, ASR, 22}, false, al, "al r4 r0 ASR 22", "al_r4_r0_ASR_22"},
117 {{al, r3, r10, ASR, 23}, false, al, "al r3 r10 ASR 23", "al_r3_r10_ASR_23"},
125 {{al, r10, r7, ASR, 15}, false, al, "al r10 r7 ASR 15", "al_r10_r7_ASR_15"},
128 {{al, r14, r3, ASR, 31}, false, al, "al r14 r3 ASR 31", "al_r14_r3_ASR_31"},
[all …]
Dtest-assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc116 const TestData kTests[] = {{{al, r11, r13, r10, ASR, 9},
121 {{al, r7, r5, r2, ASR, 2},
156 {{al, r10, r12, r4, ASR, 2},
166 {{al, r12, r11, r4, ASR, 7},
171 {{al, r9, r4, r8, ASR, 27},
176 {{al, r2, r10, r11, ASR, 1},
181 {{al, r0, r2, r9, ASR, 24},
186 {{al, r11, r6, r14, ASR, 31},
191 {{al, r2, r14, r14, ASR, 18},
196 {{al, r5, r7, r1, ASR, 2},
[all …]
Dtest-assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc116 const TestData kTests[] = {{{eq, r13, r6, r7, ASR, 5},
121 {{mi, r8, r11, r8, ASR, 32},
126 {{hi, r2, r3, r10, ASR, 18},
136 {{cc, r8, r9, r2, ASR, 3},
146 {{pl, r8, r6, r1, ASR, 31},
166 {{pl, r13, r8, r1, ASR, 7},
176 {{pl, r13, r8, r11, ASR, 17},
201 {{lt, r10, r9, r7, ASR, 25},
211 {{vc, r1, r4, r13, ASR, 32},
221 {{pl, r2, r12, r7, ASR, 2},
[all …]
Dtest-assembler-cond-rd-memop-rs-shift-amount-1to32-a32.cc617 {{al, r0, r14, minus, r1, ASR, 1, Offset},
622 {{al, r0, r4, plus, r8, ASR, 4, Offset},
627 {{al, r0, r9, minus, r1, ASR, 26, Offset},
637 {{al, r0, r0, plus, r13, ASR, 13, Offset},
642 {{al, r0, r9, minus, r7, ASR, 23, Offset},
647 {{al, r0, r13, minus, r5, ASR, 25, Offset},
652 {{al, r0, r7, plus, r5, ASR, 14, Offset},
667 {{al, r0, r2, minus, r5, ASR, 19, Offset},
672 {{al, r0, r10, minus, r7, ASR, 18, Offset},
677 {{al, r0, r0, minus, r1, ASR, 10, Offset},
[all …]
Dtest-simulator-cond-rd-memop-rs-shift-amount-1to32-a32.cc333 {{al, r1, r0, plus, r5, ASR, 24, Offset},
343 {{al, r12, r10, plus, r0, ASR, 16, Offset},
348 {{al, r4, r10, plus, r9, ASR, 19, Offset},
363 {{al, r1, r4, plus, r9, ASR, 25, Offset},
378 {{al, r0, r10, plus, r14, ASR, 11, Offset},
393 {{al, r0, r12, plus, r9, ASR, 29, Offset},
403 {{al, r10, r7, plus, r3, ASR, 29, Offset},
408 {{al, r4, r14, plus, r1, ASR, 30, Offset},
433 {{al, r14, r11, plus, r6, ASR, 16, Offset},
448 {{al, r11, r2, plus, r9, ASR, 21, Offset},
[all …]
Dtest-assembler-negative-cond-rd-rn-operand-rm-shift-rs-a32.cc139 {{vc, r15, r7, r4, ASR, r9},
163 {{cc, r15, r7, r13, ASR, r1},
202 {{le, r0, r7, r15, ASR, r11},
205 {{ge, r14, r15, r8, ASR, r7},
214 {{ne, r3, r8, r15, ASR, r11},
217 {{gt, r1, r12, r9, ASR, r15},
220 {{le, r1, r15, r1, ASR, r13},
253 {{gt, r15, r7, r9, ASR, r13},
271 {{cs, r2, r1, r15, ASR, r1},
280 {{hi, r15, r3, r11, ASR, r1},
[all …]
Dtest-assembler-cond-rd-operand-rn-shift-rs-t32.cc98 {{al, r11, r2, ASR, r10},
103 {{al, r7, r8, ASR, r12}, false, al, "al r7 r8 ASR r12", "al_r7_r8_ASR_r12"},
104 {{al, r10, r8, ASR, r4}, false, al, "al r10 r8 ASR r4", "al_r10_r8_ASR_r4"},
110 {{al, r13, r4, ASR, r5}, false, al, "al r13 r4 ASR r5", "al_r13_r4_ASR_r5"},
112 {{al, r6, r11, ASR, r8}, false, al, "al r6 r11 ASR r8", "al_r6_r11_ASR_r8"},
113 {{al, r8, r4, ASR, r4}, false, al, "al r8 r4 ASR r4", "al_r8_r4_ASR_r4"},
114 {{al, r10, r6, ASR, r7}, false, al, "al r10 r6 ASR r7", "al_r10_r6_ASR_r7"},
115 {{al, r0, r2, ASR, r14}, false, al, "al r0 r2 ASR r14", "al_r0_r2_ASR_r14"},
122 {{al, r9, r10, ASR, r9}, false, al, "al r9 r10 ASR r9", "al_r9_r10_ASR_r9"},
123 {{al, r5, r8, ASR, r4}, false, al, "al r5 r8 ASR r4", "al_r5_r8_ASR_r4"},
[all …]
Dtest-assembler-cond-rd-operand-rn-shift-rs-in-it-block-t32.cc103 {{le, r6, r6, ASR, r6}, true, le, "le r6 r6 ASR r6", "le_r6_r6_ASR_r6"},
105 {{le, r3, r3, ASR, r6}, true, le, "le r3 r3 ASR r6", "le_r3_r3_ASR_r6"},
107 {{pl, r3, r3, ASR, r2}, true, pl, "pl r3 r3 ASR r2", "pl_r3_r3_ASR_r2"},
110 {{cs, r0, r0, ASR, r6}, true, cs, "cs r0 r0 ASR r6", "cs_r0_r0_ASR_r6"},
114 {{pl, r2, r2, ASR, r7}, true, pl, "pl r2 r2 ASR r7", "pl_r2_r2_ASR_r7"},
118 {{ge, r4, r4, ASR, r1}, true, ge, "ge r4 r4 ASR r1", "ge_r4_r4_ASR_r1"},
120 {{ls, r0, r0, ASR, r2}, true, ls, "ls r0 r0 ASR r2", "ls_r0_r0_ASR_r2"},
123 {{cs, r7, r7, ASR, r3}, true, cs, "cs r7 r7 ASR r3", "cs_r7_r7_ASR_r3"},
125 {{hi, r1, r1, ASR, r6}, true, hi, "hi r1 r1 ASR r6", "hi_r1_r1_ASR_r6"},
132 {{ge, r1, r1, ASR, r7}, true, ge, "ge r1 r1 ASR r7", "ge_r1_r1_ASR_r7"},
[all …]
Dtest-assembler-cond-rd-operand-rn-shift-rs-a32.cc115 {{hi, r9, r8, ASR, r10}, false, al, "hi r9 r8 ASR r10", "hi_r9_r8_ASR_r10"},
118 {{vc, r4, r6, ASR, r11}, false, al, "vc r4 r6 ASR r11", "vc_r4_r6_ASR_r11"},
150 {{lt, r7, r12, ASR, r7}, false, al, "lt r7 r12 ASR r7", "lt_r7_r12_ASR_r7"},
157 {{lt, r5, r0, ASR, r2}, false, al, "lt r5 r0 ASR r2", "lt_r5_r0_ASR_r2"},
166 {{le, r7, r1, ASR, r0}, false, al, "le r7 r1 ASR r0", "le_r7_r1_ASR_r0"},
172 {{vc, r14, r1, ASR, r9}, false, al, "vc r14 r1 ASR r9", "vc_r14_r1_ASR_r9"},
175 {{pl, r7, r7, ASR, r9}, false, al, "pl r7 r7 ASR r9", "pl_r7_r7_ASR_r9"},
178 {{cc, r13, r1, ASR, r6}, false, al, "cc r13 r1 ASR r6", "cc_r13_r1_ASR_r6"},
179 {{cs, r12, r3, ASR, r12},
198 {{cc, r12, r10, ASR, r4},
[all …]
Dtest-assembler-cond-rd-rn-operand-rm-shift-rs-a32.cc161 {{lt, r9, r0, r9, ASR, r12},
181 {{al, r5, r8, r9, ASR, r14},
186 {{hi, r1, r2, r7, ASR, r13},
196 {{vc, r3, r6, r4, ASR, r4},
221 {{ge, r12, r13, r6, ASR, r12},
231 {{ls, r13, r14, r14, ASR, r13},
241 {{lt, r8, r8, r9, ASR, r0},
261 {{ls, r6, r11, r4, ASR, r11},
276 {{ls, r8, r7, r4, ASR, r3},
286 {{eq, r12, r7, r11, ASR, r3},
[all …]
Dtest-assembler-cond-rd-operand-rn-shift-rs-narrow-out-it-block-t32.cc112 {{al, r0, r0, ASR, r0}, false, al, "al r0 r0 ASR r0", "al_r0_r0_ASR_r0"},
113 {{al, r0, r0, ASR, r1}, false, al, "al r0 r0 ASR r1", "al_r0_r0_ASR_r1"},
114 {{al, r0, r0, ASR, r2}, false, al, "al r0 r0 ASR r2", "al_r0_r0_ASR_r2"},
115 {{al, r0, r0, ASR, r3}, false, al, "al r0 r0 ASR r3", "al_r0_r0_ASR_r3"},
116 {{al, r0, r0, ASR, r4}, false, al, "al r0 r0 ASR r4", "al_r0_r0_ASR_r4"},
117 {{al, r0, r0, ASR, r5}, false, al, "al r0 r0 ASR r5", "al_r0_r0_ASR_r5"},
118 {{al, r0, r0, ASR, r6}, false, al, "al r0 r0 ASR r6", "al_r0_r0_ASR_r6"},
119 {{al, r0, r0, ASR, r7}, false, al, "al r0 r0 ASR r7", "al_r0_r0_ASR_r7"},
144 {{al, r1, r1, ASR, r0}, false, al, "al r1 r1 ASR r0", "al_r1_r1_ASR_r0"},
145 {{al, r1, r1, ASR, r1}, false, al, "al r1 r1 ASR r1", "al_r1_r1_ASR_r1"},
[all …]
Dtest-simulator-cond-rd-operand-rn-shift-amount-1to32-a32.cc678 {{al, r0, r0, ASR, 1},
683 {{al, r0, r0, ASR, 2},
688 {{al, r0, r0, ASR, 3},
693 {{al, r0, r0, ASR, 4},
698 {{al, r0, r0, ASR, 5},
703 {{al, r0, r0, ASR, 6},
708 {{al, r0, r0, ASR, 7},
713 {{al, r0, r0, ASR, 8},
718 {{al, r0, r0, ASR, 9},
723 {{al, r0, r0, ASR, 10},
[all …]
Dtest-simulator-cond-rd-operand-rn-shift-amount-1to32-t32.cc678 {{al, r0, r1, ASR, 1},
683 {{al, r0, r1, ASR, 2},
688 {{al, r0, r1, ASR, 3},
693 {{al, r0, r1, ASR, 4},
698 {{al, r0, r1, ASR, 5},
703 {{al, r0, r1, ASR, 6},
708 {{al, r0, r1, ASR, 7},
713 {{al, r0, r1, ASR, 8},
718 {{al, r0, r1, ASR, 9},
723 {{al, r0, r1, ASR, 10},
[all …]
/external/libxaac/decoder/armv7/
Dixheaacd_autocorr_st2.s46 MOV r4, r4, ASR #3
47 MOV r5, r5, ASR #3
48 MOV r6, r6, ASR #3
49 MOV r7, r7, ASR #3
85 MOV r6, r6, ASR #3
86 MOV r7, r7, ASR #3
99 MOV r4, r4, ASR #3
100 MOV r5, r5, ASR #3
121 MOV r6, r6, ASR #3
122 MOV r7, r7, ASR #3
[all …]
Dixheaacd_auto_corr.s43 MOV r4, r4, ASR #3
44 MOV r3, r3, ASR #3
45 MOV r6, r6, ASR #3
46 MOV r5, r5, ASR #3
70 MOV r4, r4, ASR #3
75 MOV r6, r10, ASR #3
83 MOV r5, r5, ASR #3
92 MOV r4, r4, ASR #3
98 MOV r6, r6, ASR #3
108 EOR r5, r7, r7, ASR #31
[all …]
Dixheaacd_shiftrountine_with_round.s57 MOVS r10, r4, ASR #0x15
64 MOVS r10, r5, ASR #0x15
67 MOV r4, r4, ASR #16
74 MOVS r10, r6, ASR #0x15
77 MOV r5, r5, ASR #16
84 MOVS r10, r7, ASR #0x15
87 MOV r6, r6, ASR #16
95 MOV r7, r7, ASR #16
Dixheaacd_shiftrountine.s43 MOV r12, r12, ASR r3
44 MOV r4, r4, ASR r3
50 MOV r12, r12, ASR r3
51 MOV r4, r4, ASR r3
69 MOVS r7, r12, ASR r2
75 MOVS r7, r5, ASR r2
86 MOVS r7, r12, ASR r2
92 MOVS r7, r5, ASR r2
Dixheaacd_conv_ergtoamplitudelp.s47 MOV R6, R6, ASR #5
54 MOV R14, R7, ASR #1
73 MOV R6, R6, ASR #5
80 MOV R9, R7, ASR #1
101 MOV R6, R6, ASR #5
108 MOV R9, R7, ASR #1
118 MOVGT R8, R8, ASR R6
139 MOV R12, R12, ASR R6
Dixheaacd_shiftrountine_with_rnd_eld.s43 …MOVS r10, r4, ASR #0x16 @Right shift by 22 to check the overflow ( is not AAC_ELD righ…
50 MOVS r10, r5, ASR #0x16
53 MOV r4, r4, ASR #16
60 MOVS r10, r6, ASR #0x16
63 MOV r5, r5, ASR #16
70 MOVS r10, r7, ASR #0x16
73 MOV r6, r6, ASR #16
81 MOV r7, r7, ASR #16
Dixheaacd_conv_ergtoamplitude.s47 MOV R11, R11, ASR #5
58 MOV R9, R7, ASR #1
74 MOV R11, R11, ASR #5
85 MOV R9, R7, ASR #1
102 MOV R11, R11, ASR #5
113 MOV R9, R7, ASR #1
121 MOVGT R8, R8, ASR R6
/external/libxaac/decoder/armv8/
Dixheaacd_apply_scale_factors.s73 SUBS x6, x11, x5, ASR #2 // 37-(scale_factor >> 2)
95 ASR x6, x6, #16
96 ASR x7, x7 , #16
97 ASR x19, x19 , #16
98 ASR x20, x20 , #16
100 ASR x6, x6, x14 // buffex1 = shx32(buffex1, shift);
101 ASR x7, x7, x14
102 ASR x19, x19, x14
103 ASR x20, x20, x14
125 ASR x6, x6, #16
[all …]
Dixheaacd_fft32x32_ld2_armv8.s296 ASR x4, x4, #16
300 ASR x20, x20, #16
305 ASR x5, x5, #16
315 ASR x20, x20, #16
322 ASR x6, x6, #16
328 ASR x7, x7, #16
337 ASR x8, x8, #16
341 ASR x20, x20, #16
346 ASR x9, x9, #16
350 ASR x20, x20, #16
[all …]
/external/tremolo/Tremolo/
DmdctLARM.s63 MOV r5, r5, ASR #9 @ r5 = (*--r)>>9
64 MOV r6, r6, ASR #9 @ r6 = (*--r)>>9
65 MOV r7, r7, ASR #9 @ r7 = (*--r)>>9
66 MOV r12,r12,ASR #9 @ r12= (*--r)>>9
68 MOV r14,r12,ASR #15
69 TEQ r14,r14,ASR #31 @ if r14==0 || r14==-1 then in range
70 EORNE r12,r4, r14,ASR #31
73 MOV r14,r7, ASR #15
74 TEQ r14,r14,ASR #31 @ if r14==0 || r14==-1 then in range
75 EORNE r7, r4, r14,ASR #31
[all …]

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