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1 // Copyright 2016, VIXL authors
2 // All rights reserved.
3 //
4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions are met:
6 //
7 //   * Redistributions of source code must retain the above copyright notice,
8 //     this list of conditions and the following disclaimer.
9 //   * Redistributions in binary form must reproduce the above copyright notice,
10 //     this list of conditions and the following disclaimer in the documentation
11 //     and/or other materials provided with the distribution.
12 //   * Neither the name of ARM Limited nor the names of its contributors may be
13 //     used to endorse or promote products derived from this software without
14 //     specific prior written permission.
15 //
16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
17 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
18 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
19 // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
20 // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
23 // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 
27 
28 // -----------------------------------------------------------------------------
29 // This file is auto generated from the
30 // test/aarch32/config/template-assembler-aarch32.cc.in template file using
31 // tools/generate_tests.py.
32 //
33 // PLEASE DO NOT EDIT.
34 // -----------------------------------------------------------------------------
35 
36 
37 #include "test-runner.h"
38 
39 #include "test-utils.h"
40 #include "test-utils-aarch32.h"
41 
42 #include "aarch32/assembler-aarch32.h"
43 #include "aarch32/macro-assembler-aarch32.h"
44 
45 #define BUF_SIZE (4096)
46 
47 namespace vixl {
48 namespace aarch32 {
49 
50 // List of instruction mnemonics.
51 #define FOREACH_INSTRUCTION(M) \
52   M(ldr)                       \
53   M(ldrb)                      \
54   M(str)                       \
55   M(strb)
56 
57 
58 // The following definitions are defined again in each generated test, therefore
59 // we need to place them in an anomymous namespace. It expresses that they are
60 // local to this file only, and the compiler is not allowed to share these types
61 // across test files during template instantiation. Specifically, `Operands` has
62 // various layouts across generated tests so it absolutely cannot be shared.
63 
64 #ifdef VIXL_INCLUDE_TARGET_A32
65 namespace {
66 
67 // Values to be passed to the assembler to produce the instruction under test.
68 struct Operands {
69   Condition cond;
70   Register rd;
71   Register rn;
72   Sign sign;
73   Register rm;
74   ShiftType shift;
75   uint32_t amount;
76   AddrMode addr_mode;
77 };
78 
79 // This structure contains all data needed to test one specific
80 // instruction.
81 struct TestData {
82   // The `operands` field represents what to pass to the assembler to
83   // produce the instruction.
84   Operands operands;
85   // True if we need to generate an IT instruction for this test to be valid.
86   bool in_it_block;
87   // The condition to give the IT instruction, this will be set to "al" by
88   // default.
89   Condition it_condition;
90   // Description of the operands, used for error reporting.
91   const char* operands_description;
92   // Unique identifier, used for generating traces.
93   const char* identifier;
94 };
95 
96 struct TestResult {
97   size_t size;
98   const byte* encoding;
99 };
100 
101 // Each element of this array produce one instruction encoding.
102 const TestData kTests[] = {{{pl, r8, r11, plus, r6, LSR, 1, Offset},
103                             false,
104                             al,
105                             "pl r8 r11 plus r6 LSR 1 Offset",
106                             "pl_r8_r11_plus_r6_LSR_1_Offset"},
107                            {{le, r4, r8, plus, r5, LSR, 1, Offset},
108                             false,
109                             al,
110                             "le r4 r8 plus r5 LSR 1 Offset",
111                             "le_r4_r8_plus_r5_LSR_1_Offset"},
112                            {{vs, r2, r6, plus, r14, LSR, 1, Offset},
113                             false,
114                             al,
115                             "vs r2 r6 plus r14 LSR 1 Offset",
116                             "vs_r2_r6_plus_r14_LSR_1_Offset"},
117                            {{ls, r1, r7, plus, r8, LSR, 1, Offset},
118                             false,
119                             al,
120                             "ls r1 r7 plus r8 LSR 1 Offset",
121                             "ls_r1_r7_plus_r8_LSR_1_Offset"},
122                            {{ge, r14, r6, plus, r14, LSR, 1, Offset},
123                             false,
124                             al,
125                             "ge r14 r6 plus r14 LSR 1 Offset",
126                             "ge_r14_r6_plus_r14_LSR_1_Offset"},
127                            {{cs, r7, r0, plus, r7, LSR, 1, Offset},
128                             false,
129                             al,
130                             "cs r7 r0 plus r7 LSR 1 Offset",
131                             "cs_r7_r0_plus_r7_LSR_1_Offset"},
132                            {{ge, r11, r0, plus, r9, LSR, 1, Offset},
133                             false,
134                             al,
135                             "ge r11 r0 plus r9 LSR 1 Offset",
136                             "ge_r11_r0_plus_r9_LSR_1_Offset"},
137                            {{eq, r7, r10, plus, r4, LSR, 1, Offset},
138                             false,
139                             al,
140                             "eq r7 r10 plus r4 LSR 1 Offset",
141                             "eq_r7_r10_plus_r4_LSR_1_Offset"},
142                            {{al, r9, r2, plus, r3, LSR, 1, Offset},
143                             false,
144                             al,
145                             "al r9 r2 plus r3 LSR 1 Offset",
146                             "al_r9_r2_plus_r3_LSR_1_Offset"},
147                            {{cc, r11, r10, plus, r6, LSR, 1, Offset},
148                             false,
149                             al,
150                             "cc r11 r10 plus r6 LSR 1 Offset",
151                             "cc_r11_r10_plus_r6_LSR_1_Offset"},
152                            {{lt, r9, r6, plus, r1, LSR, 1, Offset},
153                             false,
154                             al,
155                             "lt r9 r6 plus r1 LSR 1 Offset",
156                             "lt_r9_r6_plus_r1_LSR_1_Offset"},
157                            {{ge, r4, r0, plus, r4, LSR, 1, Offset},
158                             false,
159                             al,
160                             "ge r4 r0 plus r4 LSR 1 Offset",
161                             "ge_r4_r0_plus_r4_LSR_1_Offset"},
162                            {{al, r9, r13, plus, r14, LSR, 1, Offset},
163                             false,
164                             al,
165                             "al r9 r13 plus r14 LSR 1 Offset",
166                             "al_r9_r13_plus_r14_LSR_1_Offset"},
167                            {{cc, r9, r0, plus, r7, LSR, 1, Offset},
168                             false,
169                             al,
170                             "cc r9 r0 plus r7 LSR 1 Offset",
171                             "cc_r9_r0_plus_r7_LSR_1_Offset"},
172                            {{cs, r11, r7, plus, r8, LSR, 1, Offset},
173                             false,
174                             al,
175                             "cs r11 r7 plus r8 LSR 1 Offset",
176                             "cs_r11_r7_plus_r8_LSR_1_Offset"},
177                            {{eq, r8, r0, plus, r8, LSR, 1, Offset},
178                             false,
179                             al,
180                             "eq r8 r0 plus r8 LSR 1 Offset",
181                             "eq_r8_r0_plus_r8_LSR_1_Offset"},
182                            {{hi, r9, r10, plus, r8, LSR, 1, Offset},
183                             false,
184                             al,
185                             "hi r9 r10 plus r8 LSR 1 Offset",
186                             "hi_r9_r10_plus_r8_LSR_1_Offset"},
187                            {{le, r8, r0, plus, r0, LSR, 1, Offset},
188                             false,
189                             al,
190                             "le r8 r0 plus r0 LSR 1 Offset",
191                             "le_r8_r0_plus_r0_LSR_1_Offset"},
192                            {{cs, r4, r5, plus, r2, LSR, 1, Offset},
193                             false,
194                             al,
195                             "cs r4 r5 plus r2 LSR 1 Offset",
196                             "cs_r4_r5_plus_r2_LSR_1_Offset"},
197                            {{eq, r14, r11, plus, r8, LSR, 1, Offset},
198                             false,
199                             al,
200                             "eq r14 r11 plus r8 LSR 1 Offset",
201                             "eq_r14_r11_plus_r8_LSR_1_Offset"},
202                            {{cs, r7, r6, plus, r14, LSR, 1, Offset},
203                             false,
204                             al,
205                             "cs r7 r6 plus r14 LSR 1 Offset",
206                             "cs_r7_r6_plus_r14_LSR_1_Offset"},
207                            {{ne, r0, r9, plus, r7, LSR, 1, Offset},
208                             false,
209                             al,
210                             "ne r0 r9 plus r7 LSR 1 Offset",
211                             "ne_r0_r9_plus_r7_LSR_1_Offset"},
212                            {{le, r7, r3, plus, r11, LSR, 1, Offset},
213                             false,
214                             al,
215                             "le r7 r3 plus r11 LSR 1 Offset",
216                             "le_r7_r3_plus_r11_LSR_1_Offset"},
217                            {{gt, r7, r9, plus, r9, LSR, 1, Offset},
218                             false,
219                             al,
220                             "gt r7 r9 plus r9 LSR 1 Offset",
221                             "gt_r7_r9_plus_r9_LSR_1_Offset"},
222                            {{le, r9, r12, plus, r9, LSR, 1, Offset},
223                             false,
224                             al,
225                             "le r9 r12 plus r9 LSR 1 Offset",
226                             "le_r9_r12_plus_r9_LSR_1_Offset"},
227                            {{pl, r2, r11, plus, r14, LSR, 1, Offset},
228                             false,
229                             al,
230                             "pl r2 r11 plus r14 LSR 1 Offset",
231                             "pl_r2_r11_plus_r14_LSR_1_Offset"},
232                            {{cs, r1, r7, plus, r2, LSR, 1, Offset},
233                             false,
234                             al,
235                             "cs r1 r7 plus r2 LSR 1 Offset",
236                             "cs_r1_r7_plus_r2_LSR_1_Offset"},
237                            {{al, r5, r1, plus, r12, LSR, 1, Offset},
238                             false,
239                             al,
240                             "al r5 r1 plus r12 LSR 1 Offset",
241                             "al_r5_r1_plus_r12_LSR_1_Offset"},
242                            {{eq, r10, r13, plus, r12, LSR, 1, Offset},
243                             false,
244                             al,
245                             "eq r10 r13 plus r12 LSR 1 Offset",
246                             "eq_r10_r13_plus_r12_LSR_1_Offset"},
247                            {{eq, r10, r11, plus, r3, LSR, 1, Offset},
248                             false,
249                             al,
250                             "eq r10 r11 plus r3 LSR 1 Offset",
251                             "eq_r10_r11_plus_r3_LSR_1_Offset"},
252                            {{al, r9, r12, plus, r0, LSR, 1, Offset},
253                             false,
254                             al,
255                             "al r9 r12 plus r0 LSR 1 Offset",
256                             "al_r9_r12_plus_r0_LSR_1_Offset"},
257                            {{ls, r3, r14, plus, r1, LSR, 1, Offset},
258                             false,
259                             al,
260                             "ls r3 r14 plus r1 LSR 1 Offset",
261                             "ls_r3_r14_plus_r1_LSR_1_Offset"},
262                            {{le, r13, r4, plus, r9, LSR, 1, Offset},
263                             false,
264                             al,
265                             "le r13 r4 plus r9 LSR 1 Offset",
266                             "le_r13_r4_plus_r9_LSR_1_Offset"},
267                            {{ls, r3, r14, plus, r3, LSR, 1, Offset},
268                             false,
269                             al,
270                             "ls r3 r14 plus r3 LSR 1 Offset",
271                             "ls_r3_r14_plus_r3_LSR_1_Offset"},
272                            {{cc, r7, r4, plus, r4, LSR, 1, Offset},
273                             false,
274                             al,
275                             "cc r7 r4 plus r4 LSR 1 Offset",
276                             "cc_r7_r4_plus_r4_LSR_1_Offset"},
277                            {{ls, r5, r9, plus, r5, LSR, 1, Offset},
278                             false,
279                             al,
280                             "ls r5 r9 plus r5 LSR 1 Offset",
281                             "ls_r5_r9_plus_r5_LSR_1_Offset"},
282                            {{ge, r6, r4, plus, r13, LSR, 1, Offset},
283                             false,
284                             al,
285                             "ge r6 r4 plus r13 LSR 1 Offset",
286                             "ge_r6_r4_plus_r13_LSR_1_Offset"},
287                            {{al, r1, r11, plus, r12, LSR, 1, Offset},
288                             false,
289                             al,
290                             "al r1 r11 plus r12 LSR 1 Offset",
291                             "al_r1_r11_plus_r12_LSR_1_Offset"},
292                            {{le, r6, r11, plus, r3, LSR, 1, Offset},
293                             false,
294                             al,
295                             "le r6 r11 plus r3 LSR 1 Offset",
296                             "le_r6_r11_plus_r3_LSR_1_Offset"},
297                            {{al, r6, r6, plus, r13, LSR, 1, Offset},
298                             false,
299                             al,
300                             "al r6 r6 plus r13 LSR 1 Offset",
301                             "al_r6_r6_plus_r13_LSR_1_Offset"},
302                            {{gt, r14, r11, plus, r2, LSR, 1, Offset},
303                             false,
304                             al,
305                             "gt r14 r11 plus r2 LSR 1 Offset",
306                             "gt_r14_r11_plus_r2_LSR_1_Offset"},
307                            {{vs, r5, r8, plus, r12, LSR, 1, Offset},
308                             false,
309                             al,
310                             "vs r5 r8 plus r12 LSR 1 Offset",
311                             "vs_r5_r8_plus_r12_LSR_1_Offset"},
312                            {{ls, r8, r12, plus, r6, LSR, 1, Offset},
313                             false,
314                             al,
315                             "ls r8 r12 plus r6 LSR 1 Offset",
316                             "ls_r8_r12_plus_r6_LSR_1_Offset"},
317                            {{vs, r6, r12, plus, r14, LSR, 1, Offset},
318                             false,
319                             al,
320                             "vs r6 r12 plus r14 LSR 1 Offset",
321                             "vs_r6_r12_plus_r14_LSR_1_Offset"},
322                            {{pl, r7, r2, plus, r7, LSR, 1, Offset},
323                             false,
324                             al,
325                             "pl r7 r2 plus r7 LSR 1 Offset",
326                             "pl_r7_r2_plus_r7_LSR_1_Offset"},
327                            {{gt, r5, r4, plus, r13, LSR, 1, Offset},
328                             false,
329                             al,
330                             "gt r5 r4 plus r13 LSR 1 Offset",
331                             "gt_r5_r4_plus_r13_LSR_1_Offset"},
332                            {{hi, r2, r7, plus, r12, LSR, 1, Offset},
333                             false,
334                             al,
335                             "hi r2 r7 plus r12 LSR 1 Offset",
336                             "hi_r2_r7_plus_r12_LSR_1_Offset"},
337                            {{ne, r2, r3, plus, r10, LSR, 1, Offset},
338                             false,
339                             al,
340                             "ne r2 r3 plus r10 LSR 1 Offset",
341                             "ne_r2_r3_plus_r10_LSR_1_Offset"},
342                            {{lt, r13, r2, plus, r6, LSR, 1, Offset},
343                             false,
344                             al,
345                             "lt r13 r2 plus r6 LSR 1 Offset",
346                             "lt_r13_r2_plus_r6_LSR_1_Offset"},
347                            {{hi, r14, r10, plus, r11, LSR, 1, Offset},
348                             false,
349                             al,
350                             "hi r14 r10 plus r11 LSR 1 Offset",
351                             "hi_r14_r10_plus_r11_LSR_1_Offset"},
352                            {{hi, r7, r10, plus, r12, LSR, 1, Offset},
353                             false,
354                             al,
355                             "hi r7 r10 plus r12 LSR 1 Offset",
356                             "hi_r7_r10_plus_r12_LSR_1_Offset"},
357                            {{cs, r3, r12, plus, r2, LSR, 1, Offset},
358                             false,
359                             al,
360                             "cs r3 r12 plus r2 LSR 1 Offset",
361                             "cs_r3_r12_plus_r2_LSR_1_Offset"},
362                            {{ls, r11, r5, plus, r1, LSR, 1, Offset},
363                             false,
364                             al,
365                             "ls r11 r5 plus r1 LSR 1 Offset",
366                             "ls_r11_r5_plus_r1_LSR_1_Offset"},
367                            {{hi, r5, r2, plus, r11, LSR, 1, Offset},
368                             false,
369                             al,
370                             "hi r5 r2 plus r11 LSR 1 Offset",
371                             "hi_r5_r2_plus_r11_LSR_1_Offset"},
372                            {{cc, r11, r8, plus, r6, LSR, 1, Offset},
373                             false,
374                             al,
375                             "cc r11 r8 plus r6 LSR 1 Offset",
376                             "cc_r11_r8_plus_r6_LSR_1_Offset"},
377                            {{lt, r11, r3, plus, r9, LSR, 1, Offset},
378                             false,
379                             al,
380                             "lt r11 r3 plus r9 LSR 1 Offset",
381                             "lt_r11_r3_plus_r9_LSR_1_Offset"},
382                            {{ne, r11, r9, plus, r8, LSR, 1, Offset},
383                             false,
384                             al,
385                             "ne r11 r9 plus r8 LSR 1 Offset",
386                             "ne_r11_r9_plus_r8_LSR_1_Offset"},
387                            {{lt, r7, r0, plus, r14, LSR, 1, Offset},
388                             false,
389                             al,
390                             "lt r7 r0 plus r14 LSR 1 Offset",
391                             "lt_r7_r0_plus_r14_LSR_1_Offset"},
392                            {{ge, r12, r3, plus, r1, LSR, 1, Offset},
393                             false,
394                             al,
395                             "ge r12 r3 plus r1 LSR 1 Offset",
396                             "ge_r12_r3_plus_r1_LSR_1_Offset"},
397                            {{le, r0, r8, plus, r13, LSR, 1, Offset},
398                             false,
399                             al,
400                             "le r0 r8 plus r13 LSR 1 Offset",
401                             "le_r0_r8_plus_r13_LSR_1_Offset"},
402                            {{vc, r5, r13, plus, r7, LSR, 1, Offset},
403                             false,
404                             al,
405                             "vc r5 r13 plus r7 LSR 1 Offset",
406                             "vc_r5_r13_plus_r7_LSR_1_Offset"},
407                            {{ge, r7, r5, plus, r11, LSR, 1, Offset},
408                             false,
409                             al,
410                             "ge r7 r5 plus r11 LSR 1 Offset",
411                             "ge_r7_r5_plus_r11_LSR_1_Offset"},
412                            {{ge, r10, r9, plus, r3, LSR, 1, Offset},
413                             false,
414                             al,
415                             "ge r10 r9 plus r3 LSR 1 Offset",
416                             "ge_r10_r9_plus_r3_LSR_1_Offset"},
417                            {{vs, r9, r5, plus, r2, LSR, 1, Offset},
418                             false,
419                             al,
420                             "vs r9 r5 plus r2 LSR 1 Offset",
421                             "vs_r9_r5_plus_r2_LSR_1_Offset"},
422                            {{hi, r2, r10, plus, r4, LSR, 1, Offset},
423                             false,
424                             al,
425                             "hi r2 r10 plus r4 LSR 1 Offset",
426                             "hi_r2_r10_plus_r4_LSR_1_Offset"},
427                            {{ge, r1, r11, plus, r1, LSR, 1, Offset},
428                             false,
429                             al,
430                             "ge r1 r11 plus r1 LSR 1 Offset",
431                             "ge_r1_r11_plus_r1_LSR_1_Offset"},
432                            {{ls, r9, r14, plus, r12, LSR, 1, Offset},
433                             false,
434                             al,
435                             "ls r9 r14 plus r12 LSR 1 Offset",
436                             "ls_r9_r14_plus_r12_LSR_1_Offset"},
437                            {{mi, r1, r9, plus, r4, LSR, 1, Offset},
438                             false,
439                             al,
440                             "mi r1 r9 plus r4 LSR 1 Offset",
441                             "mi_r1_r9_plus_r4_LSR_1_Offset"},
442                            {{mi, r7, r10, plus, r4, LSR, 1, Offset},
443                             false,
444                             al,
445                             "mi r7 r10 plus r4 LSR 1 Offset",
446                             "mi_r7_r10_plus_r4_LSR_1_Offset"},
447                            {{gt, r6, r2, plus, r5, LSR, 1, Offset},
448                             false,
449                             al,
450                             "gt r6 r2 plus r5 LSR 1 Offset",
451                             "gt_r6_r2_plus_r5_LSR_1_Offset"},
452                            {{eq, r10, r8, plus, r11, LSR, 1, Offset},
453                             false,
454                             al,
455                             "eq r10 r8 plus r11 LSR 1 Offset",
456                             "eq_r10_r8_plus_r11_LSR_1_Offset"},
457                            {{le, r10, r1, plus, r7, LSR, 1, Offset},
458                             false,
459                             al,
460                             "le r10 r1 plus r7 LSR 1 Offset",
461                             "le_r10_r1_plus_r7_LSR_1_Offset"},
462                            {{pl, r8, r14, plus, r8, LSR, 1, Offset},
463                             false,
464                             al,
465                             "pl r8 r14 plus r8 LSR 1 Offset",
466                             "pl_r8_r14_plus_r8_LSR_1_Offset"},
467                            {{gt, r5, r1, plus, r3, LSR, 1, Offset},
468                             false,
469                             al,
470                             "gt r5 r1 plus r3 LSR 1 Offset",
471                             "gt_r5_r1_plus_r3_LSR_1_Offset"},
472                            {{cs, r10, r4, plus, r13, LSR, 1, Offset},
473                             false,
474                             al,
475                             "cs r10 r4 plus r13 LSR 1 Offset",
476                             "cs_r10_r4_plus_r13_LSR_1_Offset"},
477                            {{mi, r10, r5, plus, r2, LSR, 1, Offset},
478                             false,
479                             al,
480                             "mi r10 r5 plus r2 LSR 1 Offset",
481                             "mi_r10_r5_plus_r2_LSR_1_Offset"},
482                            {{cc, r6, r0, plus, r11, LSR, 1, Offset},
483                             false,
484                             al,
485                             "cc r6 r0 plus r11 LSR 1 Offset",
486                             "cc_r6_r0_plus_r11_LSR_1_Offset"},
487                            {{eq, r3, r9, plus, r2, LSR, 1, Offset},
488                             false,
489                             al,
490                             "eq r3 r9 plus r2 LSR 1 Offset",
491                             "eq_r3_r9_plus_r2_LSR_1_Offset"},
492                            {{al, r1, r0, plus, r3, LSR, 1, Offset},
493                             false,
494                             al,
495                             "al r1 r0 plus r3 LSR 1 Offset",
496                             "al_r1_r0_plus_r3_LSR_1_Offset"},
497                            {{mi, r1, r0, plus, r13, LSR, 1, Offset},
498                             false,
499                             al,
500                             "mi r1 r0 plus r13 LSR 1 Offset",
501                             "mi_r1_r0_plus_r13_LSR_1_Offset"},
502                            {{cc, r4, r4, plus, r5, LSR, 1, Offset},
503                             false,
504                             al,
505                             "cc r4 r4 plus r5 LSR 1 Offset",
506                             "cc_r4_r4_plus_r5_LSR_1_Offset"},
507                            {{al, r2, r6, plus, r11, LSR, 1, Offset},
508                             false,
509                             al,
510                             "al r2 r6 plus r11 LSR 1 Offset",
511                             "al_r2_r6_plus_r11_LSR_1_Offset"},
512                            {{ls, r1, r5, plus, r4, LSR, 1, Offset},
513                             false,
514                             al,
515                             "ls r1 r5 plus r4 LSR 1 Offset",
516                             "ls_r1_r5_plus_r4_LSR_1_Offset"},
517                            {{eq, r0, r3, plus, r4, LSR, 1, Offset},
518                             false,
519                             al,
520                             "eq r0 r3 plus r4 LSR 1 Offset",
521                             "eq_r0_r3_plus_r4_LSR_1_Offset"},
522                            {{lt, r7, r11, plus, r10, LSR, 1, Offset},
523                             false,
524                             al,
525                             "lt r7 r11 plus r10 LSR 1 Offset",
526                             "lt_r7_r11_plus_r10_LSR_1_Offset"},
527                            {{vc, r3, r0, plus, r13, LSR, 1, Offset},
528                             false,
529                             al,
530                             "vc r3 r0 plus r13 LSR 1 Offset",
531                             "vc_r3_r0_plus_r13_LSR_1_Offset"},
532                            {{ls, r3, r3, plus, r7, LSR, 1, Offset},
533                             false,
534                             al,
535                             "ls r3 r3 plus r7 LSR 1 Offset",
536                             "ls_r3_r3_plus_r7_LSR_1_Offset"},
537                            {{al, r5, r14, plus, r3, LSR, 1, Offset},
538                             false,
539                             al,
540                             "al r5 r14 plus r3 LSR 1 Offset",
541                             "al_r5_r14_plus_r3_LSR_1_Offset"},
542                            {{ne, r2, r13, plus, r9, LSR, 1, Offset},
543                             false,
544                             al,
545                             "ne r2 r13 plus r9 LSR 1 Offset",
546                             "ne_r2_r13_plus_r9_LSR_1_Offset"},
547                            {{lt, r6, r2, plus, r11, LSR, 1, Offset},
548                             false,
549                             al,
550                             "lt r6 r2 plus r11 LSR 1 Offset",
551                             "lt_r6_r2_plus_r11_LSR_1_Offset"},
552                            {{vc, r9, r2, plus, r13, LSR, 1, Offset},
553                             false,
554                             al,
555                             "vc r9 r2 plus r13 LSR 1 Offset",
556                             "vc_r9_r2_plus_r13_LSR_1_Offset"},
557                            {{ne, r5, r9, plus, r6, LSR, 1, Offset},
558                             false,
559                             al,
560                             "ne r5 r9 plus r6 LSR 1 Offset",
561                             "ne_r5_r9_plus_r6_LSR_1_Offset"},
562                            {{vc, r4, r9, plus, r8, LSR, 1, Offset},
563                             false,
564                             al,
565                             "vc r4 r9 plus r8 LSR 1 Offset",
566                             "vc_r4_r9_plus_r8_LSR_1_Offset"},
567                            {{cc, r6, r9, plus, r2, LSR, 1, Offset},
568                             false,
569                             al,
570                             "cc r6 r9 plus r2 LSR 1 Offset",
571                             "cc_r6_r9_plus_r2_LSR_1_Offset"},
572                            {{vs, r8, r7, plus, r13, LSR, 1, Offset},
573                             false,
574                             al,
575                             "vs r8 r7 plus r13 LSR 1 Offset",
576                             "vs_r8_r7_plus_r13_LSR_1_Offset"},
577                            {{pl, r14, r14, plus, r7, LSR, 1, Offset},
578                             false,
579                             al,
580                             "pl r14 r14 plus r7 LSR 1 Offset",
581                             "pl_r14_r14_plus_r7_LSR_1_Offset"},
582                            {{eq, r8, r2, plus, r6, LSR, 1, Offset},
583                             false,
584                             al,
585                             "eq r8 r2 plus r6 LSR 1 Offset",
586                             "eq_r8_r2_plus_r6_LSR_1_Offset"},
587                            {{al, r13, r13, plus, r13, LSR, 1, Offset},
588                             false,
589                             al,
590                             "al r13 r13 plus r13 LSR 1 Offset",
591                             "al_r13_r13_plus_r13_LSR_1_Offset"},
592                            {{gt, r12, r14, plus, r5, LSR, 1, Offset},
593                             false,
594                             al,
595                             "gt r12 r14 plus r5 LSR 1 Offset",
596                             "gt_r12_r14_plus_r5_LSR_1_Offset"},
597                            {{lt, r14, r7, plus, r1, LSR, 1, Offset},
598                             false,
599                             al,
600                             "lt r14 r7 plus r1 LSR 1 Offset",
601                             "lt_r14_r7_plus_r1_LSR_1_Offset"},
602                            {{al, r0, r2, plus, r12, LSR, 20, Offset},
603                             false,
604                             al,
605                             "al r0 r2 plus r12 LSR 20 Offset",
606                             "al_r0_r2_plus_r12_LSR_20_Offset"},
607                            {{al, r0, r4, plus, r4, LSR, 19, Offset},
608                             false,
609                             al,
610                             "al r0 r4 plus r4 LSR 19 Offset",
611                             "al_r0_r4_plus_r4_LSR_19_Offset"},
612                            {{al, r0, r13, plus, r3, LSR, 28, Offset},
613                             false,
614                             al,
615                             "al r0 r13 plus r3 LSR 28 Offset",
616                             "al_r0_r13_plus_r3_LSR_28_Offset"},
617                            {{al, r0, r14, minus, r1, ASR, 1, Offset},
618                             false,
619                             al,
620                             "al r0 r14 minus r1 ASR 1 Offset",
621                             "al_r0_r14_minus_r1_ASR_1_Offset"},
622                            {{al, r0, r4, plus, r8, ASR, 4, Offset},
623                             false,
624                             al,
625                             "al r0 r4 plus r8 ASR 4 Offset",
626                             "al_r0_r4_plus_r8_ASR_4_Offset"},
627                            {{al, r0, r9, minus, r1, ASR, 26, Offset},
628                             false,
629                             al,
630                             "al r0 r9 minus r1 ASR 26 Offset",
631                             "al_r0_r9_minus_r1_ASR_26_Offset"},
632                            {{al, r0, r6, minus, r9, LSR, 20, Offset},
633                             false,
634                             al,
635                             "al r0 r6 minus r9 LSR 20 Offset",
636                             "al_r0_r6_minus_r9_LSR_20_Offset"},
637                            {{al, r0, r0, plus, r13, ASR, 13, Offset},
638                             false,
639                             al,
640                             "al r0 r0 plus r13 ASR 13 Offset",
641                             "al_r0_r0_plus_r13_ASR_13_Offset"},
642                            {{al, r0, r9, minus, r7, ASR, 23, Offset},
643                             false,
644                             al,
645                             "al r0 r9 minus r7 ASR 23 Offset",
646                             "al_r0_r9_minus_r7_ASR_23_Offset"},
647                            {{al, r0, r13, minus, r5, ASR, 25, Offset},
648                             false,
649                             al,
650                             "al r0 r13 minus r5 ASR 25 Offset",
651                             "al_r0_r13_minus_r5_ASR_25_Offset"},
652                            {{al, r0, r7, plus, r5, ASR, 14, Offset},
653                             false,
654                             al,
655                             "al r0 r7 plus r5 ASR 14 Offset",
656                             "al_r0_r7_plus_r5_ASR_14_Offset"},
657                            {{al, r0, r3, minus, r6, LSR, 28, Offset},
658                             false,
659                             al,
660                             "al r0 r3 minus r6 LSR 28 Offset",
661                             "al_r0_r3_minus_r6_LSR_28_Offset"},
662                            {{al, r0, r7, plus, r5, LSR, 27, Offset},
663                             false,
664                             al,
665                             "al r0 r7 plus r5 LSR 27 Offset",
666                             "al_r0_r7_plus_r5_LSR_27_Offset"},
667                            {{al, r0, r2, minus, r5, ASR, 19, Offset},
668                             false,
669                             al,
670                             "al r0 r2 minus r5 ASR 19 Offset",
671                             "al_r0_r2_minus_r5_ASR_19_Offset"},
672                            {{al, r0, r10, minus, r7, ASR, 18, Offset},
673                             false,
674                             al,
675                             "al r0 r10 minus r7 ASR 18 Offset",
676                             "al_r0_r10_minus_r7_ASR_18_Offset"},
677                            {{al, r0, r0, minus, r1, ASR, 10, Offset},
678                             false,
679                             al,
680                             "al r0 r0 minus r1 ASR 10 Offset",
681                             "al_r0_r0_minus_r1_ASR_10_Offset"},
682                            {{al, r0, r8, plus, r14, ASR, 17, Offset},
683                             false,
684                             al,
685                             "al r0 r8 plus r14 ASR 17 Offset",
686                             "al_r0_r8_plus_r14_ASR_17_Offset"},
687                            {{al, r0, r4, minus, r7, LSR, 14, Offset},
688                             false,
689                             al,
690                             "al r0 r4 minus r7 LSR 14 Offset",
691                             "al_r0_r4_minus_r7_LSR_14_Offset"},
692                            {{al, r0, r14, minus, r4, ASR, 13, Offset},
693                             false,
694                             al,
695                             "al r0 r14 minus r4 ASR 13 Offset",
696                             "al_r0_r14_minus_r4_ASR_13_Offset"},
697                            {{al, r0, r9, minus, r2, ASR, 6, Offset},
698                             false,
699                             al,
700                             "al r0 r9 minus r2 ASR 6 Offset",
701                             "al_r0_r9_minus_r2_ASR_6_Offset"},
702                            {{al, r0, r12, plus, r1, LSR, 19, Offset},
703                             false,
704                             al,
705                             "al r0 r12 plus r1 LSR 19 Offset",
706                             "al_r0_r12_plus_r1_LSR_19_Offset"},
707                            {{al, r0, r9, plus, r4, LSR, 4, Offset},
708                             false,
709                             al,
710                             "al r0 r9 plus r4 LSR 4 Offset",
711                             "al_r0_r9_plus_r4_LSR_4_Offset"},
712                            {{al, r0, r6, plus, r14, LSR, 10, Offset},
713                             false,
714                             al,
715                             "al r0 r6 plus r14 LSR 10 Offset",
716                             "al_r0_r6_plus_r14_LSR_10_Offset"},
717                            {{al, r0, r6, minus, r6, LSR, 25, Offset},
718                             false,
719                             al,
720                             "al r0 r6 minus r6 LSR 25 Offset",
721                             "al_r0_r6_minus_r6_LSR_25_Offset"},
722                            {{al, r0, r12, plus, r8, ASR, 14, Offset},
723                             false,
724                             al,
725                             "al r0 r12 plus r8 ASR 14 Offset",
726                             "al_r0_r12_plus_r8_ASR_14_Offset"},
727                            {{al, r0, r0, plus, r7, LSR, 32, Offset},
728                             false,
729                             al,
730                             "al r0 r0 plus r7 LSR 32 Offset",
731                             "al_r0_r0_plus_r7_LSR_32_Offset"},
732                            {{al, r0, r10, minus, r2, LSR, 23, Offset},
733                             false,
734                             al,
735                             "al r0 r10 minus r2 LSR 23 Offset",
736                             "al_r0_r10_minus_r2_LSR_23_Offset"},
737                            {{al, r0, r2, plus, r1, ASR, 1, Offset},
738                             false,
739                             al,
740                             "al r0 r2 plus r1 ASR 1 Offset",
741                             "al_r0_r2_plus_r1_ASR_1_Offset"},
742                            {{al, r0, r13, minus, r11, LSR, 2, Offset},
743                             false,
744                             al,
745                             "al r0 r13 minus r11 LSR 2 Offset",
746                             "al_r0_r13_minus_r11_LSR_2_Offset"},
747                            {{al, r0, r8, plus, r11, LSR, 10, Offset},
748                             false,
749                             al,
750                             "al r0 r8 plus r11 LSR 10 Offset",
751                             "al_r0_r8_plus_r11_LSR_10_Offset"},
752                            {{al, r0, r0, plus, r8, ASR, 1, Offset},
753                             false,
754                             al,
755                             "al r0 r0 plus r8 ASR 1 Offset",
756                             "al_r0_r0_plus_r8_ASR_1_Offset"},
757                            {{al, r0, r4, minus, r6, ASR, 14, Offset},
758                             false,
759                             al,
760                             "al r0 r4 minus r6 ASR 14 Offset",
761                             "al_r0_r4_minus_r6_ASR_14_Offset"},
762                            {{al, r0, r2, minus, r1, ASR, 25, Offset},
763                             false,
764                             al,
765                             "al r0 r2 minus r1 ASR 25 Offset",
766                             "al_r0_r2_minus_r1_ASR_25_Offset"},
767                            {{al, r0, r12, plus, r6, LSR, 21, Offset},
768                             false,
769                             al,
770                             "al r0 r12 plus r6 LSR 21 Offset",
771                             "al_r0_r12_plus_r6_LSR_21_Offset"},
772                            {{al, r0, r6, plus, r12, ASR, 18, Offset},
773                             false,
774                             al,
775                             "al r0 r6 plus r12 ASR 18 Offset",
776                             "al_r0_r6_plus_r12_ASR_18_Offset"},
777                            {{al, r0, r9, plus, r13, LSR, 15, Offset},
778                             false,
779                             al,
780                             "al r0 r9 plus r13 LSR 15 Offset",
781                             "al_r0_r9_plus_r13_LSR_15_Offset"},
782                            {{al, r0, r6, plus, r6, LSR, 26, Offset},
783                             false,
784                             al,
785                             "al r0 r6 plus r6 LSR 26 Offset",
786                             "al_r0_r6_plus_r6_LSR_26_Offset"},
787                            {{al, r0, r4, minus, r9, ASR, 14, Offset},
788                             false,
789                             al,
790                             "al r0 r4 minus r9 ASR 14 Offset",
791                             "al_r0_r4_minus_r9_ASR_14_Offset"},
792                            {{al, r0, r0, plus, r7, ASR, 6, Offset},
793                             false,
794                             al,
795                             "al r0 r0 plus r7 ASR 6 Offset",
796                             "al_r0_r0_plus_r7_ASR_6_Offset"},
797                            {{al, r0, r14, plus, r8, ASR, 9, Offset},
798                             false,
799                             al,
800                             "al r0 r14 plus r8 ASR 9 Offset",
801                             "al_r0_r14_plus_r8_ASR_9_Offset"},
802                            {{al, r0, r10, plus, r7, LSR, 4, Offset},
803                             false,
804                             al,
805                             "al r0 r10 plus r7 LSR 4 Offset",
806                             "al_r0_r10_plus_r7_LSR_4_Offset"},
807                            {{al, r0, r11, plus, r3, LSR, 13, Offset},
808                             false,
809                             al,
810                             "al r0 r11 plus r3 LSR 13 Offset",
811                             "al_r0_r11_plus_r3_LSR_13_Offset"},
812                            {{al, r0, r13, plus, r3, LSR, 25, Offset},
813                             false,
814                             al,
815                             "al r0 r13 plus r3 LSR 25 Offset",
816                             "al_r0_r13_plus_r3_LSR_25_Offset"},
817                            {{al, r0, r4, plus, r3, ASR, 13, Offset},
818                             false,
819                             al,
820                             "al r0 r4 plus r3 ASR 13 Offset",
821                             "al_r0_r4_plus_r3_ASR_13_Offset"},
822                            {{al, r0, r4, minus, r2, LSR, 2, Offset},
823                             false,
824                             al,
825                             "al r0 r4 minus r2 LSR 2 Offset",
826                             "al_r0_r4_minus_r2_LSR_2_Offset"},
827                            {{al, r0, r13, minus, r7, LSR, 1, Offset},
828                             false,
829                             al,
830                             "al r0 r13 minus r7 LSR 1 Offset",
831                             "al_r0_r13_minus_r7_LSR_1_Offset"},
832                            {{al, r0, r10, minus, r9, LSR, 7, Offset},
833                             false,
834                             al,
835                             "al r0 r10 minus r9 LSR 7 Offset",
836                             "al_r0_r10_minus_r9_LSR_7_Offset"},
837                            {{al, r0, r0, plus, r0, LSR, 10, Offset},
838                             false,
839                             al,
840                             "al r0 r0 plus r0 LSR 10 Offset",
841                             "al_r0_r0_plus_r0_LSR_10_Offset"},
842                            {{al, r0, r5, minus, r1, LSR, 23, Offset},
843                             false,
844                             al,
845                             "al r0 r5 minus r1 LSR 23 Offset",
846                             "al_r0_r5_minus_r1_LSR_23_Offset"},
847                            {{al, r0, r3, plus, r10, LSR, 21, Offset},
848                             false,
849                             al,
850                             "al r0 r3 plus r10 LSR 21 Offset",
851                             "al_r0_r3_plus_r10_LSR_21_Offset"},
852                            {{al, r0, r1, plus, r11, ASR, 22, Offset},
853                             false,
854                             al,
855                             "al r0 r1 plus r11 ASR 22 Offset",
856                             "al_r0_r1_plus_r11_ASR_22_Offset"},
857                            {{al, r0, r4, minus, r6, ASR, 28, Offset},
858                             false,
859                             al,
860                             "al r0 r4 minus r6 ASR 28 Offset",
861                             "al_r0_r4_minus_r6_ASR_28_Offset"},
862                            {{al, r0, r4, plus, r10, LSR, 29, Offset},
863                             false,
864                             al,
865                             "al r0 r4 plus r10 LSR 29 Offset",
866                             "al_r0_r4_plus_r10_LSR_29_Offset"},
867                            {{al, r0, r4, plus, r3, LSR, 10, Offset},
868                             false,
869                             al,
870                             "al r0 r4 plus r3 LSR 10 Offset",
871                             "al_r0_r4_plus_r3_LSR_10_Offset"},
872                            {{al, r0, r14, minus, r12, LSR, 11, Offset},
873                             false,
874                             al,
875                             "al r0 r14 minus r12 LSR 11 Offset",
876                             "al_r0_r14_minus_r12_LSR_11_Offset"},
877                            {{al, r0, r5, plus, r3, LSR, 6, Offset},
878                             false,
879                             al,
880                             "al r0 r5 plus r3 LSR 6 Offset",
881                             "al_r0_r5_plus_r3_LSR_6_Offset"},
882                            {{al, r0, r3, minus, r9, ASR, 18, Offset},
883                             false,
884                             al,
885                             "al r0 r3 minus r9 ASR 18 Offset",
886                             "al_r0_r3_minus_r9_ASR_18_Offset"},
887                            {{al, r0, r3, minus, r10, ASR, 21, Offset},
888                             false,
889                             al,
890                             "al r0 r3 minus r10 ASR 21 Offset",
891                             "al_r0_r3_minus_r10_ASR_21_Offset"},
892                            {{al, r0, r9, minus, r4, ASR, 2, Offset},
893                             false,
894                             al,
895                             "al r0 r9 minus r4 ASR 2 Offset",
896                             "al_r0_r9_minus_r4_ASR_2_Offset"},
897                            {{al, r0, r4, plus, r7, LSR, 23, Offset},
898                             false,
899                             al,
900                             "al r0 r4 plus r7 LSR 23 Offset",
901                             "al_r0_r4_plus_r7_LSR_23_Offset"},
902                            {{al, r0, r4, plus, r9, ASR, 17, Offset},
903                             false,
904                             al,
905                             "al r0 r4 plus r9 ASR 17 Offset",
906                             "al_r0_r4_plus_r9_ASR_17_Offset"},
907                            {{al, r0, r2, plus, r1, ASR, 14, Offset},
908                             false,
909                             al,
910                             "al r0 r2 plus r1 ASR 14 Offset",
911                             "al_r0_r2_plus_r1_ASR_14_Offset"},
912                            {{al, r0, r7, minus, r3, ASR, 14, Offset},
913                             false,
914                             al,
915                             "al r0 r7 minus r3 ASR 14 Offset",
916                             "al_r0_r7_minus_r3_ASR_14_Offset"},
917                            {{al, r0, r6, minus, r7, ASR, 13, Offset},
918                             false,
919                             al,
920                             "al r0 r6 minus r7 ASR 13 Offset",
921                             "al_r0_r6_minus_r7_ASR_13_Offset"},
922                            {{al, r0, r3, plus, r14, ASR, 25, Offset},
923                             false,
924                             al,
925                             "al r0 r3 plus r14 ASR 25 Offset",
926                             "al_r0_r3_plus_r14_ASR_25_Offset"},
927                            {{al, r0, r5, plus, r8, LSR, 14, Offset},
928                             false,
929                             al,
930                             "al r0 r5 plus r8 LSR 14 Offset",
931                             "al_r0_r5_plus_r8_LSR_14_Offset"},
932                            {{al, r0, r5, minus, r11, LSR, 10, Offset},
933                             false,
934                             al,
935                             "al r0 r5 minus r11 LSR 10 Offset",
936                             "al_r0_r5_minus_r11_LSR_10_Offset"},
937                            {{al, r0, r0, plus, r11, ASR, 14, Offset},
938                             false,
939                             al,
940                             "al r0 r0 plus r11 ASR 14 Offset",
941                             "al_r0_r0_plus_r11_ASR_14_Offset"},
942                            {{al, r0, r9, plus, r12, LSR, 15, Offset},
943                             false,
944                             al,
945                             "al r0 r9 plus r12 LSR 15 Offset",
946                             "al_r0_r9_plus_r12_LSR_15_Offset"},
947                            {{al, r0, r3, minus, r7, ASR, 3, Offset},
948                             false,
949                             al,
950                             "al r0 r3 minus r7 ASR 3 Offset",
951                             "al_r0_r3_minus_r7_ASR_3_Offset"},
952                            {{al, r0, r4, minus, r8, LSR, 4, Offset},
953                             false,
954                             al,
955                             "al r0 r4 minus r8 LSR 4 Offset",
956                             "al_r0_r4_minus_r8_LSR_4_Offset"},
957                            {{al, r0, r4, minus, r14, ASR, 12, Offset},
958                             false,
959                             al,
960                             "al r0 r4 minus r14 ASR 12 Offset",
961                             "al_r0_r4_minus_r14_ASR_12_Offset"},
962                            {{al, r0, r1, plus, r1, ASR, 10, Offset},
963                             false,
964                             al,
965                             "al r0 r1 plus r1 ASR 10 Offset",
966                             "al_r0_r1_plus_r1_ASR_10_Offset"},
967                            {{al, r0, r5, plus, r7, LSR, 24, Offset},
968                             false,
969                             al,
970                             "al r0 r5 plus r7 LSR 24 Offset",
971                             "al_r0_r5_plus_r7_LSR_24_Offset"},
972                            {{al, r0, r10, plus, r2, LSR, 10, Offset},
973                             false,
974                             al,
975                             "al r0 r10 plus r2 LSR 10 Offset",
976                             "al_r0_r10_plus_r2_LSR_10_Offset"},
977                            {{al, r0, r13, minus, r3, LSR, 29, Offset},
978                             false,
979                             al,
980                             "al r0 r13 minus r3 LSR 29 Offset",
981                             "al_r0_r13_minus_r3_LSR_29_Offset"},
982                            {{al, r0, r8, minus, r8, LSR, 22, Offset},
983                             false,
984                             al,
985                             "al r0 r8 minus r8 LSR 22 Offset",
986                             "al_r0_r8_minus_r8_LSR_22_Offset"},
987                            {{al, r0, r14, minus, r10, LSR, 20, Offset},
988                             false,
989                             al,
990                             "al r0 r14 minus r10 LSR 20 Offset",
991                             "al_r0_r14_minus_r10_LSR_20_Offset"},
992                            {{al, r0, r12, plus, r10, LSR, 10, Offset},
993                             false,
994                             al,
995                             "al r0 r12 plus r10 LSR 10 Offset",
996                             "al_r0_r12_plus_r10_LSR_10_Offset"},
997                            {{al, r0, r3, plus, r12, LSR, 25, Offset},
998                             false,
999                             al,
1000                             "al r0 r3 plus r12 LSR 25 Offset",
1001                             "al_r0_r3_plus_r12_LSR_25_Offset"},
1002                            {{al, r0, r2, plus, r13, ASR, 4, Offset},
1003                             false,
1004                             al,
1005                             "al r0 r2 plus r13 ASR 4 Offset",
1006                             "al_r0_r2_plus_r13_ASR_4_Offset"},
1007                            {{al, r0, r6, plus, r11, LSR, 24, Offset},
1008                             false,
1009                             al,
1010                             "al r0 r6 plus r11 LSR 24 Offset",
1011                             "al_r0_r6_plus_r11_LSR_24_Offset"},
1012                            {{al, r0, r1, plus, r5, LSR, 8, Offset},
1013                             false,
1014                             al,
1015                             "al r0 r1 plus r5 LSR 8 Offset",
1016                             "al_r0_r1_plus_r5_LSR_8_Offset"},
1017                            {{al, r0, r6, minus, r8, LSR, 12, Offset},
1018                             false,
1019                             al,
1020                             "al r0 r6 minus r8 LSR 12 Offset",
1021                             "al_r0_r6_minus_r8_LSR_12_Offset"},
1022                            {{al, r0, r4, plus, r6, LSR, 16, Offset},
1023                             false,
1024                             al,
1025                             "al r0 r4 plus r6 LSR 16 Offset",
1026                             "al_r0_r4_plus_r6_LSR_16_Offset"},
1027                            {{al, r0, r7, plus, r12, LSR, 6, Offset},
1028                             false,
1029                             al,
1030                             "al r0 r7 plus r12 LSR 6 Offset",
1031                             "al_r0_r7_plus_r12_LSR_6_Offset"},
1032                            {{al, r0, r12, plus, r8, ASR, 11, Offset},
1033                             false,
1034                             al,
1035                             "al r0 r12 plus r8 ASR 11 Offset",
1036                             "al_r0_r12_plus_r8_ASR_11_Offset"},
1037                            {{al, r0, r11, minus, r1, LSR, 17, Offset},
1038                             false,
1039                             al,
1040                             "al r0 r11 minus r1 LSR 17 Offset",
1041                             "al_r0_r11_minus_r1_LSR_17_Offset"},
1042                            {{al, r0, r4, minus, r0, LSR, 8, Offset},
1043                             false,
1044                             al,
1045                             "al r0 r4 minus r0 LSR 8 Offset",
1046                             "al_r0_r4_minus_r0_LSR_8_Offset"},
1047                            {{al, r0, r5, minus, r14, LSR, 2, Offset},
1048                             false,
1049                             al,
1050                             "al r0 r5 minus r14 LSR 2 Offset",
1051                             "al_r0_r5_minus_r14_LSR_2_Offset"},
1052                            {{al, r0, r10, minus, r8, LSR, 24, Offset},
1053                             false,
1054                             al,
1055                             "al r0 r10 minus r8 LSR 24 Offset",
1056                             "al_r0_r10_minus_r8_LSR_24_Offset"},
1057                            {{al, r0, r8, minus, r12, ASR, 4, Offset},
1058                             false,
1059                             al,
1060                             "al r0 r8 minus r12 ASR 4 Offset",
1061                             "al_r0_r8_minus_r12_ASR_4_Offset"},
1062                            {{al, r0, r3, minus, r4, ASR, 27, Offset},
1063                             false,
1064                             al,
1065                             "al r0 r3 minus r4 ASR 27 Offset",
1066                             "al_r0_r3_minus_r4_ASR_27_Offset"},
1067                            {{al, r0, r12, minus, r8, LSR, 25, Offset},
1068                             false,
1069                             al,
1070                             "al r0 r12 minus r8 LSR 25 Offset",
1071                             "al_r0_r12_minus_r8_LSR_25_Offset"},
1072                            {{al, r0, r10, minus, r13, LSR, 5, Offset},
1073                             false,
1074                             al,
1075                             "al r0 r10 minus r13 LSR 5 Offset",
1076                             "al_r0_r10_minus_r13_LSR_5_Offset"},
1077                            {{al, r0, r0, minus, r8, LSR, 26, Offset},
1078                             false,
1079                             al,
1080                             "al r0 r0 minus r8 LSR 26 Offset",
1081                             "al_r0_r0_minus_r8_LSR_26_Offset"},
1082                            {{al, r0, r4, minus, r1, LSR, 18, Offset},
1083                             false,
1084                             al,
1085                             "al r0 r4 minus r1 LSR 18 Offset",
1086                             "al_r0_r4_minus_r1_LSR_18_Offset"},
1087                            {{al, r0, r3, plus, r4, LSR, 26, Offset},
1088                             false,
1089                             al,
1090                             "al r0 r3 plus r4 LSR 26 Offset",
1091                             "al_r0_r3_plus_r4_LSR_26_Offset"},
1092                            {{al, r0, r6, plus, r1, LSR, 27, Offset},
1093                             false,
1094                             al,
1095                             "al r0 r6 plus r1 LSR 27 Offset",
1096                             "al_r0_r6_plus_r1_LSR_27_Offset"},
1097                            {{al, r0, r14, minus, r11, ASR, 9, Offset},
1098                             false,
1099                             al,
1100                             "al r0 r14 minus r11 ASR 9 Offset",
1101                             "al_r0_r14_minus_r11_ASR_9_Offset"},
1102                            {{al, r0, r5, minus, r13, LSR, 25, Offset},
1103                             false,
1104                             al,
1105                             "al r0 r5 minus r13 LSR 25 Offset",
1106                             "al_r0_r5_minus_r13_LSR_25_Offset"},
1107                            {{al, r0, r6, minus, r2, ASR, 23, Offset},
1108                             false,
1109                             al,
1110                             "al r0 r6 minus r2 ASR 23 Offset",
1111                             "al_r0_r6_minus_r2_ASR_23_Offset"},
1112                            {{al, r0, r13, minus, r3, LSR, 21, Offset},
1113                             false,
1114                             al,
1115                             "al r0 r13 minus r3 LSR 21 Offset",
1116                             "al_r0_r13_minus_r3_LSR_21_Offset"},
1117                            {{al, r0, r12, minus, r7, ASR, 10, Offset},
1118                             false,
1119                             al,
1120                             "al r0 r12 minus r7 ASR 10 Offset",
1121                             "al_r0_r12_minus_r7_ASR_10_Offset"},
1122                            {{al, r0, r0, plus, r0, ASR, 19, Offset},
1123                             false,
1124                             al,
1125                             "al r0 r0 plus r0 ASR 19 Offset",
1126                             "al_r0_r0_plus_r0_ASR_19_Offset"},
1127                            {{al, r0, r14, minus, r14, ASR, 32, Offset},
1128                             false,
1129                             al,
1130                             "al r0 r14 minus r14 ASR 32 Offset",
1131                             "al_r0_r14_minus_r14_ASR_32_Offset"},
1132                            {{al, r0, r9, plus, r11, LSR, 4, Offset},
1133                             false,
1134                             al,
1135                             "al r0 r9 plus r11 LSR 4 Offset",
1136                             "al_r0_r9_plus_r11_LSR_4_Offset"},
1137                            {{al, r0, r10, minus, r12, ASR, 28, Offset},
1138                             false,
1139                             al,
1140                             "al r0 r10 minus r12 ASR 28 Offset",
1141                             "al_r0_r10_minus_r12_ASR_28_Offset"},
1142                            {{al, r0, r1, minus, r3, LSR, 15, Offset},
1143                             false,
1144                             al,
1145                             "al r0 r1 minus r3 LSR 15 Offset",
1146                             "al_r0_r1_minus_r3_LSR_15_Offset"},
1147                            {{al, r0, r0, plus, r3, LSR, 5, Offset},
1148                             false,
1149                             al,
1150                             "al r0 r0 plus r3 LSR 5 Offset",
1151                             "al_r0_r0_plus_r3_LSR_5_Offset"},
1152                            {{al, r0, r2, plus, r9, ASR, 16, Offset},
1153                             false,
1154                             al,
1155                             "al r0 r2 plus r9 ASR 16 Offset",
1156                             "al_r0_r2_plus_r9_ASR_16_Offset"},
1157                            {{al, r0, r7, minus, r3, ASR, 30, Offset},
1158                             false,
1159                             al,
1160                             "al r0 r7 minus r3 ASR 30 Offset",
1161                             "al_r0_r7_minus_r3_ASR_30_Offset"},
1162                            {{al, r0, r10, minus, r1, ASR, 31, Offset},
1163                             false,
1164                             al,
1165                             "al r0 r10 minus r1 ASR 31 Offset",
1166                             "al_r0_r10_minus_r1_ASR_31_Offset"},
1167                            {{al, r0, r11, minus, r7, LSR, 26, Offset},
1168                             false,
1169                             al,
1170                             "al r0 r11 minus r7 LSR 26 Offset",
1171                             "al_r0_r11_minus_r7_LSR_26_Offset"},
1172                            {{al, r0, r0, minus, r4, LSR, 8, Offset},
1173                             false,
1174                             al,
1175                             "al r0 r0 minus r4 LSR 8 Offset",
1176                             "al_r0_r0_minus_r4_LSR_8_Offset"},
1177                            {{al, r0, r3, plus, r1, LSR, 5, Offset},
1178                             false,
1179                             al,
1180                             "al r0 r3 plus r1 LSR 5 Offset",
1181                             "al_r0_r3_plus_r1_LSR_5_Offset"},
1182                            {{al, r0, r14, minus, r1, LSR, 15, Offset},
1183                             false,
1184                             al,
1185                             "al r0 r14 minus r1 LSR 15 Offset",
1186                             "al_r0_r14_minus_r1_LSR_15_Offset"},
1187                            {{al, r0, r2, plus, r8, ASR, 7, Offset},
1188                             false,
1189                             al,
1190                             "al r0 r2 plus r8 ASR 7 Offset",
1191                             "al_r0_r2_plus_r8_ASR_7_Offset"},
1192                            {{al, r0, r11, plus, r12, ASR, 7, Offset},
1193                             false,
1194                             al,
1195                             "al r0 r11 plus r12 ASR 7 Offset",
1196                             "al_r0_r11_plus_r12_ASR_7_Offset"},
1197                            {{al, r0, r14, plus, r6, LSR, 19, Offset},
1198                             false,
1199                             al,
1200                             "al r0 r14 plus r6 LSR 19 Offset",
1201                             "al_r0_r14_plus_r6_LSR_19_Offset"},
1202                            {{al, r0, r0, minus, r6, ASR, 12, Offset},
1203                             false,
1204                             al,
1205                             "al r0 r0 minus r6 ASR 12 Offset",
1206                             "al_r0_r0_minus_r6_ASR_12_Offset"},
1207                            {{al, r0, r2, minus, r8, LSR, 24, Offset},
1208                             false,
1209                             al,
1210                             "al r0 r2 minus r8 LSR 24 Offset",
1211                             "al_r0_r2_minus_r8_LSR_24_Offset"},
1212                            {{al, r0, r2, minus, r13, LSR, 4, Offset},
1213                             false,
1214                             al,
1215                             "al r0 r2 minus r13 LSR 4 Offset",
1216                             "al_r0_r2_minus_r13_LSR_4_Offset"},
1217                            {{al, r0, r11, minus, r12, LSR, 6, Offset},
1218                             false,
1219                             al,
1220                             "al r0 r11 minus r12 LSR 6 Offset",
1221                             "al_r0_r11_minus_r12_LSR_6_Offset"},
1222                            {{al, r0, r0, plus, r9, ASR, 12, Offset},
1223                             false,
1224                             al,
1225                             "al r0 r0 plus r9 ASR 12 Offset",
1226                             "al_r0_r0_plus_r9_ASR_12_Offset"},
1227                            {{al, r0, r5, plus, r9, ASR, 25, Offset},
1228                             false,
1229                             al,
1230                             "al r0 r5 plus r9 ASR 25 Offset",
1231                             "al_r0_r5_plus_r9_ASR_25_Offset"},
1232                            {{al, r0, r0, minus, r8, ASR, 23, Offset},
1233                             false,
1234                             al,
1235                             "al r0 r0 minus r8 ASR 23 Offset",
1236                             "al_r0_r0_minus_r8_ASR_23_Offset"},
1237                            {{al, r0, r8, plus, r4, ASR, 29, Offset},
1238                             false,
1239                             al,
1240                             "al r0 r8 plus r4 ASR 29 Offset",
1241                             "al_r0_r8_plus_r4_ASR_29_Offset"},
1242                            {{al, r0, r0, minus, r1, LSR, 25, Offset},
1243                             false,
1244                             al,
1245                             "al r0 r0 minus r1 LSR 25 Offset",
1246                             "al_r0_r0_minus_r1_LSR_25_Offset"},
1247                            {{al, r0, r1, minus, r0, LSR, 25, Offset},
1248                             false,
1249                             al,
1250                             "al r0 r1 minus r0 LSR 25 Offset",
1251                             "al_r0_r1_minus_r0_LSR_25_Offset"},
1252                            {{al, r0, r2, plus, r13, LSR, 32, Offset},
1253                             false,
1254                             al,
1255                             "al r0 r2 plus r13 LSR 32 Offset",
1256                             "al_r0_r2_plus_r13_LSR_32_Offset"},
1257                            {{al, r0, r9, plus, r3, LSR, 10, Offset},
1258                             false,
1259                             al,
1260                             "al r0 r9 plus r3 LSR 10 Offset",
1261                             "al_r0_r9_plus_r3_LSR_10_Offset"},
1262                            {{al, r0, r5, minus, r4, LSR, 21, Offset},
1263                             false,
1264                             al,
1265                             "al r0 r5 minus r4 LSR 21 Offset",
1266                             "al_r0_r5_minus_r4_LSR_21_Offset"},
1267                            {{al, r0, r2, minus, r5, LSR, 30, Offset},
1268                             false,
1269                             al,
1270                             "al r0 r2 minus r5 LSR 30 Offset",
1271                             "al_r0_r2_minus_r5_LSR_30_Offset"},
1272                            {{al, r0, r2, plus, r8, LSR, 26, Offset},
1273                             false,
1274                             al,
1275                             "al r0 r2 plus r8 LSR 26 Offset",
1276                             "al_r0_r2_plus_r8_LSR_26_Offset"},
1277                            {{al, r0, r5, minus, r10, ASR, 12, Offset},
1278                             false,
1279                             al,
1280                             "al r0 r5 minus r10 ASR 12 Offset",
1281                             "al_r0_r5_minus_r10_ASR_12_Offset"},
1282                            {{al, r0, r14, minus, r0, ASR, 21, Offset},
1283                             false,
1284                             al,
1285                             "al r0 r14 minus r0 ASR 21 Offset",
1286                             "al_r0_r14_minus_r0_ASR_21_Offset"},
1287                            {{al, r0, r5, plus, r6, ASR, 1, Offset},
1288                             false,
1289                             al,
1290                             "al r0 r5 plus r6 ASR 1 Offset",
1291                             "al_r0_r5_plus_r6_ASR_1_Offset"},
1292                            {{al, r0, r3, minus, r3, ASR, 16, Offset},
1293                             false,
1294                             al,
1295                             "al r0 r3 minus r3 ASR 16 Offset",
1296                             "al_r0_r3_minus_r3_ASR_16_Offset"},
1297                            {{al, r0, r12, plus, r0, LSR, 10, Offset},
1298                             false,
1299                             al,
1300                             "al r0 r12 plus r0 LSR 10 Offset",
1301                             "al_r0_r12_plus_r0_LSR_10_Offset"},
1302                            {{al, r0, r11, plus, r5, ASR, 5, Offset},
1303                             false,
1304                             al,
1305                             "al r0 r11 plus r5 ASR 5 Offset",
1306                             "al_r0_r11_plus_r5_ASR_5_Offset"},
1307                            {{al, r0, r3, minus, r11, ASR, 19, Offset},
1308                             false,
1309                             al,
1310                             "al r0 r3 minus r11 ASR 19 Offset",
1311                             "al_r0_r3_minus_r11_ASR_19_Offset"},
1312                            {{al, r0, r4, minus, r5, LSR, 27, Offset},
1313                             false,
1314                             al,
1315                             "al r0 r4 minus r5 LSR 27 Offset",
1316                             "al_r0_r4_minus_r5_LSR_27_Offset"},
1317                            {{al, r0, r3, plus, r5, ASR, 17, Offset},
1318                             false,
1319                             al,
1320                             "al r0 r3 plus r5 ASR 17 Offset",
1321                             "al_r0_r3_plus_r5_ASR_17_Offset"},
1322                            {{al, r0, r8, plus, r5, LSR, 18, Offset},
1323                             false,
1324                             al,
1325                             "al r0 r8 plus r5 LSR 18 Offset",
1326                             "al_r0_r8_plus_r5_LSR_18_Offset"},
1327                            {{al, r0, r8, plus, r11, ASR, 24, Offset},
1328                             false,
1329                             al,
1330                             "al r0 r8 plus r11 ASR 24 Offset",
1331                             "al_r0_r8_plus_r11_ASR_24_Offset"},
1332                            {{al, r0, r10, plus, r12, LSR, 30, Offset},
1333                             false,
1334                             al,
1335                             "al r0 r10 plus r12 LSR 30 Offset",
1336                             "al_r0_r10_plus_r12_LSR_30_Offset"},
1337                            {{al, r0, r8, minus, r3, ASR, 9, Offset},
1338                             false,
1339                             al,
1340                             "al r0 r8 minus r3 ASR 9 Offset",
1341                             "al_r0_r8_minus_r3_ASR_9_Offset"},
1342                            {{al, r0, r11, plus, r9, ASR, 11, Offset},
1343                             false,
1344                             al,
1345                             "al r0 r11 plus r9 ASR 11 Offset",
1346                             "al_r0_r11_plus_r9_ASR_11_Offset"},
1347                            {{al, r0, r10, plus, r7, LSR, 22, Offset},
1348                             false,
1349                             al,
1350                             "al r0 r10 plus r7 LSR 22 Offset",
1351                             "al_r0_r10_plus_r7_LSR_22_Offset"},
1352                            {{al, r0, r10, plus, r7, ASR, 13, Offset},
1353                             false,
1354                             al,
1355                             "al r0 r10 plus r7 ASR 13 Offset",
1356                             "al_r0_r10_plus_r7_ASR_13_Offset"},
1357                            {{al, r0, r7, plus, r13, LSR, 21, Offset},
1358                             false,
1359                             al,
1360                             "al r0 r7 plus r13 LSR 21 Offset",
1361                             "al_r0_r7_plus_r13_LSR_21_Offset"},
1362                            {{al, r0, r12, minus, r1, LSR, 16, Offset},
1363                             false,
1364                             al,
1365                             "al r0 r12 minus r1 LSR 16 Offset",
1366                             "al_r0_r12_minus_r1_LSR_16_Offset"},
1367                            {{al, r0, r2, minus, r2, LSR, 4, Offset},
1368                             false,
1369                             al,
1370                             "al r0 r2 minus r2 LSR 4 Offset",
1371                             "al_r0_r2_minus_r2_LSR_4_Offset"},
1372                            {{al, r0, r13, minus, r13, ASR, 19, Offset},
1373                             false,
1374                             al,
1375                             "al r0 r13 minus r13 ASR 19 Offset",
1376                             "al_r0_r13_minus_r13_ASR_19_Offset"},
1377                            {{al, r0, r2, plus, r4, LSR, 13, Offset},
1378                             false,
1379                             al,
1380                             "al r0 r2 plus r4 LSR 13 Offset",
1381                             "al_r0_r2_plus_r4_LSR_13_Offset"},
1382                            {{al, r0, r9, plus, r1, LSR, 32, Offset},
1383                             false,
1384                             al,
1385                             "al r0 r9 plus r1 LSR 32 Offset",
1386                             "al_r0_r9_plus_r1_LSR_32_Offset"},
1387                            {{al, r0, r3, plus, r6, ASR, 21, Offset},
1388                             false,
1389                             al,
1390                             "al r0 r3 plus r6 ASR 21 Offset",
1391                             "al_r0_r3_plus_r6_ASR_21_Offset"},
1392                            {{al, r0, r2, plus, r1, LSR, 5, Offset},
1393                             false,
1394                             al,
1395                             "al r0 r2 plus r1 LSR 5 Offset",
1396                             "al_r0_r2_plus_r1_LSR_5_Offset"},
1397                            {{al, r0, r0, minus, r11, ASR, 6, Offset},
1398                             false,
1399                             al,
1400                             "al r0 r0 minus r11 ASR 6 Offset",
1401                             "al_r0_r0_minus_r11_ASR_6_Offset"},
1402                            {{al, r0, r2, minus, r9, ASR, 31, Offset},
1403                             false,
1404                             al,
1405                             "al r0 r2 minus r9 ASR 31 Offset",
1406                             "al_r0_r2_minus_r9_ASR_31_Offset"},
1407                            {{al, r0, r0, plus, r11, LSR, 6, Offset},
1408                             false,
1409                             al,
1410                             "al r0 r0 plus r11 LSR 6 Offset",
1411                             "al_r0_r0_plus_r11_LSR_6_Offset"},
1412                            {{al, r0, r10, minus, r11, LSR, 14, Offset},
1413                             false,
1414                             al,
1415                             "al r0 r10 minus r11 LSR 14 Offset",
1416                             "al_r0_r10_minus_r11_LSR_14_Offset"},
1417                            {{al, r0, r0, plus, r14, LSR, 24, Offset},
1418                             false,
1419                             al,
1420                             "al r0 r0 plus r14 LSR 24 Offset",
1421                             "al_r0_r0_plus_r14_LSR_24_Offset"},
1422                            {{al, r0, r0, plus, r2, LSR, 8, Offset},
1423                             false,
1424                             al,
1425                             "al r0 r0 plus r2 LSR 8 Offset",
1426                             "al_r0_r0_plus_r2_LSR_8_Offset"},
1427                            {{al, r0, r13, minus, r12, ASR, 10, Offset},
1428                             false,
1429                             al,
1430                             "al r0 r13 minus r12 ASR 10 Offset",
1431                             "al_r0_r13_minus_r12_ASR_10_Offset"},
1432                            {{al, r0, r2, plus, r2, LSR, 12, Offset},
1433                             false,
1434                             al,
1435                             "al r0 r2 plus r2 LSR 12 Offset",
1436                             "al_r0_r2_plus_r2_LSR_12_Offset"},
1437                            {{al, r0, r12, plus, r10, LSR, 30, Offset},
1438                             false,
1439                             al,
1440                             "al r0 r12 plus r10 LSR 30 Offset",
1441                             "al_r0_r12_plus_r10_LSR_30_Offset"},
1442                            {{al, r0, r8, minus, r0, ASR, 9, Offset},
1443                             false,
1444                             al,
1445                             "al r0 r8 minus r0 ASR 9 Offset",
1446                             "al_r0_r8_minus_r0_ASR_9_Offset"},
1447                            {{al, r0, r9, minus, r6, LSR, 4, Offset},
1448                             false,
1449                             al,
1450                             "al r0 r9 minus r6 LSR 4 Offset",
1451                             "al_r0_r9_minus_r6_LSR_4_Offset"},
1452                            {{al, r0, r3, plus, r14, ASR, 3, Offset},
1453                             false,
1454                             al,
1455                             "al r0 r3 plus r14 ASR 3 Offset",
1456                             "al_r0_r3_plus_r14_ASR_3_Offset"},
1457                            {{al, r0, r14, minus, r10, ASR, 4, Offset},
1458                             false,
1459                             al,
1460                             "al r0 r14 minus r10 ASR 4 Offset",
1461                             "al_r0_r14_minus_r10_ASR_4_Offset"},
1462                            {{al, r0, r7, plus, r8, LSR, 5, Offset},
1463                             false,
1464                             al,
1465                             "al r0 r7 plus r8 LSR 5 Offset",
1466                             "al_r0_r7_plus_r8_LSR_5_Offset"},
1467                            {{al, r0, r0, minus, r13, ASR, 17, Offset},
1468                             false,
1469                             al,
1470                             "al r0 r0 minus r13 ASR 17 Offset",
1471                             "al_r0_r0_minus_r13_ASR_17_Offset"},
1472                            {{al, r0, r3, minus, r7, LSR, 2, Offset},
1473                             false,
1474                             al,
1475                             "al r0 r3 minus r7 LSR 2 Offset",
1476                             "al_r0_r3_minus_r7_LSR_2_Offset"},
1477                            {{al, r0, r8, minus, r8, ASR, 15, Offset},
1478                             false,
1479                             al,
1480                             "al r0 r8 minus r8 ASR 15 Offset",
1481                             "al_r0_r8_minus_r8_ASR_15_Offset"},
1482                            {{al, r0, r13, plus, r12, ASR, 29, Offset},
1483                             false,
1484                             al,
1485                             "al r0 r13 plus r12 ASR 29 Offset",
1486                             "al_r0_r13_plus_r12_ASR_29_Offset"},
1487                            {{al, r0, r10, plus, r4, LSR, 22, Offset},
1488                             false,
1489                             al,
1490                             "al r0 r10 plus r4 LSR 22 Offset",
1491                             "al_r0_r10_plus_r4_LSR_22_Offset"},
1492                            {{al, r0, r2, plus, r1, ASR, 24, Offset},
1493                             false,
1494                             al,
1495                             "al r0 r2 plus r1 ASR 24 Offset",
1496                             "al_r0_r2_plus_r1_ASR_24_Offset"},
1497                            {{al, r0, r14, minus, r13, LSR, 29, Offset},
1498                             false,
1499                             al,
1500                             "al r0 r14 minus r13 LSR 29 Offset",
1501                             "al_r0_r14_minus_r13_LSR_29_Offset"},
1502                            {{al, r0, r3, plus, r1, LSR, 6, Offset},
1503                             false,
1504                             al,
1505                             "al r0 r3 plus r1 LSR 6 Offset",
1506                             "al_r0_r3_plus_r1_LSR_6_Offset"},
1507                            {{al, r0, r7, plus, r5, LSR, 32, Offset},
1508                             false,
1509                             al,
1510                             "al r0 r7 plus r5 LSR 32 Offset",
1511                             "al_r0_r7_plus_r5_LSR_32_Offset"},
1512                            {{al, r0, r12, plus, r6, LSR, 30, Offset},
1513                             false,
1514                             al,
1515                             "al r0 r12 plus r6 LSR 30 Offset",
1516                             "al_r0_r12_plus_r6_LSR_30_Offset"},
1517                            {{al, r0, r13, plus, r13, ASR, 6, Offset},
1518                             false,
1519                             al,
1520                             "al r0 r13 plus r13 ASR 6 Offset",
1521                             "al_r0_r13_plus_r13_ASR_6_Offset"},
1522                            {{al, r0, r14, minus, r0, LSR, 4, Offset},
1523                             false,
1524                             al,
1525                             "al r0 r14 minus r0 LSR 4 Offset",
1526                             "al_r0_r14_minus_r0_LSR_4_Offset"},
1527                            {{al, r0, r7, minus, r4, ASR, 6, Offset},
1528                             false,
1529                             al,
1530                             "al r0 r7 minus r4 ASR 6 Offset",
1531                             "al_r0_r7_minus_r4_ASR_6_Offset"},
1532                            {{al, r0, r9, plus, r13, ASR, 5, Offset},
1533                             false,
1534                             al,
1535                             "al r0 r9 plus r13 ASR 5 Offset",
1536                             "al_r0_r9_plus_r13_ASR_5_Offset"},
1537                            {{al, r0, r8, plus, r9, LSR, 5, Offset},
1538                             false,
1539                             al,
1540                             "al r0 r8 plus r9 LSR 5 Offset",
1541                             "al_r0_r8_plus_r9_LSR_5_Offset"},
1542                            {{al, r0, r3, plus, r11, LSR, 7, Offset},
1543                             false,
1544                             al,
1545                             "al r0 r3 plus r11 LSR 7 Offset",
1546                             "al_r0_r3_plus_r11_LSR_7_Offset"},
1547                            {{al, r0, r5, plus, r2, LSR, 11, Offset},
1548                             false,
1549                             al,
1550                             "al r0 r5 plus r2 LSR 11 Offset",
1551                             "al_r0_r5_plus_r2_LSR_11_Offset"},
1552                            {{al, r0, r10, minus, r4, LSR, 12, Offset},
1553                             false,
1554                             al,
1555                             "al r0 r10 minus r4 LSR 12 Offset",
1556                             "al_r0_r10_minus_r4_LSR_12_Offset"},
1557                            {{al, r0, r0, minus, r0, ASR, 25, Offset},
1558                             false,
1559                             al,
1560                             "al r0 r0 minus r0 ASR 25 Offset",
1561                             "al_r0_r0_minus_r0_ASR_25_Offset"},
1562                            {{al, r0, r13, minus, r10, ASR, 6, Offset},
1563                             false,
1564                             al,
1565                             "al r0 r13 minus r10 ASR 6 Offset",
1566                             "al_r0_r13_minus_r10_ASR_6_Offset"},
1567                            {{al, r0, r11, plus, r1, LSR, 20, Offset},
1568                             false,
1569                             al,
1570                             "al r0 r11 plus r1 LSR 20 Offset",
1571                             "al_r0_r11_plus_r1_LSR_20_Offset"},
1572                            {{al, r0, r13, minus, r10, LSR, 3, Offset},
1573                             false,
1574                             al,
1575                             "al r0 r13 minus r10 LSR 3 Offset",
1576                             "al_r0_r13_minus_r10_LSR_3_Offset"},
1577                            {{al, r0, r6, plus, r9, ASR, 2, Offset},
1578                             false,
1579                             al,
1580                             "al r0 r6 plus r9 ASR 2 Offset",
1581                             "al_r0_r6_plus_r9_ASR_2_Offset"},
1582                            {{al, r0, r4, minus, r7, ASR, 23, Offset},
1583                             false,
1584                             al,
1585                             "al r0 r4 minus r7 ASR 23 Offset",
1586                             "al_r0_r4_minus_r7_ASR_23_Offset"},
1587                            {{al, r0, r13, minus, r10, LSR, 11, Offset},
1588                             false,
1589                             al,
1590                             "al r0 r13 minus r10 LSR 11 Offset",
1591                             "al_r0_r13_minus_r10_LSR_11_Offset"},
1592                            {{al, r0, r9, minus, r0, LSR, 15, Offset},
1593                             false,
1594                             al,
1595                             "al r0 r9 minus r0 LSR 15 Offset",
1596                             "al_r0_r9_minus_r0_LSR_15_Offset"},
1597                            {{al, r0, r3, plus, r5, ASR, 23, Offset},
1598                             false,
1599                             al,
1600                             "al r0 r3 plus r5 ASR 23 Offset",
1601                             "al_r0_r3_plus_r5_ASR_23_Offset"},
1602                            {{al, r8, r0, plus, r1, ASR, 3, PreIndex},
1603                             false,
1604                             al,
1605                             "al r8 r0 plus r1 ASR 3 PreIndex",
1606                             "al_r8_r0_plus_r1_ASR_3_PreIndex"},
1607                            {{al, r0, r14, minus, r6, ASR, 27, PreIndex},
1608                             false,
1609                             al,
1610                             "al r0 r14 minus r6 ASR 27 PreIndex",
1611                             "al_r0_r14_minus_r6_ASR_27_PreIndex"},
1612                            {{al, r12, r11, minus, r8, LSR, 2, PostIndex},
1613                             false,
1614                             al,
1615                             "al r12 r11 minus r8 LSR 2 PostIndex",
1616                             "al_r12_r11_minus_r8_LSR_2_PostIndex"},
1617                            {{al, r9, r3, plus, r10, ASR, 28, PostIndex},
1618                             false,
1619                             al,
1620                             "al r9 r3 plus r10 ASR 28 PostIndex",
1621                             "al_r9_r3_plus_r10_ASR_28_PostIndex"},
1622                            {{al, r2, r5, plus, r6, ASR, 7, PreIndex},
1623                             false,
1624                             al,
1625                             "al r2 r5 plus r6 ASR 7 PreIndex",
1626                             "al_r2_r5_plus_r6_ASR_7_PreIndex"},
1627                            {{al, r14, r11, minus, r2, ASR, 2, PostIndex},
1628                             false,
1629                             al,
1630                             "al r14 r11 minus r2 ASR 2 PostIndex",
1631                             "al_r14_r11_minus_r2_ASR_2_PostIndex"},
1632                            {{al, r0, r11, minus, r1, ASR, 13, PreIndex},
1633                             false,
1634                             al,
1635                             "al r0 r11 minus r1 ASR 13 PreIndex",
1636                             "al_r0_r11_minus_r1_ASR_13_PreIndex"},
1637                            {{al, r13, r12, plus, r6, LSR, 16, PreIndex},
1638                             false,
1639                             al,
1640                             "al r13 r12 plus r6 LSR 16 PreIndex",
1641                             "al_r13_r12_plus_r6_LSR_16_PreIndex"},
1642                            {{al, r10, r2, plus, r10, LSR, 31, PreIndex},
1643                             false,
1644                             al,
1645                             "al r10 r2 plus r10 LSR 31 PreIndex",
1646                             "al_r10_r2_plus_r10_LSR_31_PreIndex"},
1647                            {{al, r14, r11, plus, r14, LSR, 9, PreIndex},
1648                             false,
1649                             al,
1650                             "al r14 r11 plus r14 LSR 9 PreIndex",
1651                             "al_r14_r11_plus_r14_LSR_9_PreIndex"},
1652                            {{al, r0, r2, minus, r12, LSR, 9, PreIndex},
1653                             false,
1654                             al,
1655                             "al r0 r2 minus r12 LSR 9 PreIndex",
1656                             "al_r0_r2_minus_r12_LSR_9_PreIndex"},
1657                            {{al, r0, r13, minus, r4, ASR, 26, PostIndex},
1658                             false,
1659                             al,
1660                             "al r0 r13 minus r4 ASR 26 PostIndex",
1661                             "al_r0_r13_minus_r4_ASR_26_PostIndex"},
1662                            {{al, r7, r14, minus, r5, ASR, 21, PreIndex},
1663                             false,
1664                             al,
1665                             "al r7 r14 minus r5 ASR 21 PreIndex",
1666                             "al_r7_r14_minus_r5_ASR_21_PreIndex"},
1667                            {{al, r0, r4, minus, r8, ASR, 21, PostIndex},
1668                             false,
1669                             al,
1670                             "al r0 r4 minus r8 ASR 21 PostIndex",
1671                             "al_r0_r4_minus_r8_ASR_21_PostIndex"},
1672                            {{al, r11, r6, plus, r2, LSR, 31, PostIndex},
1673                             false,
1674                             al,
1675                             "al r11 r6 plus r2 LSR 31 PostIndex",
1676                             "al_r11_r6_plus_r2_LSR_31_PostIndex"},
1677                            {{al, r2, r9, minus, r2, LSR, 29, PostIndex},
1678                             false,
1679                             al,
1680                             "al r2 r9 minus r2 LSR 29 PostIndex",
1681                             "al_r2_r9_minus_r2_LSR_29_PostIndex"},
1682                            {{al, r3, r4, minus, r9, LSR, 8, PreIndex},
1683                             false,
1684                             al,
1685                             "al r3 r4 minus r9 LSR 8 PreIndex",
1686                             "al_r3_r4_minus_r9_LSR_8_PreIndex"},
1687                            {{al, r8, r14, plus, r11, LSR, 32, PreIndex},
1688                             false,
1689                             al,
1690                             "al r8 r14 plus r11 LSR 32 PreIndex",
1691                             "al_r8_r14_plus_r11_LSR_32_PreIndex"},
1692                            {{al, r11, r0, plus, r4, ASR, 18, PostIndex},
1693                             false,
1694                             al,
1695                             "al r11 r0 plus r4 ASR 18 PostIndex",
1696                             "al_r11_r0_plus_r4_ASR_18_PostIndex"},
1697                            {{al, r4, r7, plus, r2, ASR, 30, PreIndex},
1698                             false,
1699                             al,
1700                             "al r4 r7 plus r2 ASR 30 PreIndex",
1701                             "al_r4_r7_plus_r2_ASR_30_PreIndex"},
1702                            {{al, r8, r6, minus, r2, LSR, 30, PreIndex},
1703                             false,
1704                             al,
1705                             "al r8 r6 minus r2 LSR 30 PreIndex",
1706                             "al_r8_r6_minus_r2_LSR_30_PreIndex"},
1707                            {{al, r4, r5, minus, r0, ASR, 20, PreIndex},
1708                             false,
1709                             al,
1710                             "al r4 r5 minus r0 ASR 20 PreIndex",
1711                             "al_r4_r5_minus_r0_ASR_20_PreIndex"},
1712                            {{al, r5, r11, minus, r11, LSR, 30, PostIndex},
1713                             false,
1714                             al,
1715                             "al r5 r11 minus r11 LSR 30 PostIndex",
1716                             "al_r5_r11_minus_r11_LSR_30_PostIndex"},
1717                            {{al, r12, r4, minus, r7, ASR, 13, PreIndex},
1718                             false,
1719                             al,
1720                             "al r12 r4 minus r7 ASR 13 PreIndex",
1721                             "al_r12_r4_minus_r7_ASR_13_PreIndex"},
1722                            {{al, r5, r12, minus, r1, ASR, 16, PreIndex},
1723                             false,
1724                             al,
1725                             "al r5 r12 minus r1 ASR 16 PreIndex",
1726                             "al_r5_r12_minus_r1_ASR_16_PreIndex"},
1727                            {{al, r8, r3, minus, r0, LSR, 10, PostIndex},
1728                             false,
1729                             al,
1730                             "al r8 r3 minus r0 LSR 10 PostIndex",
1731                             "al_r8_r3_minus_r0_LSR_10_PostIndex"},
1732                            {{al, r2, r11, plus, r5, LSR, 12, PreIndex},
1733                             false,
1734                             al,
1735                             "al r2 r11 plus r5 LSR 12 PreIndex",
1736                             "al_r2_r11_plus_r5_LSR_12_PreIndex"},
1737                            {{al, r6, r2, minus, r4, ASR, 16, PreIndex},
1738                             false,
1739                             al,
1740                             "al r6 r2 minus r4 ASR 16 PreIndex",
1741                             "al_r6_r2_minus_r4_ASR_16_PreIndex"},
1742                            {{al, r10, r2, minus, r0, LSR, 20, PreIndex},
1743                             false,
1744                             al,
1745                             "al r10 r2 minus r0 LSR 20 PreIndex",
1746                             "al_r10_r2_minus_r0_LSR_20_PreIndex"},
1747                            {{al, r6, r11, minus, r13, ASR, 30, PostIndex},
1748                             false,
1749                             al,
1750                             "al r6 r11 minus r13 ASR 30 PostIndex",
1751                             "al_r6_r11_minus_r13_ASR_30_PostIndex"},
1752                            {{al, r11, r8, minus, r10, ASR, 9, PostIndex},
1753                             false,
1754                             al,
1755                             "al r11 r8 minus r10 ASR 9 PostIndex",
1756                             "al_r11_r8_minus_r10_ASR_9_PostIndex"},
1757                            {{al, r2, r3, plus, r12, LSR, 22, PostIndex},
1758                             false,
1759                             al,
1760                             "al r2 r3 plus r12 LSR 22 PostIndex",
1761                             "al_r2_r3_plus_r12_LSR_22_PostIndex"},
1762                            {{al, r1, r6, minus, r5, ASR, 15, PostIndex},
1763                             false,
1764                             al,
1765                             "al r1 r6 minus r5 ASR 15 PostIndex",
1766                             "al_r1_r6_minus_r5_ASR_15_PostIndex"},
1767                            {{al, r8, r5, minus, r5, ASR, 10, PreIndex},
1768                             false,
1769                             al,
1770                             "al r8 r5 minus r5 ASR 10 PreIndex",
1771                             "al_r8_r5_minus_r5_ASR_10_PreIndex"},
1772                            {{al, r2, r1, minus, r14, LSR, 26, PostIndex},
1773                             false,
1774                             al,
1775                             "al r2 r1 minus r14 LSR 26 PostIndex",
1776                             "al_r2_r1_minus_r14_LSR_26_PostIndex"},
1777                            {{al, r7, r12, minus, r3, LSR, 16, PostIndex},
1778                             false,
1779                             al,
1780                             "al r7 r12 minus r3 LSR 16 PostIndex",
1781                             "al_r7_r12_minus_r3_LSR_16_PostIndex"},
1782                            {{al, r8, r5, minus, r12, ASR, 24, PreIndex},
1783                             false,
1784                             al,
1785                             "al r8 r5 minus r12 ASR 24 PreIndex",
1786                             "al_r8_r5_minus_r12_ASR_24_PreIndex"},
1787                            {{al, r8, r4, plus, r0, ASR, 23, PreIndex},
1788                             false,
1789                             al,
1790                             "al r8 r4 plus r0 ASR 23 PreIndex",
1791                             "al_r8_r4_plus_r0_ASR_23_PreIndex"},
1792                            {{al, r2, r0, minus, r14, ASR, 31, PostIndex},
1793                             false,
1794                             al,
1795                             "al r2 r0 minus r14 ASR 31 PostIndex",
1796                             "al_r2_r0_minus_r14_ASR_31_PostIndex"},
1797                            {{al, r6, r13, minus, r8, LSR, 30, PostIndex},
1798                             false,
1799                             al,
1800                             "al r6 r13 minus r8 LSR 30 PostIndex",
1801                             "al_r6_r13_minus_r8_LSR_30_PostIndex"},
1802                            {{al, r3, r6, minus, r4, LSR, 22, PostIndex},
1803                             false,
1804                             al,
1805                             "al r3 r6 minus r4 LSR 22 PostIndex",
1806                             "al_r3_r6_minus_r4_LSR_22_PostIndex"},
1807                            {{al, r12, r8, plus, r9, ASR, 32, PreIndex},
1808                             false,
1809                             al,
1810                             "al r12 r8 plus r9 ASR 32 PreIndex",
1811                             "al_r12_r8_plus_r9_ASR_32_PreIndex"},
1812                            {{al, r2, r4, plus, r4, ASR, 13, PreIndex},
1813                             false,
1814                             al,
1815                             "al r2 r4 plus r4 ASR 13 PreIndex",
1816                             "al_r2_r4_plus_r4_ASR_13_PreIndex"},
1817                            {{al, r3, r13, plus, r7, ASR, 12, PreIndex},
1818                             false,
1819                             al,
1820                             "al r3 r13 plus r7 ASR 12 PreIndex",
1821                             "al_r3_r13_plus_r7_ASR_12_PreIndex"},
1822                            {{al, r11, r1, minus, r14, LSR, 14, PostIndex},
1823                             false,
1824                             al,
1825                             "al r11 r1 minus r14 LSR 14 PostIndex",
1826                             "al_r11_r1_minus_r14_LSR_14_PostIndex"},
1827                            {{al, r12, r9, plus, r5, ASR, 27, PostIndex},
1828                             false,
1829                             al,
1830                             "al r12 r9 plus r5 ASR 27 PostIndex",
1831                             "al_r12_r9_plus_r5_ASR_27_PostIndex"},
1832                            {{al, r1, r3, plus, r11, ASR, 31, PreIndex},
1833                             false,
1834                             al,
1835                             "al r1 r3 plus r11 ASR 31 PreIndex",
1836                             "al_r1_r3_plus_r11_ASR_31_PreIndex"},
1837                            {{al, r10, r2, plus, r2, ASR, 26, PostIndex},
1838                             false,
1839                             al,
1840                             "al r10 r2 plus r2 ASR 26 PostIndex",
1841                             "al_r10_r2_plus_r2_ASR_26_PostIndex"},
1842                            {{al, r0, r7, plus, r5, LSR, 19, PreIndex},
1843                             false,
1844                             al,
1845                             "al r0 r7 plus r5 LSR 19 PreIndex",
1846                             "al_r0_r7_plus_r5_LSR_19_PreIndex"},
1847                            {{al, r12, r7, plus, r5, LSR, 27, PreIndex},
1848                             false,
1849                             al,
1850                             "al r12 r7 plus r5 LSR 27 PreIndex",
1851                             "al_r12_r7_plus_r5_LSR_27_PreIndex"},
1852                            {{al, r10, r11, plus, r11, LSR, 9, PostIndex},
1853                             false,
1854                             al,
1855                             "al r10 r11 plus r11 LSR 9 PostIndex",
1856                             "al_r10_r11_plus_r11_LSR_9_PostIndex"},
1857                            {{al, r2, r14, plus, r13, ASR, 24, PreIndex},
1858                             false,
1859                             al,
1860                             "al r2 r14 plus r13 ASR 24 PreIndex",
1861                             "al_r2_r14_plus_r13_ASR_24_PreIndex"},
1862                            {{al, r13, r0, minus, r1, LSR, 20, PreIndex},
1863                             false,
1864                             al,
1865                             "al r13 r0 minus r1 LSR 20 PreIndex",
1866                             "al_r13_r0_minus_r1_LSR_20_PreIndex"},
1867                            {{al, r2, r4, minus, r8, LSR, 26, PostIndex},
1868                             false,
1869                             al,
1870                             "al r2 r4 minus r8 LSR 26 PostIndex",
1871                             "al_r2_r4_minus_r8_LSR_26_PostIndex"},
1872                            {{al, r10, r13, minus, r8, ASR, 14, PostIndex},
1873                             false,
1874                             al,
1875                             "al r10 r13 minus r8 ASR 14 PostIndex",
1876                             "al_r10_r13_minus_r8_ASR_14_PostIndex"},
1877                            {{al, r6, r0, plus, r7, ASR, 8, PostIndex},
1878                             false,
1879                             al,
1880                             "al r6 r0 plus r7 ASR 8 PostIndex",
1881                             "al_r6_r0_plus_r7_ASR_8_PostIndex"},
1882                            {{al, r3, r9, plus, r6, ASR, 18, PreIndex},
1883                             false,
1884                             al,
1885                             "al r3 r9 plus r6 ASR 18 PreIndex",
1886                             "al_r3_r9_plus_r6_ASR_18_PreIndex"},
1887                            {{al, r4, r1, minus, r0, ASR, 2, PreIndex},
1888                             false,
1889                             al,
1890                             "al r4 r1 minus r0 ASR 2 PreIndex",
1891                             "al_r4_r1_minus_r0_ASR_2_PreIndex"},
1892                            {{al, r4, r11, plus, r11, ASR, 7, PostIndex},
1893                             false,
1894                             al,
1895                             "al r4 r11 plus r11 ASR 7 PostIndex",
1896                             "al_r4_r11_plus_r11_ASR_7_PostIndex"},
1897                            {{al, r14, r9, minus, r11, ASR, 3, PostIndex},
1898                             false,
1899                             al,
1900                             "al r14 r9 minus r11 ASR 3 PostIndex",
1901                             "al_r14_r9_minus_r11_ASR_3_PostIndex"},
1902                            {{al, r2, r11, minus, r8, ASR, 31, PostIndex},
1903                             false,
1904                             al,
1905                             "al r2 r11 minus r8 ASR 31 PostIndex",
1906                             "al_r2_r11_minus_r8_ASR_31_PostIndex"},
1907                            {{al, r11, r4, plus, r4, ASR, 31, PreIndex},
1908                             false,
1909                             al,
1910                             "al r11 r4 plus r4 ASR 31 PreIndex",
1911                             "al_r11_r4_plus_r4_ASR_31_PreIndex"},
1912                            {{al, r10, r2, plus, r4, LSR, 20, PostIndex},
1913                             false,
1914                             al,
1915                             "al r10 r2 plus r4 LSR 20 PostIndex",
1916                             "al_r10_r2_plus_r4_LSR_20_PostIndex"},
1917                            {{al, r3, r13, minus, r11, LSR, 2, PreIndex},
1918                             false,
1919                             al,
1920                             "al r3 r13 minus r11 LSR 2 PreIndex",
1921                             "al_r3_r13_minus_r11_LSR_2_PreIndex"},
1922                            {{al, r14, r2, minus, r5, LSR, 21, PreIndex},
1923                             false,
1924                             al,
1925                             "al r14 r2 minus r5 LSR 21 PreIndex",
1926                             "al_r14_r2_minus_r5_LSR_21_PreIndex"},
1927                            {{al, r8, r5, minus, r0, LSR, 21, PostIndex},
1928                             false,
1929                             al,
1930                             "al r8 r5 minus r0 LSR 21 PostIndex",
1931                             "al_r8_r5_minus_r0_LSR_21_PostIndex"},
1932                            {{al, r9, r10, plus, r3, LSR, 10, PostIndex},
1933                             false,
1934                             al,
1935                             "al r9 r10 plus r3 LSR 10 PostIndex",
1936                             "al_r9_r10_plus_r3_LSR_10_PostIndex"},
1937                            {{al, r12, r11, plus, r12, LSR, 27, PostIndex},
1938                             false,
1939                             al,
1940                             "al r12 r11 plus r12 LSR 27 PostIndex",
1941                             "al_r12_r11_plus_r12_LSR_27_PostIndex"},
1942                            {{al, r9, r8, minus, r8, ASR, 28, PreIndex},
1943                             false,
1944                             al,
1945                             "al r9 r8 minus r8 ASR 28 PreIndex",
1946                             "al_r9_r8_minus_r8_ASR_28_PreIndex"},
1947                            {{al, r5, r7, minus, r5, LSR, 17, PreIndex},
1948                             false,
1949                             al,
1950                             "al r5 r7 minus r5 LSR 17 PreIndex",
1951                             "al_r5_r7_minus_r5_LSR_17_PreIndex"},
1952                            {{al, r7, r2, minus, r3, ASR, 21, PreIndex},
1953                             false,
1954                             al,
1955                             "al r7 r2 minus r3 ASR 21 PreIndex",
1956                             "al_r7_r2_minus_r3_ASR_21_PreIndex"},
1957                            {{al, r7, r12, minus, r1, ASR, 26, PreIndex},
1958                             false,
1959                             al,
1960                             "al r7 r12 minus r1 ASR 26 PreIndex",
1961                             "al_r7_r12_minus_r1_ASR_26_PreIndex"},
1962                            {{al, r14, r5, plus, r8, ASR, 14, PreIndex},
1963                             false,
1964                             al,
1965                             "al r14 r5 plus r8 ASR 14 PreIndex",
1966                             "al_r14_r5_plus_r8_ASR_14_PreIndex"},
1967                            {{al, r13, r14, minus, r10, LSR, 28, PostIndex},
1968                             false,
1969                             al,
1970                             "al r13 r14 minus r10 LSR 28 PostIndex",
1971                             "al_r13_r14_minus_r10_LSR_28_PostIndex"},
1972                            {{al, r12, r8, plus, r10, ASR, 11, PreIndex},
1973                             false,
1974                             al,
1975                             "al r12 r8 plus r10 ASR 11 PreIndex",
1976                             "al_r12_r8_plus_r10_ASR_11_PreIndex"},
1977                            {{al, r1, r7, plus, r12, ASR, 6, PostIndex},
1978                             false,
1979                             al,
1980                             "al r1 r7 plus r12 ASR 6 PostIndex",
1981                             "al_r1_r7_plus_r12_ASR_6_PostIndex"},
1982                            {{al, r11, r3, plus, r3, LSR, 17, PreIndex},
1983                             false,
1984                             al,
1985                             "al r11 r3 plus r3 LSR 17 PreIndex",
1986                             "al_r11_r3_plus_r3_LSR_17_PreIndex"},
1987                            {{al, r12, r4, minus, r5, ASR, 8, PostIndex},
1988                             false,
1989                             al,
1990                             "al r12 r4 minus r5 ASR 8 PostIndex",
1991                             "al_r12_r4_minus_r5_ASR_8_PostIndex"},
1992                            {{al, r2, r5, plus, r13, LSR, 11, PostIndex},
1993                             false,
1994                             al,
1995                             "al r2 r5 plus r13 LSR 11 PostIndex",
1996                             "al_r2_r5_plus_r13_LSR_11_PostIndex"},
1997                            {{al, r3, r4, minus, r12, ASR, 13, PostIndex},
1998                             false,
1999                             al,
2000                             "al r3 r4 minus r12 ASR 13 PostIndex",
2001                             "al_r3_r4_minus_r12_ASR_13_PostIndex"},
2002                            {{al, r1, r0, plus, r7, ASR, 6, PreIndex},
2003                             false,
2004                             al,
2005                             "al r1 r0 plus r7 ASR 6 PreIndex",
2006                             "al_r1_r0_plus_r7_ASR_6_PreIndex"},
2007                            {{al, r5, r9, minus, r1, ASR, 29, PostIndex},
2008                             false,
2009                             al,
2010                             "al r5 r9 minus r1 ASR 29 PostIndex",
2011                             "al_r5_r9_minus_r1_ASR_29_PostIndex"},
2012                            {{al, r13, r11, plus, r1, ASR, 17, PostIndex},
2013                             false,
2014                             al,
2015                             "al r13 r11 plus r1 ASR 17 PostIndex",
2016                             "al_r13_r11_plus_r1_ASR_17_PostIndex"},
2017                            {{al, r8, r10, minus, r12, ASR, 26, PostIndex},
2018                             false,
2019                             al,
2020                             "al r8 r10 minus r12 ASR 26 PostIndex",
2021                             "al_r8_r10_minus_r12_ASR_26_PostIndex"},
2022                            {{al, r7, r8, minus, r5, LSR, 18, PreIndex},
2023                             false,
2024                             al,
2025                             "al r7 r8 minus r5 LSR 18 PreIndex",
2026                             "al_r7_r8_minus_r5_LSR_18_PreIndex"},
2027                            {{al, r9, r8, plus, r2, LSR, 14, PreIndex},
2028                             false,
2029                             al,
2030                             "al r9 r8 plus r2 LSR 14 PreIndex",
2031                             "al_r9_r8_plus_r2_LSR_14_PreIndex"},
2032                            {{al, r5, r0, plus, r2, ASR, 32, PostIndex},
2033                             false,
2034                             al,
2035                             "al r5 r0 plus r2 ASR 32 PostIndex",
2036                             "al_r5_r0_plus_r2_ASR_32_PostIndex"},
2037                            {{al, r13, r2, minus, r3, ASR, 11, PreIndex},
2038                             false,
2039                             al,
2040                             "al r13 r2 minus r3 ASR 11 PreIndex",
2041                             "al_r13_r2_minus_r3_ASR_11_PreIndex"},
2042                            {{al, r1, r12, plus, r10, ASR, 18, PostIndex},
2043                             false,
2044                             al,
2045                             "al r1 r12 plus r10 ASR 18 PostIndex",
2046                             "al_r1_r12_plus_r10_ASR_18_PostIndex"},
2047                            {{al, r5, r12, minus, r2, LSR, 19, PostIndex},
2048                             false,
2049                             al,
2050                             "al r5 r12 minus r2 LSR 19 PostIndex",
2051                             "al_r5_r12_minus_r2_LSR_19_PostIndex"},
2052                            {{al, r7, r0, minus, r1, LSR, 9, PreIndex},
2053                             false,
2054                             al,
2055                             "al r7 r0 minus r1 LSR 9 PreIndex",
2056                             "al_r7_r0_minus_r1_LSR_9_PreIndex"},
2057                            {{al, r5, r8, plus, r11, ASR, 13, PostIndex},
2058                             false,
2059                             al,
2060                             "al r5 r8 plus r11 ASR 13 PostIndex",
2061                             "al_r5_r8_plus_r11_ASR_13_PostIndex"},
2062                            {{al, r7, r0, minus, r8, LSR, 24, PreIndex},
2063                             false,
2064                             al,
2065                             "al r7 r0 minus r8 LSR 24 PreIndex",
2066                             "al_r7_r0_minus_r8_LSR_24_PreIndex"},
2067                            {{al, r4, r3, plus, r5, ASR, 24, PreIndex},
2068                             false,
2069                             al,
2070                             "al r4 r3 plus r5 ASR 24 PreIndex",
2071                             "al_r4_r3_plus_r5_ASR_24_PreIndex"},
2072                            {{al, r7, r9, minus, r6, LSR, 23, PreIndex},
2073                             false,
2074                             al,
2075                             "al r7 r9 minus r6 LSR 23 PreIndex",
2076                             "al_r7_r9_minus_r6_LSR_23_PreIndex"},
2077                            {{al, r2, r4, plus, r0, LSR, 30, PreIndex},
2078                             false,
2079                             al,
2080                             "al r2 r4 plus r0 LSR 30 PreIndex",
2081                             "al_r2_r4_plus_r0_LSR_30_PreIndex"},
2082                            {{al, r10, r6, plus, r13, LSR, 26, PreIndex},
2083                             false,
2084                             al,
2085                             "al r10 r6 plus r13 LSR 26 PreIndex",
2086                             "al_r10_r6_plus_r13_LSR_26_PreIndex"},
2087                            {{al, r4, r8, minus, r9, ASR, 17, PreIndex},
2088                             false,
2089                             al,
2090                             "al r4 r8 minus r9 ASR 17 PreIndex",
2091                             "al_r4_r8_minus_r9_ASR_17_PreIndex"},
2092                            {{al, r4, r9, plus, r9, ASR, 30, PreIndex},
2093                             false,
2094                             al,
2095                             "al r4 r9 plus r9 ASR 30 PreIndex",
2096                             "al_r4_r9_plus_r9_ASR_30_PreIndex"},
2097                            {{al, r1, r5, plus, r13, LSR, 20, PostIndex},
2098                             false,
2099                             al,
2100                             "al r1 r5 plus r13 LSR 20 PostIndex",
2101                             "al_r1_r5_plus_r13_LSR_20_PostIndex"},
2102                            {{al, r8, r6, minus, r1, LSR, 29, PreIndex},
2103                             false,
2104                             al,
2105                             "al r8 r6 minus r1 LSR 29 PreIndex",
2106                             "al_r8_r6_minus_r1_LSR_29_PreIndex"},
2107                            {{al, r12, r3, plus, r6, ASR, 29, PostIndex},
2108                             false,
2109                             al,
2110                             "al r12 r3 plus r6 ASR 29 PostIndex",
2111                             "al_r12_r3_plus_r6_ASR_29_PostIndex"},
2112                            {{al, r13, r5, plus, r0, LSR, 13, PreIndex},
2113                             false,
2114                             al,
2115                             "al r13 r5 plus r0 LSR 13 PreIndex",
2116                             "al_r13_r5_plus_r0_LSR_13_PreIndex"},
2117                            {{al, r5, r1, plus, r0, ASR, 26, PreIndex},
2118                             false,
2119                             al,
2120                             "al r5 r1 plus r0 ASR 26 PreIndex",
2121                             "al_r5_r1_plus_r0_ASR_26_PreIndex"},
2122                            {{al, r6, r7, plus, r8, ASR, 26, PreIndex},
2123                             false,
2124                             al,
2125                             "al r6 r7 plus r8 ASR 26 PreIndex",
2126                             "al_r6_r7_plus_r8_ASR_26_PreIndex"},
2127                            {{al, r5, r14, plus, r8, ASR, 8, PostIndex},
2128                             false,
2129                             al,
2130                             "al r5 r14 plus r8 ASR 8 PostIndex",
2131                             "al_r5_r14_plus_r8_ASR_8_PostIndex"},
2132                            {{al, r9, r14, plus, r6, LSR, 23, PreIndex},
2133                             false,
2134                             al,
2135                             "al r9 r14 plus r6 LSR 23 PreIndex",
2136                             "al_r9_r14_plus_r6_LSR_23_PreIndex"},
2137                            {{al, r6, r4, plus, r3, ASR, 9, PreIndex},
2138                             false,
2139                             al,
2140                             "al r6 r4 plus r3 ASR 9 PreIndex",
2141                             "al_r6_r4_plus_r3_ASR_9_PreIndex"},
2142                            {{al, r8, r7, minus, r11, ASR, 29, PreIndex},
2143                             false,
2144                             al,
2145                             "al r8 r7 minus r11 ASR 29 PreIndex",
2146                             "al_r8_r7_minus_r11_ASR_29_PreIndex"},
2147                            {{al, r9, r3, plus, r0, ASR, 5, PostIndex},
2148                             false,
2149                             al,
2150                             "al r9 r3 plus r0 ASR 5 PostIndex",
2151                             "al_r9_r3_plus_r0_ASR_5_PostIndex"},
2152                            {{al, r8, r6, plus, r5, LSR, 4, PreIndex},
2153                             false,
2154                             al,
2155                             "al r8 r6 plus r5 LSR 4 PreIndex",
2156                             "al_r8_r6_plus_r5_LSR_4_PreIndex"},
2157                            {{al, r9, r8, plus, r7, ASR, 4, PostIndex},
2158                             false,
2159                             al,
2160                             "al r9 r8 plus r7 ASR 4 PostIndex",
2161                             "al_r9_r8_plus_r7_ASR_4_PostIndex"},
2162                            {{al, r12, r4, plus, r6, ASR, 28, PostIndex},
2163                             false,
2164                             al,
2165                             "al r12 r4 plus r6 ASR 28 PostIndex",
2166                             "al_r12_r4_plus_r6_ASR_28_PostIndex"},
2167                            {{al, r4, r7, minus, r4, ASR, 25, PreIndex},
2168                             false,
2169                             al,
2170                             "al r4 r7 minus r4 ASR 25 PreIndex",
2171                             "al_r4_r7_minus_r4_ASR_25_PreIndex"},
2172                            {{al, r1, r4, minus, r7, ASR, 5, PostIndex},
2173                             false,
2174                             al,
2175                             "al r1 r4 minus r7 ASR 5 PostIndex",
2176                             "al_r1_r4_minus_r7_ASR_5_PostIndex"},
2177                            {{al, r3, r1, plus, r12, LSR, 25, PostIndex},
2178                             false,
2179                             al,
2180                             "al r3 r1 plus r12 LSR 25 PostIndex",
2181                             "al_r3_r1_plus_r12_LSR_25_PostIndex"},
2182                            {{al, r13, r8, plus, r14, ASR, 32, PreIndex},
2183                             false,
2184                             al,
2185                             "al r13 r8 plus r14 ASR 32 PreIndex",
2186                             "al_r13_r8_plus_r14_ASR_32_PreIndex"},
2187                            {{al, r1, r3, minus, r1, LSR, 7, PostIndex},
2188                             false,
2189                             al,
2190                             "al r1 r3 minus r1 LSR 7 PostIndex",
2191                             "al_r1_r3_minus_r1_LSR_7_PostIndex"},
2192                            {{al, r13, r3, minus, r4, ASR, 21, PostIndex},
2193                             false,
2194                             al,
2195                             "al r13 r3 minus r4 ASR 21 PostIndex",
2196                             "al_r13_r3_minus_r4_ASR_21_PostIndex"},
2197                            {{al, r11, r8, plus, r10, LSR, 7, PostIndex},
2198                             false,
2199                             al,
2200                             "al r11 r8 plus r10 LSR 7 PostIndex",
2201                             "al_r11_r8_plus_r10_LSR_7_PostIndex"},
2202                            {{al, r10, r0, minus, r0, LSR, 24, PreIndex},
2203                             false,
2204                             al,
2205                             "al r10 r0 minus r0 LSR 24 PreIndex",
2206                             "al_r10_r0_minus_r0_LSR_24_PreIndex"},
2207                            {{al, r12, r11, plus, r2, LSR, 7, PreIndex},
2208                             false,
2209                             al,
2210                             "al r12 r11 plus r2 LSR 7 PreIndex",
2211                             "al_r12_r11_plus_r2_LSR_7_PreIndex"},
2212                            {{al, r11, r10, minus, r6, ASR, 2, PostIndex},
2213                             false,
2214                             al,
2215                             "al r11 r10 minus r6 ASR 2 PostIndex",
2216                             "al_r11_r10_minus_r6_ASR_2_PostIndex"},
2217                            {{al, r5, r10, minus, r10, ASR, 19, PostIndex},
2218                             false,
2219                             al,
2220                             "al r5 r10 minus r10 ASR 19 PostIndex",
2221                             "al_r5_r10_minus_r10_ASR_19_PostIndex"},
2222                            {{al, r13, r8, minus, r6, ASR, 30, PreIndex},
2223                             false,
2224                             al,
2225                             "al r13 r8 minus r6 ASR 30 PreIndex",
2226                             "al_r13_r8_minus_r6_ASR_30_PreIndex"},
2227                            {{al, r1, r10, plus, r0, ASR, 18, PreIndex},
2228                             false,
2229                             al,
2230                             "al r1 r10 plus r0 ASR 18 PreIndex",
2231                             "al_r1_r10_plus_r0_ASR_18_PreIndex"},
2232                            {{al, r10, r14, plus, r5, ASR, 8, PostIndex},
2233                             false,
2234                             al,
2235                             "al r10 r14 plus r5 ASR 8 PostIndex",
2236                             "al_r10_r14_plus_r5_ASR_8_PostIndex"},
2237                            {{al, r1, r3, minus, r10, LSR, 11, PreIndex},
2238                             false,
2239                             al,
2240                             "al r1 r3 minus r10 LSR 11 PreIndex",
2241                             "al_r1_r3_minus_r10_LSR_11_PreIndex"},
2242                            {{al, r11, r13, minus, r11, LSR, 5, PreIndex},
2243                             false,
2244                             al,
2245                             "al r11 r13 minus r11 LSR 5 PreIndex",
2246                             "al_r11_r13_minus_r11_LSR_5_PreIndex"},
2247                            {{al, r4, r9, plus, r12, LSR, 28, PostIndex},
2248                             false,
2249                             al,
2250                             "al r4 r9 plus r12 LSR 28 PostIndex",
2251                             "al_r4_r9_plus_r12_LSR_28_PostIndex"},
2252                            {{al, r3, r8, plus, r12, LSR, 14, PostIndex},
2253                             false,
2254                             al,
2255                             "al r3 r8 plus r12 LSR 14 PostIndex",
2256                             "al_r3_r8_plus_r12_LSR_14_PostIndex"},
2257                            {{al, r11, r7, minus, r2, ASR, 3, PostIndex},
2258                             false,
2259                             al,
2260                             "al r11 r7 minus r2 ASR 3 PostIndex",
2261                             "al_r11_r7_minus_r2_ASR_3_PostIndex"},
2262                            {{al, r0, r8, plus, r7, ASR, 20, PostIndex},
2263                             false,
2264                             al,
2265                             "al r0 r8 plus r7 ASR 20 PostIndex",
2266                             "al_r0_r8_plus_r7_ASR_20_PostIndex"},
2267                            {{al, r8, r1, minus, r2, LSR, 15, PreIndex},
2268                             false,
2269                             al,
2270                             "al r8 r1 minus r2 LSR 15 PreIndex",
2271                             "al_r8_r1_minus_r2_LSR_15_PreIndex"},
2272                            {{al, r9, r5, plus, r7, LSR, 14, PostIndex},
2273                             false,
2274                             al,
2275                             "al r9 r5 plus r7 LSR 14 PostIndex",
2276                             "al_r9_r5_plus_r7_LSR_14_PostIndex"},
2277                            {{al, r1, r8, minus, r13, LSR, 12, PostIndex},
2278                             false,
2279                             al,
2280                             "al r1 r8 minus r13 LSR 12 PostIndex",
2281                             "al_r1_r8_minus_r13_LSR_12_PostIndex"},
2282                            {{al, r8, r0, plus, r12, LSR, 22, PreIndex},
2283                             false,
2284                             al,
2285                             "al r8 r0 plus r12 LSR 22 PreIndex",
2286                             "al_r8_r0_plus_r12_LSR_22_PreIndex"},
2287                            {{al, r13, r0, minus, r10, ASR, 26, PostIndex},
2288                             false,
2289                             al,
2290                             "al r13 r0 minus r10 ASR 26 PostIndex",
2291                             "al_r13_r0_minus_r10_ASR_26_PostIndex"},
2292                            {{al, r12, r3, minus, r3, LSR, 11, PreIndex},
2293                             false,
2294                             al,
2295                             "al r12 r3 minus r3 LSR 11 PreIndex",
2296                             "al_r12_r3_minus_r3_LSR_11_PreIndex"},
2297                            {{al, r7, r3, minus, r8, LSR, 25, PostIndex},
2298                             false,
2299                             al,
2300                             "al r7 r3 minus r8 LSR 25 PostIndex",
2301                             "al_r7_r3_minus_r8_LSR_25_PostIndex"},
2302                            {{al, r5, r4, plus, r5, ASR, 2, PreIndex},
2303                             false,
2304                             al,
2305                             "al r5 r4 plus r5 ASR 2 PreIndex",
2306                             "al_r5_r4_plus_r5_ASR_2_PreIndex"},
2307                            {{al, r3, r10, plus, r1, ASR, 22, PostIndex},
2308                             false,
2309                             al,
2310                             "al r3 r10 plus r1 ASR 22 PostIndex",
2311                             "al_r3_r10_plus_r1_ASR_22_PostIndex"},
2312                            {{al, r6, r11, minus, r7, LSR, 4, PostIndex},
2313                             false,
2314                             al,
2315                             "al r6 r11 minus r7 LSR 4 PostIndex",
2316                             "al_r6_r11_minus_r7_LSR_4_PostIndex"},
2317                            {{al, r13, r7, minus, r3, ASR, 28, PreIndex},
2318                             false,
2319                             al,
2320                             "al r13 r7 minus r3 ASR 28 PreIndex",
2321                             "al_r13_r7_minus_r3_ASR_28_PreIndex"},
2322                            {{al, r3, r10, minus, r4, LSR, 5, PreIndex},
2323                             false,
2324                             al,
2325                             "al r3 r10 minus r4 LSR 5 PreIndex",
2326                             "al_r3_r10_minus_r4_LSR_5_PreIndex"},
2327                            {{al, r1, r2, minus, r10, LSR, 25, PreIndex},
2328                             false,
2329                             al,
2330                             "al r1 r2 minus r10 LSR 25 PreIndex",
2331                             "al_r1_r2_minus_r10_LSR_25_PreIndex"},
2332                            {{al, r1, r3, plus, r11, LSR, 19, PreIndex},
2333                             false,
2334                             al,
2335                             "al r1 r3 plus r11 LSR 19 PreIndex",
2336                             "al_r1_r3_plus_r11_LSR_19_PreIndex"},
2337                            {{al, r3, r4, minus, r9, LSR, 32, PostIndex},
2338                             false,
2339                             al,
2340                             "al r3 r4 minus r9 LSR 32 PostIndex",
2341                             "al_r3_r4_minus_r9_LSR_32_PostIndex"},
2342                            {{al, r13, r11, plus, r2, LSR, 17, PreIndex},
2343                             false,
2344                             al,
2345                             "al r13 r11 plus r2 LSR 17 PreIndex",
2346                             "al_r13_r11_plus_r2_LSR_17_PreIndex"},
2347                            {{al, r4, r6, plus, r2, ASR, 20, PreIndex},
2348                             false,
2349                             al,
2350                             "al r4 r6 plus r2 ASR 20 PreIndex",
2351                             "al_r4_r6_plus_r2_ASR_20_PreIndex"},
2352                            {{al, r1, r12, minus, r10, ASR, 18, PreIndex},
2353                             false,
2354                             al,
2355                             "al r1 r12 minus r10 ASR 18 PreIndex",
2356                             "al_r1_r12_minus_r10_ASR_18_PreIndex"},
2357                            {{al, r4, r14, plus, r7, LSR, 15, PostIndex},
2358                             false,
2359                             al,
2360                             "al r4 r14 plus r7 LSR 15 PostIndex",
2361                             "al_r4_r14_plus_r7_LSR_15_PostIndex"},
2362                            {{al, r11, r13, minus, r0, ASR, 19, PreIndex},
2363                             false,
2364                             al,
2365                             "al r11 r13 minus r0 ASR 19 PreIndex",
2366                             "al_r11_r13_minus_r0_ASR_19_PreIndex"},
2367                            {{al, r13, r10, minus, r12, ASR, 8, PostIndex},
2368                             false,
2369                             al,
2370                             "al r13 r10 minus r12 ASR 8 PostIndex",
2371                             "al_r13_r10_minus_r12_ASR_8_PostIndex"},
2372                            {{al, r5, r14, minus, r4, ASR, 17, PreIndex},
2373                             false,
2374                             al,
2375                             "al r5 r14 minus r4 ASR 17 PreIndex",
2376                             "al_r5_r14_minus_r4_ASR_17_PreIndex"},
2377                            {{al, r8, r7, minus, r3, LSR, 11, PreIndex},
2378                             false,
2379                             al,
2380                             "al r8 r7 minus r3 LSR 11 PreIndex",
2381                             "al_r8_r7_minus_r3_LSR_11_PreIndex"},
2382                            {{al, r12, r7, plus, r8, ASR, 3, PostIndex},
2383                             false,
2384                             al,
2385                             "al r12 r7 plus r8 ASR 3 PostIndex",
2386                             "al_r12_r7_plus_r8_ASR_3_PostIndex"},
2387                            {{al, r0, r6, minus, r4, ASR, 26, PostIndex},
2388                             false,
2389                             al,
2390                             "al r0 r6 minus r4 ASR 26 PostIndex",
2391                             "al_r0_r6_minus_r4_ASR_26_PostIndex"},
2392                            {{al, r5, r13, plus, r8, ASR, 21, PreIndex},
2393                             false,
2394                             al,
2395                             "al r5 r13 plus r8 ASR 21 PreIndex",
2396                             "al_r5_r13_plus_r8_ASR_21_PreIndex"},
2397                            {{al, r4, r0, minus, r0, ASR, 3, PostIndex},
2398                             false,
2399                             al,
2400                             "al r4 r0 minus r0 ASR 3 PostIndex",
2401                             "al_r4_r0_minus_r0_ASR_3_PostIndex"},
2402                            {{al, r13, r3, minus, r0, LSR, 20, PreIndex},
2403                             false,
2404                             al,
2405                             "al r13 r3 minus r0 LSR 20 PreIndex",
2406                             "al_r13_r3_minus_r0_LSR_20_PreIndex"},
2407                            {{al, r3, r14, minus, r6, ASR, 31, PostIndex},
2408                             false,
2409                             al,
2410                             "al r3 r14 minus r6 ASR 31 PostIndex",
2411                             "al_r3_r14_minus_r6_ASR_31_PostIndex"},
2412                            {{al, r12, r2, plus, r13, LSR, 1, PreIndex},
2413                             false,
2414                             al,
2415                             "al r12 r2 plus r13 LSR 1 PreIndex",
2416                             "al_r12_r2_plus_r13_LSR_1_PreIndex"},
2417                            {{al, r9, r11, plus, r8, LSR, 15, PreIndex},
2418                             false,
2419                             al,
2420                             "al r9 r11 plus r8 LSR 15 PreIndex",
2421                             "al_r9_r11_plus_r8_LSR_15_PreIndex"},
2422                            {{al, r3, r14, plus, r9, LSR, 22, PreIndex},
2423                             false,
2424                             al,
2425                             "al r3 r14 plus r9 LSR 22 PreIndex",
2426                             "al_r3_r14_plus_r9_LSR_22_PreIndex"},
2427                            {{al, r12, r1, plus, r2, ASR, 23, PostIndex},
2428                             false,
2429                             al,
2430                             "al r12 r1 plus r2 ASR 23 PostIndex",
2431                             "al_r12_r1_plus_r2_ASR_23_PostIndex"},
2432                            {{al, r4, r6, plus, r4, LSR, 18, PreIndex},
2433                             false,
2434                             al,
2435                             "al r4 r6 plus r4 LSR 18 PreIndex",
2436                             "al_r4_r6_plus_r4_LSR_18_PreIndex"},
2437                            {{al, r11, r2, minus, r3, ASR, 30, PreIndex},
2438                             false,
2439                             al,
2440                             "al r11 r2 minus r3 ASR 30 PreIndex",
2441                             "al_r11_r2_minus_r3_ASR_30_PreIndex"},
2442                            {{al, r4, r1, minus, r0, ASR, 6, PostIndex},
2443                             false,
2444                             al,
2445                             "al r4 r1 minus r0 ASR 6 PostIndex",
2446                             "al_r4_r1_minus_r0_ASR_6_PostIndex"},
2447                            {{al, r12, r5, minus, r9, LSR, 30, PreIndex},
2448                             false,
2449                             al,
2450                             "al r12 r5 minus r9 LSR 30 PreIndex",
2451                             "al_r12_r5_minus_r9_LSR_30_PreIndex"},
2452                            {{al, r11, r0, minus, r1, LSR, 26, PreIndex},
2453                             false,
2454                             al,
2455                             "al r11 r0 minus r1 LSR 26 PreIndex",
2456                             "al_r11_r0_minus_r1_LSR_26_PreIndex"},
2457                            {{al, r11, r2, plus, r11, LSR, 4, PostIndex},
2458                             false,
2459                             al,
2460                             "al r11 r2 plus r11 LSR 4 PostIndex",
2461                             "al_r11_r2_plus_r11_LSR_4_PostIndex"},
2462                            {{al, r12, r13, plus, r10, LSR, 8, PostIndex},
2463                             false,
2464                             al,
2465                             "al r12 r13 plus r10 LSR 8 PostIndex",
2466                             "al_r12_r13_plus_r10_LSR_8_PostIndex"},
2467                            {{al, r0, r9, minus, r2, ASR, 29, PostIndex},
2468                             false,
2469                             al,
2470                             "al r0 r9 minus r2 ASR 29 PostIndex",
2471                             "al_r0_r9_minus_r2_ASR_29_PostIndex"},
2472                            {{al, r1, r10, plus, r13, LSR, 16, PostIndex},
2473                             false,
2474                             al,
2475                             "al r1 r10 plus r13 LSR 16 PostIndex",
2476                             "al_r1_r10_plus_r13_LSR_16_PostIndex"},
2477                            {{al, r5, r12, minus, r1, ASR, 21, PostIndex},
2478                             false,
2479                             al,
2480                             "al r5 r12 minus r1 ASR 21 PostIndex",
2481                             "al_r5_r12_minus_r1_ASR_21_PostIndex"},
2482                            {{al, r14, r1, minus, r11, ASR, 23, PreIndex},
2483                             false,
2484                             al,
2485                             "al r14 r1 minus r11 ASR 23 PreIndex",
2486                             "al_r14_r1_minus_r11_ASR_23_PreIndex"},
2487                            {{al, r6, r12, plus, r10, LSR, 13, PostIndex},
2488                             false,
2489                             al,
2490                             "al r6 r12 plus r10 LSR 13 PostIndex",
2491                             "al_r6_r12_plus_r10_LSR_13_PostIndex"},
2492                            {{al, r5, r2, minus, r2, ASR, 13, PreIndex},
2493                             false,
2494                             al,
2495                             "al r5 r2 minus r2 ASR 13 PreIndex",
2496                             "al_r5_r2_minus_r2_ASR_13_PreIndex"},
2497                            {{al, r1, r12, plus, r6, ASR, 18, PreIndex},
2498                             false,
2499                             al,
2500                             "al r1 r12 plus r6 ASR 18 PreIndex",
2501                             "al_r1_r12_plus_r6_ASR_18_PreIndex"},
2502                            {{al, r7, r5, minus, r1, ASR, 11, PostIndex},
2503                             false,
2504                             al,
2505                             "al r7 r5 minus r1 ASR 11 PostIndex",
2506                             "al_r7_r5_minus_r1_ASR_11_PostIndex"},
2507                            {{al, r4, r6, minus, r1, LSR, 3, PreIndex},
2508                             false,
2509                             al,
2510                             "al r4 r6 minus r1 LSR 3 PreIndex",
2511                             "al_r4_r6_minus_r1_LSR_3_PreIndex"},
2512                            {{al, r6, r5, plus, r13, LSR, 27, PreIndex},
2513                             false,
2514                             al,
2515                             "al r6 r5 plus r13 LSR 27 PreIndex",
2516                             "al_r6_r5_plus_r13_LSR_27_PreIndex"},
2517                            {{al, r1, r13, minus, r13, ASR, 30, PreIndex},
2518                             false,
2519                             al,
2520                             "al r1 r13 minus r13 ASR 30 PreIndex",
2521                             "al_r1_r13_minus_r13_ASR_30_PreIndex"},
2522                            {{al, r5, r13, plus, r9, LSR, 3, PreIndex},
2523                             false,
2524                             al,
2525                             "al r5 r13 plus r9 LSR 3 PreIndex",
2526                             "al_r5_r13_plus_r9_LSR_3_PreIndex"},
2527                            {{al, r1, r4, plus, r0, ASR, 25, PreIndex},
2528                             false,
2529                             al,
2530                             "al r1 r4 plus r0 ASR 25 PreIndex",
2531                             "al_r1_r4_plus_r0_ASR_25_PreIndex"},
2532                            {{al, r0, r12, minus, r0, ASR, 17, PostIndex},
2533                             false,
2534                             al,
2535                             "al r0 r12 minus r0 ASR 17 PostIndex",
2536                             "al_r0_r12_minus_r0_ASR_17_PostIndex"},
2537                            {{al, r5, r4, minus, r7, LSR, 11, PostIndex},
2538                             false,
2539                             al,
2540                             "al r5 r4 minus r7 LSR 11 PostIndex",
2541                             "al_r5_r4_minus_r7_LSR_11_PostIndex"},
2542                            {{al, r14, r4, minus, r10, ASR, 16, PreIndex},
2543                             false,
2544                             al,
2545                             "al r14 r4 minus r10 ASR 16 PreIndex",
2546                             "al_r14_r4_minus_r10_ASR_16_PreIndex"},
2547                            {{al, r4, r12, plus, r12, LSR, 17, PostIndex},
2548                             false,
2549                             al,
2550                             "al r4 r12 plus r12 LSR 17 PostIndex",
2551                             "al_r4_r12_plus_r12_LSR_17_PostIndex"},
2552                            {{al, r9, r2, plus, r7, LSR, 24, PostIndex},
2553                             false,
2554                             al,
2555                             "al r9 r2 plus r7 LSR 24 PostIndex",
2556                             "al_r9_r2_plus_r7_LSR_24_PostIndex"},
2557                            {{al, r13, r14, plus, r7, ASR, 12, PostIndex},
2558                             false,
2559                             al,
2560                             "al r13 r14 plus r7 ASR 12 PostIndex",
2561                             "al_r13_r14_plus_r7_ASR_12_PostIndex"},
2562                            {{al, r2, r7, minus, r11, LSR, 13, PreIndex},
2563                             false,
2564                             al,
2565                             "al r2 r7 minus r11 LSR 13 PreIndex",
2566                             "al_r2_r7_minus_r11_LSR_13_PreIndex"},
2567                            {{al, r0, r4, plus, r9, LSR, 27, PostIndex},
2568                             false,
2569                             al,
2570                             "al r0 r4 plus r9 LSR 27 PostIndex",
2571                             "al_r0_r4_plus_r9_LSR_27_PostIndex"},
2572                            {{al, r6, r9, minus, r10, LSR, 29, PostIndex},
2573                             false,
2574                             al,
2575                             "al r6 r9 minus r10 LSR 29 PostIndex",
2576                             "al_r6_r9_minus_r10_LSR_29_PostIndex"},
2577                            {{al, r7, r4, minus, r1, ASR, 25, PostIndex},
2578                             false,
2579                             al,
2580                             "al r7 r4 minus r1 ASR 25 PostIndex",
2581                             "al_r7_r4_minus_r1_ASR_25_PostIndex"},
2582                            {{al, r6, r1, plus, r11, ASR, 29, PostIndex},
2583                             false,
2584                             al,
2585                             "al r6 r1 plus r11 ASR 29 PostIndex",
2586                             "al_r6_r1_plus_r11_ASR_29_PostIndex"},
2587                            {{al, r12, r7, minus, r13, LSR, 3, PostIndex},
2588                             false,
2589                             al,
2590                             "al r12 r7 minus r13 LSR 3 PostIndex",
2591                             "al_r12_r7_minus_r13_LSR_3_PostIndex"},
2592                            {{al, r13, r12, plus, r6, ASR, 25, PostIndex},
2593                             false,
2594                             al,
2595                             "al r13 r12 plus r6 ASR 25 PostIndex",
2596                             "al_r13_r12_plus_r6_ASR_25_PostIndex"},
2597                            {{al, r2, r4, minus, r1, ASR, 13, PostIndex},
2598                             false,
2599                             al,
2600                             "al r2 r4 minus r1 ASR 13 PostIndex",
2601                             "al_r2_r4_minus_r1_ASR_13_PostIndex"},
2602                            {{al, r6, r3, plus, r3, ASR, 5, PreIndex},
2603                             false,
2604                             al,
2605                             "al r6 r3 plus r3 ASR 5 PreIndex",
2606                             "al_r6_r3_plus_r3_ASR_5_PreIndex"},
2607                            {{al, r0, r1, plus, r0, LSR, 8, PostIndex},
2608                             false,
2609                             al,
2610                             "al r0 r1 plus r0 LSR 8 PostIndex",
2611                             "al_r0_r1_plus_r0_LSR_8_PostIndex"},
2612                            {{al, r6, r0, minus, r3, LSR, 31, PostIndex},
2613                             false,
2614                             al,
2615                             "al r6 r0 minus r3 LSR 31 PostIndex",
2616                             "al_r6_r0_minus_r3_LSR_31_PostIndex"},
2617                            {{al, r9, r11, minus, r3, ASR, 2, PostIndex},
2618                             false,
2619                             al,
2620                             "al r9 r11 minus r3 ASR 2 PostIndex",
2621                             "al_r9_r11_minus_r3_ASR_2_PostIndex"},
2622                            {{al, r1, r13, plus, r13, LSR, 26, PostIndex},
2623                             false,
2624                             al,
2625                             "al r1 r13 plus r13 LSR 26 PostIndex",
2626                             "al_r1_r13_plus_r13_LSR_26_PostIndex"},
2627                            {{al, r14, r3, minus, r7, ASR, 18, PreIndex},
2628                             false,
2629                             al,
2630                             "al r14 r3 minus r7 ASR 18 PreIndex",
2631                             "al_r14_r3_minus_r7_ASR_18_PreIndex"},
2632                            {{al, r11, r12, plus, r1, LSR, 5, PostIndex},
2633                             false,
2634                             al,
2635                             "al r11 r12 plus r1 LSR 5 PostIndex",
2636                             "al_r11_r12_plus_r1_LSR_5_PostIndex"},
2637                            {{al, r4, r6, minus, r0, ASR, 7, PostIndex},
2638                             false,
2639                             al,
2640                             "al r4 r6 minus r0 ASR 7 PostIndex",
2641                             "al_r4_r6_minus_r0_ASR_7_PostIndex"},
2642                            {{al, r8, r14, plus, r2, ASR, 13, PreIndex},
2643                             false,
2644                             al,
2645                             "al r8 r14 plus r2 ASR 13 PreIndex",
2646                             "al_r8_r14_plus_r2_ASR_13_PreIndex"},
2647                            {{al, r1, r6, minus, r13, ASR, 14, PostIndex},
2648                             false,
2649                             al,
2650                             "al r1 r6 minus r13 ASR 14 PostIndex",
2651                             "al_r1_r6_minus_r13_ASR_14_PostIndex"},
2652                            {{al, r8, r9, minus, r3, LSR, 3, PreIndex},
2653                             false,
2654                             al,
2655                             "al r8 r9 minus r3 LSR 3 PreIndex",
2656                             "al_r8_r9_minus_r3_LSR_3_PreIndex"},
2657                            {{al, r2, r14, plus, r8, ASR, 2, PreIndex},
2658                             false,
2659                             al,
2660                             "al r2 r14 plus r8 ASR 2 PreIndex",
2661                             "al_r2_r14_plus_r8_ASR_2_PreIndex"},
2662                            {{al, r1, r10, minus, r5, ASR, 31, PostIndex},
2663                             false,
2664                             al,
2665                             "al r1 r10 minus r5 ASR 31 PostIndex",
2666                             "al_r1_r10_minus_r5_ASR_31_PostIndex"},
2667                            {{al, r2, r14, minus, r13, ASR, 28, PostIndex},
2668                             false,
2669                             al,
2670                             "al r2 r14 minus r13 ASR 28 PostIndex",
2671                             "al_r2_r14_minus_r13_ASR_28_PostIndex"},
2672                            {{al, r14, r5, plus, r5, LSR, 11, PostIndex},
2673                             false,
2674                             al,
2675                             "al r14 r5 plus r5 LSR 11 PostIndex",
2676                             "al_r14_r5_plus_r5_LSR_11_PostIndex"},
2677                            {{al, r2, r14, minus, r14, ASR, 21, PostIndex},
2678                             false,
2679                             al,
2680                             "al r2 r14 minus r14 ASR 21 PostIndex",
2681                             "al_r2_r14_minus_r14_ASR_21_PostIndex"},
2682                            {{al, r12, r1, plus, r0, LSR, 3, PostIndex},
2683                             false,
2684                             al,
2685                             "al r12 r1 plus r0 LSR 3 PostIndex",
2686                             "al_r12_r1_plus_r0_LSR_3_PostIndex"},
2687                            {{al, r12, r5, plus, r14, LSR, 27, PostIndex},
2688                             false,
2689                             al,
2690                             "al r12 r5 plus r14 LSR 27 PostIndex",
2691                             "al_r12_r5_plus_r14_LSR_27_PostIndex"},
2692                            {{al, r14, r3, minus, r6, LSR, 15, PostIndex},
2693                             false,
2694                             al,
2695                             "al r14 r3 minus r6 LSR 15 PostIndex",
2696                             "al_r14_r3_minus_r6_LSR_15_PostIndex"},
2697                            {{al, r1, r4, plus, r1, LSR, 29, PostIndex},
2698                             false,
2699                             al,
2700                             "al r1 r4 plus r1 LSR 29 PostIndex",
2701                             "al_r1_r4_plus_r1_LSR_29_PostIndex"},
2702                            {{al, r3, r2, plus, r8, ASR, 29, PreIndex},
2703                             false,
2704                             al,
2705                             "al r3 r2 plus r8 ASR 29 PreIndex",
2706                             "al_r3_r2_plus_r8_ASR_29_PreIndex"},
2707                            {{al, r6, r4, minus, r2, ASR, 28, PostIndex},
2708                             false,
2709                             al,
2710                             "al r6 r4 minus r2 ASR 28 PostIndex",
2711                             "al_r6_r4_minus_r2_ASR_28_PostIndex"},
2712                            {{al, r7, r11, minus, r13, ASR, 31, PreIndex},
2713                             false,
2714                             al,
2715                             "al r7 r11 minus r13 ASR 31 PreIndex",
2716                             "al_r7_r11_minus_r13_ASR_31_PreIndex"},
2717                            {{al, r9, r13, plus, r10, ASR, 10, PreIndex},
2718                             false,
2719                             al,
2720                             "al r9 r13 plus r10 ASR 10 PreIndex",
2721                             "al_r9_r13_plus_r10_ASR_10_PreIndex"},
2722                            {{al, r7, r5, plus, r8, ASR, 14, PostIndex},
2723                             false,
2724                             al,
2725                             "al r7 r5 plus r8 ASR 14 PostIndex",
2726                             "al_r7_r5_plus_r8_ASR_14_PostIndex"},
2727                            {{al, r12, r7, minus, r13, LSR, 8, PostIndex},
2728                             false,
2729                             al,
2730                             "al r12 r7 minus r13 LSR 8 PostIndex",
2731                             "al_r12_r7_minus_r13_LSR_8_PostIndex"},
2732                            {{al, r14, r11, plus, r10, ASR, 6, PreIndex},
2733                             false,
2734                             al,
2735                             "al r14 r11 plus r10 ASR 6 PreIndex",
2736                             "al_r14_r11_plus_r10_ASR_6_PreIndex"},
2737                            {{al, r1, r5, minus, r5, LSR, 22, PreIndex},
2738                             false,
2739                             al,
2740                             "al r1 r5 minus r5 LSR 22 PreIndex",
2741                             "al_r1_r5_minus_r5_LSR_22_PreIndex"},
2742                            {{al, r12, r5, plus, r4, ASR, 7, PostIndex},
2743                             false,
2744                             al,
2745                             "al r12 r5 plus r4 ASR 7 PostIndex",
2746                             "al_r12_r5_plus_r4_ASR_7_PostIndex"},
2747                            {{al, r10, r12, minus, r11, LSR, 15, PreIndex},
2748                             false,
2749                             al,
2750                             "al r10 r12 minus r11 LSR 15 PreIndex",
2751                             "al_r10_r12_minus_r11_LSR_15_PreIndex"},
2752                            {{al, r13, r2, plus, r5, LSR, 26, PreIndex},
2753                             false,
2754                             al,
2755                             "al r13 r2 plus r5 LSR 26 PreIndex",
2756                             "al_r13_r2_plus_r5_LSR_26_PreIndex"},
2757                            {{al, r7, r1, minus, r4, LSR, 24, PostIndex},
2758                             false,
2759                             al,
2760                             "al r7 r1 minus r4 LSR 24 PostIndex",
2761                             "al_r7_r1_minus_r4_LSR_24_PostIndex"},
2762                            {{al, r7, r1, plus, r5, LSR, 10, PostIndex},
2763                             false,
2764                             al,
2765                             "al r7 r1 plus r5 LSR 10 PostIndex",
2766                             "al_r7_r1_plus_r5_LSR_10_PostIndex"},
2767                            {{al, r7, r0, plus, r3, ASR, 27, PostIndex},
2768                             false,
2769                             al,
2770                             "al r7 r0 plus r3 ASR 27 PostIndex",
2771                             "al_r7_r0_plus_r3_ASR_27_PostIndex"},
2772                            {{al, r5, r11, minus, r8, ASR, 29, PostIndex},
2773                             false,
2774                             al,
2775                             "al r5 r11 minus r8 ASR 29 PostIndex",
2776                             "al_r5_r11_minus_r8_ASR_29_PostIndex"},
2777                            {{al, r9, r12, plus, r7, LSR, 29, PostIndex},
2778                             false,
2779                             al,
2780                             "al r9 r12 plus r7 LSR 29 PostIndex",
2781                             "al_r9_r12_plus_r7_LSR_29_PostIndex"},
2782                            {{al, r10, r0, minus, r10, LSR, 8, PostIndex},
2783                             false,
2784                             al,
2785                             "al r10 r0 minus r10 LSR 8 PostIndex",
2786                             "al_r10_r0_minus_r10_LSR_8_PostIndex"},
2787                            {{al, r5, r12, plus, r14, LSR, 8, PostIndex},
2788                             false,
2789                             al,
2790                             "al r5 r12 plus r14 LSR 8 PostIndex",
2791                             "al_r5_r12_plus_r14_LSR_8_PostIndex"},
2792                            {{al, r13, r12, plus, r3, LSR, 14, PreIndex},
2793                             false,
2794                             al,
2795                             "al r13 r12 plus r3 LSR 14 PreIndex",
2796                             "al_r13_r12_plus_r3_LSR_14_PreIndex"},
2797                            {{al, r4, r13, minus, r7, ASR, 4, PreIndex},
2798                             false,
2799                             al,
2800                             "al r4 r13 minus r7 ASR 4 PreIndex",
2801                             "al_r4_r13_minus_r7_ASR_4_PreIndex"},
2802                            {{al, r2, r12, minus, r12, ASR, 9, PostIndex},
2803                             false,
2804                             al,
2805                             "al r2 r12 minus r12 ASR 9 PostIndex",
2806                             "al_r2_r12_minus_r12_ASR_9_PostIndex"},
2807                            {{al, r13, r8, plus, r11, LSR, 2, PostIndex},
2808                             false,
2809                             al,
2810                             "al r13 r8 plus r11 LSR 2 PostIndex",
2811                             "al_r13_r8_plus_r11_LSR_2_PostIndex"},
2812                            {{al, r6, r5, minus, r12, ASR, 6, PostIndex},
2813                             false,
2814                             al,
2815                             "al r6 r5 minus r12 ASR 6 PostIndex",
2816                             "al_r6_r5_minus_r12_ASR_6_PostIndex"},
2817                            {{al, r9, r12, plus, r14, ASR, 31, PreIndex},
2818                             false,
2819                             al,
2820                             "al r9 r12 plus r14 ASR 31 PreIndex",
2821                             "al_r9_r12_plus_r14_ASR_31_PreIndex"},
2822                            {{al, r13, r7, minus, r5, ASR, 17, PreIndex},
2823                             false,
2824                             al,
2825                             "al r13 r7 minus r5 ASR 17 PreIndex",
2826                             "al_r13_r7_minus_r5_ASR_17_PreIndex"},
2827                            {{al, r14, r4, minus, r8, ASR, 32, PostIndex},
2828                             false,
2829                             al,
2830                             "al r14 r4 minus r8 ASR 32 PostIndex",
2831                             "al_r14_r4_minus_r8_ASR_32_PostIndex"},
2832                            {{al, r1, r4, plus, r9, LSR, 20, PreIndex},
2833                             false,
2834                             al,
2835                             "al r1 r4 plus r9 LSR 20 PreIndex",
2836                             "al_r1_r4_plus_r9_LSR_20_PreIndex"},
2837                            {{al, r11, r8, plus, r13, LSR, 12, PostIndex},
2838                             false,
2839                             al,
2840                             "al r11 r8 plus r13 LSR 12 PostIndex",
2841                             "al_r11_r8_plus_r13_LSR_12_PostIndex"},
2842                            {{al, r3, r0, plus, r4, LSR, 22, PreIndex},
2843                             false,
2844                             al,
2845                             "al r3 r0 plus r4 LSR 22 PreIndex",
2846                             "al_r3_r0_plus_r4_LSR_22_PreIndex"},
2847                            {{al, r9, r8, plus, r2, LSR, 19, PostIndex},
2848                             false,
2849                             al,
2850                             "al r9 r8 plus r2 LSR 19 PostIndex",
2851                             "al_r9_r8_plus_r2_LSR_19_PostIndex"},
2852                            {{al, r14, r11, plus, r8, ASR, 28, PreIndex},
2853                             false,
2854                             al,
2855                             "al r14 r11 plus r8 ASR 28 PreIndex",
2856                             "al_r14_r11_plus_r8_ASR_28_PreIndex"},
2857                            {{al, r6, r10, plus, r5, LSR, 28, PostIndex},
2858                             false,
2859                             al,
2860                             "al r6 r10 plus r5 LSR 28 PostIndex",
2861                             "al_r6_r10_plus_r5_LSR_28_PostIndex"},
2862                            {{al, r12, r13, minus, r12, ASR, 14, PreIndex},
2863                             false,
2864                             al,
2865                             "al r12 r13 minus r12 ASR 14 PreIndex",
2866                             "al_r12_r13_minus_r12_ASR_14_PreIndex"},
2867                            {{al, r12, r2, plus, r9, ASR, 13, PostIndex},
2868                             false,
2869                             al,
2870                             "al r12 r2 plus r9 ASR 13 PostIndex",
2871                             "al_r12_r2_plus_r9_ASR_13_PostIndex"},
2872                            {{al, r11, r13, minus, r8, LSR, 14, PreIndex},
2873                             false,
2874                             al,
2875                             "al r11 r13 minus r8 LSR 14 PreIndex",
2876                             "al_r11_r13_minus_r8_LSR_14_PreIndex"},
2877                            {{al, r6, r4, minus, r11, LSR, 1, PreIndex},
2878                             false,
2879                             al,
2880                             "al r6 r4 minus r11 LSR 1 PreIndex",
2881                             "al_r6_r4_minus_r11_LSR_1_PreIndex"},
2882                            {{al, r3, r6, plus, r1, ASR, 14, PostIndex},
2883                             false,
2884                             al,
2885                             "al r3 r6 plus r1 ASR 14 PostIndex",
2886                             "al_r3_r6_plus_r1_ASR_14_PostIndex"},
2887                            {{al, r14, r9, minus, r0, ASR, 23, PostIndex},
2888                             false,
2889                             al,
2890                             "al r14 r9 minus r0 ASR 23 PostIndex",
2891                             "al_r14_r9_minus_r0_ASR_23_PostIndex"},
2892                            {{al, r9, r2, plus, r0, ASR, 23, PreIndex},
2893                             false,
2894                             al,
2895                             "al r9 r2 plus r0 ASR 23 PreIndex",
2896                             "al_r9_r2_plus_r0_ASR_23_PreIndex"},
2897                            {{al, r8, r4, minus, r9, LSR, 13, PostIndex},
2898                             false,
2899                             al,
2900                             "al r8 r4 minus r9 LSR 13 PostIndex",
2901                             "al_r8_r4_minus_r9_LSR_13_PostIndex"},
2902                            {{al, r0, r12, plus, r5, LSR, 12, PostIndex},
2903                             false,
2904                             al,
2905                             "al r0 r12 plus r5 LSR 12 PostIndex",
2906                             "al_r0_r12_plus_r5_LSR_12_PostIndex"},
2907                            {{al, r6, r5, plus, r3, ASR, 31, PostIndex},
2908                             false,
2909                             al,
2910                             "al r6 r5 plus r3 ASR 31 PostIndex",
2911                             "al_r6_r5_plus_r3_ASR_31_PostIndex"},
2912                            {{al, r0, r2, minus, r11, ASR, 16, PostIndex},
2913                             false,
2914                             al,
2915                             "al r0 r2 minus r11 ASR 16 PostIndex",
2916                             "al_r0_r2_minus_r11_ASR_16_PostIndex"},
2917                            {{al, r14, r10, plus, r12, ASR, 32, PreIndex},
2918                             false,
2919                             al,
2920                             "al r14 r10 plus r12 ASR 32 PreIndex",
2921                             "al_r14_r10_plus_r12_ASR_32_PreIndex"},
2922                            {{al, r10, r14, minus, r7, LSR, 13, PreIndex},
2923                             false,
2924                             al,
2925                             "al r10 r14 minus r7 LSR 13 PreIndex",
2926                             "al_r10_r14_minus_r7_LSR_13_PreIndex"},
2927                            {{al, r2, r10, plus, r13, ASR, 32, PostIndex},
2928                             false,
2929                             al,
2930                             "al r2 r10 plus r13 ASR 32 PostIndex",
2931                             "al_r2_r10_plus_r13_ASR_32_PostIndex"},
2932                            {{al, r7, r13, minus, r13, ASR, 2, PreIndex},
2933                             false,
2934                             al,
2935                             "al r7 r13 minus r13 ASR 2 PreIndex",
2936                             "al_r7_r13_minus_r13_ASR_2_PreIndex"},
2937                            {{al, r5, r14, plus, r1, ASR, 19, PreIndex},
2938                             false,
2939                             al,
2940                             "al r5 r14 plus r1 ASR 19 PreIndex",
2941                             "al_r5_r14_plus_r1_ASR_19_PreIndex"},
2942                            {{al, r7, r8, plus, r8, LSR, 12, PreIndex},
2943                             false,
2944                             al,
2945                             "al r7 r8 plus r8 LSR 12 PreIndex",
2946                             "al_r7_r8_plus_r8_LSR_12_PreIndex"},
2947                            {{al, r6, r8, plus, r6, ASR, 31, PostIndex},
2948                             false,
2949                             al,
2950                             "al r6 r8 plus r6 ASR 31 PostIndex",
2951                             "al_r6_r8_plus_r6_ASR_31_PostIndex"},
2952                            {{al, r9, r0, minus, r0, LSR, 3, PostIndex},
2953                             false,
2954                             al,
2955                             "al r9 r0 minus r0 LSR 3 PostIndex",
2956                             "al_r9_r0_minus_r0_LSR_3_PostIndex"},
2957                            {{al, r13, r14, plus, r6, ASR, 31, PostIndex},
2958                             false,
2959                             al,
2960                             "al r13 r14 plus r6 ASR 31 PostIndex",
2961                             "al_r13_r14_plus_r6_ASR_31_PostIndex"},
2962                            {{al, r5, r8, minus, r0, ASR, 26, PostIndex},
2963                             false,
2964                             al,
2965                             "al r5 r8 minus r0 ASR 26 PostIndex",
2966                             "al_r5_r8_minus_r0_ASR_26_PostIndex"},
2967                            {{al, r1, r9, plus, r5, LSR, 11, PostIndex},
2968                             false,
2969                             al,
2970                             "al r1 r9 plus r5 LSR 11 PostIndex",
2971                             "al_r1_r9_plus_r5_LSR_11_PostIndex"},
2972                            {{al, r6, r12, plus, r12, LSR, 22, PostIndex},
2973                             false,
2974                             al,
2975                             "al r6 r12 plus r12 LSR 22 PostIndex",
2976                             "al_r6_r12_plus_r12_LSR_22_PostIndex"},
2977                            {{al, r6, r12, minus, r6, ASR, 1, PreIndex},
2978                             false,
2979                             al,
2980                             "al r6 r12 minus r6 ASR 1 PreIndex",
2981                             "al_r6_r12_minus_r6_ASR_1_PreIndex"},
2982                            {{al, r4, r1, plus, r14, LSR, 30, PostIndex},
2983                             false,
2984                             al,
2985                             "al r4 r1 plus r14 LSR 30 PostIndex",
2986                             "al_r4_r1_plus_r14_LSR_30_PostIndex"},
2987                            {{al, r9, r11, plus, r8, ASR, 21, PostIndex},
2988                             false,
2989                             al,
2990                             "al r9 r11 plus r8 ASR 21 PostIndex",
2991                             "al_r9_r11_plus_r8_ASR_21_PostIndex"},
2992                            {{al, r1, r0, minus, r13, ASR, 19, PostIndex},
2993                             false,
2994                             al,
2995                             "al r1 r0 minus r13 ASR 19 PostIndex",
2996                             "al_r1_r0_minus_r13_ASR_19_PostIndex"},
2997                            {{al, r10, r12, plus, r13, LSR, 19, PostIndex},
2998                             false,
2999                             al,
3000                             "al r10 r12 plus r13 LSR 19 PostIndex",
3001                             "al_r10_r12_plus_r13_LSR_19_PostIndex"},
3002                            {{al, r2, r7, minus, r14, LSR, 29, PostIndex},
3003                             false,
3004                             al,
3005                             "al r2 r7 minus r14 LSR 29 PostIndex",
3006                             "al_r2_r7_minus_r14_LSR_29_PostIndex"},
3007                            {{al, r7, r0, plus, r0, LSR, 2, PostIndex},
3008                             false,
3009                             al,
3010                             "al r7 r0 plus r0 LSR 2 PostIndex",
3011                             "al_r7_r0_plus_r0_LSR_2_PostIndex"},
3012                            {{al, r2, r8, plus, r7, LSR, 2, PostIndex},
3013                             false,
3014                             al,
3015                             "al r2 r8 plus r7 LSR 2 PostIndex",
3016                             "al_r2_r8_plus_r7_LSR_2_PostIndex"},
3017                            {{al, r5, r10, minus, r14, LSR, 22, PreIndex},
3018                             false,
3019                             al,
3020                             "al r5 r10 minus r14 LSR 22 PreIndex",
3021                             "al_r5_r10_minus_r14_LSR_22_PreIndex"},
3022                            {{al, r8, r7, plus, r6, ASR, 23, PreIndex},
3023                             false,
3024                             al,
3025                             "al r8 r7 plus r6 ASR 23 PreIndex",
3026                             "al_r8_r7_plus_r6_ASR_23_PreIndex"},
3027                            {{al, r6, r13, plus, r10, LSR, 10, PreIndex},
3028                             false,
3029                             al,
3030                             "al r6 r13 plus r10 LSR 10 PreIndex",
3031                             "al_r6_r13_plus_r10_LSR_10_PreIndex"},
3032                            {{al, r0, r9, plus, r8, ASR, 12, PostIndex},
3033                             false,
3034                             al,
3035                             "al r0 r9 plus r8 ASR 12 PostIndex",
3036                             "al_r0_r9_plus_r8_ASR_12_PostIndex"},
3037                            {{al, r14, r13, plus, r5, LSR, 20, PreIndex},
3038                             false,
3039                             al,
3040                             "al r14 r13 plus r5 LSR 20 PreIndex",
3041                             "al_r14_r13_plus_r5_LSR_20_PreIndex"},
3042                            {{al, r5, r7, plus, r2, LSR, 25, PostIndex},
3043                             false,
3044                             al,
3045                             "al r5 r7 plus r2 LSR 25 PostIndex",
3046                             "al_r5_r7_plus_r2_LSR_25_PostIndex"},
3047                            {{al, r3, r2, plus, r4, LSR, 22, PreIndex},
3048                             false,
3049                             al,
3050                             "al r3 r2 plus r4 LSR 22 PreIndex",
3051                             "al_r3_r2_plus_r4_LSR_22_PreIndex"},
3052                            {{al, r14, r10, plus, r5, LSR, 27, PreIndex},
3053                             false,
3054                             al,
3055                             "al r14 r10 plus r5 LSR 27 PreIndex",
3056                             "al_r14_r10_plus_r5_LSR_27_PreIndex"},
3057                            {{al, r3, r9, plus, r3, LSR, 6, PreIndex},
3058                             false,
3059                             al,
3060                             "al r3 r9 plus r3 LSR 6 PreIndex",
3061                             "al_r3_r9_plus_r3_LSR_6_PreIndex"},
3062                            {{al, r2, r13, plus, r12, ASR, 9, PreIndex},
3063                             false,
3064                             al,
3065                             "al r2 r13 plus r12 ASR 9 PreIndex",
3066                             "al_r2_r13_plus_r12_ASR_9_PreIndex"},
3067                            {{al, r2, r0, minus, r1, ASR, 26, PostIndex},
3068                             false,
3069                             al,
3070                             "al r2 r0 minus r1 ASR 26 PostIndex",
3071                             "al_r2_r0_minus_r1_ASR_26_PostIndex"},
3072                            {{al, r5, r14, plus, r11, ASR, 10, PreIndex},
3073                             false,
3074                             al,
3075                             "al r5 r14 plus r11 ASR 10 PreIndex",
3076                             "al_r5_r14_plus_r11_ASR_10_PreIndex"},
3077                            {{al, r5, r3, minus, r8, LSR, 10, PostIndex},
3078                             false,
3079                             al,
3080                             "al r5 r3 minus r8 LSR 10 PostIndex",
3081                             "al_r5_r3_minus_r8_LSR_10_PostIndex"},
3082                            {{al, r12, r3, minus, r5, LSR, 26, PreIndex},
3083                             false,
3084                             al,
3085                             "al r12 r3 minus r5 LSR 26 PreIndex",
3086                             "al_r12_r3_minus_r5_LSR_26_PreIndex"},
3087                            {{al, r3, r5, minus, r10, ASR, 8, PreIndex},
3088                             false,
3089                             al,
3090                             "al r3 r5 minus r10 ASR 8 PreIndex",
3091                             "al_r3_r5_minus_r10_ASR_8_PreIndex"},
3092                            {{al, r1, r14, minus, r12, ASR, 8, PreIndex},
3093                             false,
3094                             al,
3095                             "al r1 r14 minus r12 ASR 8 PreIndex",
3096                             "al_r1_r14_minus_r12_ASR_8_PreIndex"},
3097                            {{al, r7, r8, minus, r9, ASR, 9, PreIndex},
3098                             false,
3099                             al,
3100                             "al r7 r8 minus r9 ASR 9 PreIndex",
3101                             "al_r7_r8_minus_r9_ASR_9_PreIndex"},
3102                            {{al, r7, r2, plus, r3, LSR, 23, PostIndex},
3103                             false,
3104                             al,
3105                             "al r7 r2 plus r3 LSR 23 PostIndex",
3106                             "al_r7_r2_plus_r3_LSR_23_PostIndex"},
3107                            {{al, r13, r12, plus, r13, ASR, 2, PreIndex},
3108                             false,
3109                             al,
3110                             "al r13 r12 plus r13 ASR 2 PreIndex",
3111                             "al_r13_r12_plus_r13_ASR_2_PreIndex"},
3112                            {{al, r0, r6, plus, r2, ASR, 32, PreIndex},
3113                             false,
3114                             al,
3115                             "al r0 r6 plus r2 ASR 32 PreIndex",
3116                             "al_r0_r6_plus_r2_ASR_32_PreIndex"},
3117                            {{al, r0, r14, plus, r1, LSR, 16, PreIndex},
3118                             false,
3119                             al,
3120                             "al r0 r14 plus r1 LSR 16 PreIndex",
3121                             "al_r0_r14_plus_r1_LSR_16_PreIndex"},
3122                            {{al, r9, r0, minus, r13, LSR, 18, PreIndex},
3123                             false,
3124                             al,
3125                             "al r9 r0 minus r13 LSR 18 PreIndex",
3126                             "al_r9_r0_minus_r13_LSR_18_PreIndex"},
3127                            {{al, r7, r14, minus, r4, LSR, 10, PostIndex},
3128                             false,
3129                             al,
3130                             "al r7 r14 minus r4 LSR 10 PostIndex",
3131                             "al_r7_r14_minus_r4_LSR_10_PostIndex"},
3132                            {{al, r2, r4, plus, r3, LSR, 10, PostIndex},
3133                             false,
3134                             al,
3135                             "al r2 r4 plus r3 LSR 10 PostIndex",
3136                             "al_r2_r4_plus_r3_LSR_10_PostIndex"},
3137                            {{al, r4, r10, minus, r3, ASR, 8, PostIndex},
3138                             false,
3139                             al,
3140                             "al r4 r10 minus r3 ASR 8 PostIndex",
3141                             "al_r4_r10_minus_r3_ASR_8_PostIndex"},
3142                            {{al, r0, r7, plus, r13, ASR, 22, PostIndex},
3143                             false,
3144                             al,
3145                             "al r0 r7 plus r13 ASR 22 PostIndex",
3146                             "al_r0_r7_plus_r13_ASR_22_PostIndex"},
3147                            {{al, r9, r0, plus, r10, LSR, 29, PreIndex},
3148                             false,
3149                             al,
3150                             "al r9 r0 plus r10 LSR 29 PreIndex",
3151                             "al_r9_r0_plus_r10_LSR_29_PreIndex"},
3152                            {{al, r6, r0, plus, r7, ASR, 6, PostIndex},
3153                             false,
3154                             al,
3155                             "al r6 r0 plus r7 ASR 6 PostIndex",
3156                             "al_r6_r0_plus_r7_ASR_6_PostIndex"},
3157                            {{al, r14, r11, minus, r2, ASR, 6, PreIndex},
3158                             false,
3159                             al,
3160                             "al r14 r11 minus r2 ASR 6 PreIndex",
3161                             "al_r14_r11_minus_r2_ASR_6_PreIndex"},
3162                            {{al, r6, r9, minus, r9, ASR, 25, PostIndex},
3163                             false,
3164                             al,
3165                             "al r6 r9 minus r9 ASR 25 PostIndex",
3166                             "al_r6_r9_minus_r9_ASR_25_PostIndex"},
3167                            {{al, r13, r1, minus, r11, LSR, 7, PreIndex},
3168                             false,
3169                             al,
3170                             "al r13 r1 minus r11 LSR 7 PreIndex",
3171                             "al_r13_r1_minus_r11_LSR_7_PreIndex"},
3172                            {{al, r12, r9, minus, r6, ASR, 21, PostIndex},
3173                             false,
3174                             al,
3175                             "al r12 r9 minus r6 ASR 21 PostIndex",
3176                             "al_r12_r9_minus_r6_ASR_21_PostIndex"},
3177                            {{al, r8, r6, minus, r11, ASR, 1, PreIndex},
3178                             false,
3179                             al,
3180                             "al r8 r6 minus r11 ASR 1 PreIndex",
3181                             "al_r8_r6_minus_r11_ASR_1_PreIndex"},
3182                            {{al, r0, r13, minus, r11, LSR, 20, PostIndex},
3183                             false,
3184                             al,
3185                             "al r0 r13 minus r11 LSR 20 PostIndex",
3186                             "al_r0_r13_minus_r11_LSR_20_PostIndex"},
3187                            {{al, r12, r3, minus, r8, ASR, 25, PreIndex},
3188                             false,
3189                             al,
3190                             "al r12 r3 minus r8 ASR 25 PreIndex",
3191                             "al_r12_r3_minus_r8_ASR_25_PreIndex"},
3192                            {{al, r10, r7, plus, r8, ASR, 16, PostIndex},
3193                             false,
3194                             al,
3195                             "al r10 r7 plus r8 ASR 16 PostIndex",
3196                             "al_r10_r7_plus_r8_ASR_16_PostIndex"},
3197                            {{al, r10, r4, plus, r13, LSR, 27, PreIndex},
3198                             false,
3199                             al,
3200                             "al r10 r4 plus r13 LSR 27 PreIndex",
3201                             "al_r10_r4_plus_r13_LSR_27_PreIndex"},
3202                            {{al, r8, r10, plus, r7, ASR, 29, PreIndex},
3203                             false,
3204                             al,
3205                             "al r8 r10 plus r7 ASR 29 PreIndex",
3206                             "al_r8_r10_plus_r7_ASR_29_PreIndex"},
3207                            {{al, r2, r9, minus, r1, LSR, 30, PostIndex},
3208                             false,
3209                             al,
3210                             "al r2 r9 minus r1 LSR 30 PostIndex",
3211                             "al_r2_r9_minus_r1_LSR_30_PostIndex"},
3212                            {{al, r9, r2, plus, r1, LSR, 9, PreIndex},
3213                             false,
3214                             al,
3215                             "al r9 r2 plus r1 LSR 9 PreIndex",
3216                             "al_r9_r2_plus_r1_LSR_9_PreIndex"},
3217                            {{al, r13, r4, plus, r4, ASR, 20, PreIndex},
3218                             false,
3219                             al,
3220                             "al r13 r4 plus r4 ASR 20 PreIndex",
3221                             "al_r13_r4_plus_r4_ASR_20_PreIndex"},
3222                            {{al, r3, r1, minus, r7, ASR, 32, PostIndex},
3223                             false,
3224                             al,
3225                             "al r3 r1 minus r7 ASR 32 PostIndex",
3226                             "al_r3_r1_minus_r7_ASR_32_PostIndex"},
3227                            {{al, r0, r5, minus, r5, ASR, 9, PreIndex},
3228                             false,
3229                             al,
3230                             "al r0 r5 minus r5 ASR 9 PreIndex",
3231                             "al_r0_r5_minus_r5_ASR_9_PreIndex"},
3232                            {{al, r11, r6, minus, r9, LSR, 23, PostIndex},
3233                             false,
3234                             al,
3235                             "al r11 r6 minus r9 LSR 23 PostIndex",
3236                             "al_r11_r6_minus_r9_LSR_23_PostIndex"},
3237                            {{al, r12, r8, plus, r4, ASR, 25, PostIndex},
3238                             false,
3239                             al,
3240                             "al r12 r8 plus r4 ASR 25 PostIndex",
3241                             "al_r12_r8_plus_r4_ASR_25_PostIndex"},
3242                            {{al, r3, r5, minus, r5, LSR, 26, PostIndex},
3243                             false,
3244                             al,
3245                             "al r3 r5 minus r5 LSR 26 PostIndex",
3246                             "al_r3_r5_minus_r5_LSR_26_PostIndex"},
3247                            {{al, r1, r0, minus, r0, LSR, 21, PostIndex},
3248                             false,
3249                             al,
3250                             "al r1 r0 minus r0 LSR 21 PostIndex",
3251                             "al_r1_r0_minus_r0_LSR_21_PostIndex"},
3252                            {{al, r13, r8, plus, r9, LSR, 6, PostIndex},
3253                             false,
3254                             al,
3255                             "al r13 r8 plus r9 LSR 6 PostIndex",
3256                             "al_r13_r8_plus_r9_LSR_6_PostIndex"},
3257                            {{al, r1, r7, plus, r6, LSR, 28, PreIndex},
3258                             false,
3259                             al,
3260                             "al r1 r7 plus r6 LSR 28 PreIndex",
3261                             "al_r1_r7_plus_r6_LSR_28_PreIndex"},
3262                            {{al, r14, r4, plus, r13, LSR, 14, PostIndex},
3263                             false,
3264                             al,
3265                             "al r14 r4 plus r13 LSR 14 PostIndex",
3266                             "al_r14_r4_plus_r13_LSR_14_PostIndex"},
3267                            {{al, r14, r3, plus, r11, ASR, 21, PreIndex},
3268                             false,
3269                             al,
3270                             "al r14 r3 plus r11 ASR 21 PreIndex",
3271                             "al_r14_r3_plus_r11_ASR_21_PreIndex"},
3272                            {{al, r10, r6, plus, r11, LSR, 6, PreIndex},
3273                             false,
3274                             al,
3275                             "al r10 r6 plus r11 LSR 6 PreIndex",
3276                             "al_r10_r6_plus_r11_LSR_6_PreIndex"},
3277                            {{al, r13, r7, plus, r11, ASR, 25, PreIndex},
3278                             false,
3279                             al,
3280                             "al r13 r7 plus r11 ASR 25 PreIndex",
3281                             "al_r13_r7_plus_r11_ASR_25_PreIndex"},
3282                            {{al, r3, r2, minus, r8, LSR, 13, PreIndex},
3283                             false,
3284                             al,
3285                             "al r3 r2 minus r8 LSR 13 PreIndex",
3286                             "al_r3_r2_minus_r8_LSR_13_PreIndex"},
3287                            {{al, r8, r14, minus, r13, LSR, 4, PostIndex},
3288                             false,
3289                             al,
3290                             "al r8 r14 minus r13 LSR 4 PostIndex",
3291                             "al_r8_r14_minus_r13_LSR_4_PostIndex"},
3292                            {{al, r2, r9, minus, r2, LSR, 26, PostIndex},
3293                             false,
3294                             al,
3295                             "al r2 r9 minus r2 LSR 26 PostIndex",
3296                             "al_r2_r9_minus_r2_LSR_26_PostIndex"},
3297                            {{al, r11, r14, minus, r13, ASR, 27, PostIndex},
3298                             false,
3299                             al,
3300                             "al r11 r14 minus r13 ASR 27 PostIndex",
3301                             "al_r11_r14_minus_r13_ASR_27_PostIndex"},
3302                            {{al, r2, r8, minus, r8, LSR, 6, PreIndex},
3303                             false,
3304                             al,
3305                             "al r2 r8 minus r8 LSR 6 PreIndex",
3306                             "al_r2_r8_minus_r8_LSR_6_PreIndex"},
3307                            {{al, r10, r11, minus, r2, ASR, 12, PreIndex},
3308                             false,
3309                             al,
3310                             "al r10 r11 minus r2 ASR 12 PreIndex",
3311                             "al_r10_r11_minus_r2_ASR_12_PreIndex"},
3312                            {{al, r11, r9, plus, r8, ASR, 2, PreIndex},
3313                             false,
3314                             al,
3315                             "al r11 r9 plus r8 ASR 2 PreIndex",
3316                             "al_r11_r9_plus_r8_ASR_2_PreIndex"},
3317                            {{al, r11, r7, minus, r12, ASR, 7, PreIndex},
3318                             false,
3319                             al,
3320                             "al r11 r7 minus r12 ASR 7 PreIndex",
3321                             "al_r11_r7_minus_r12_ASR_7_PreIndex"},
3322                            {{al, r8, r7, plus, r8, ASR, 3, PreIndex},
3323                             false,
3324                             al,
3325                             "al r8 r7 plus r8 ASR 3 PreIndex",
3326                             "al_r8_r7_plus_r8_ASR_3_PreIndex"},
3327                            {{al, r5, r12, minus, r2, LSR, 28, PostIndex},
3328                             false,
3329                             al,
3330                             "al r5 r12 minus r2 LSR 28 PostIndex",
3331                             "al_r5_r12_minus_r2_LSR_28_PostIndex"},
3332                            {{al, r4, r3, minus, r13, ASR, 15, PreIndex},
3333                             false,
3334                             al,
3335                             "al r4 r3 minus r13 ASR 15 PreIndex",
3336                             "al_r4_r3_minus_r13_ASR_15_PreIndex"},
3337                            {{al, r7, r11, minus, r11, LSR, 17, PostIndex},
3338                             false,
3339                             al,
3340                             "al r7 r11 minus r11 LSR 17 PostIndex",
3341                             "al_r7_r11_minus_r11_LSR_17_PostIndex"},
3342                            {{al, r7, r1, minus, r10, LSR, 18, PostIndex},
3343                             false,
3344                             al,
3345                             "al r7 r1 minus r10 LSR 18 PostIndex",
3346                             "al_r7_r1_minus_r10_LSR_18_PostIndex"},
3347                            {{al, r1, r11, minus, r2, ASR, 25, PreIndex},
3348                             false,
3349                             al,
3350                             "al r1 r11 minus r2 ASR 25 PreIndex",
3351                             "al_r1_r11_minus_r2_ASR_25_PreIndex"},
3352                            {{al, r4, r0, minus, r4, ASR, 19, PostIndex},
3353                             false,
3354                             al,
3355                             "al r4 r0 minus r4 ASR 19 PostIndex",
3356                             "al_r4_r0_minus_r4_ASR_19_PostIndex"},
3357                            {{al, r4, r12, minus, r10, LSR, 32, PostIndex},
3358                             false,
3359                             al,
3360                             "al r4 r12 minus r10 LSR 32 PostIndex",
3361                             "al_r4_r12_minus_r10_LSR_32_PostIndex"},
3362                            {{al, r0, r11, plus, r9, ASR, 31, PostIndex},
3363                             false,
3364                             al,
3365                             "al r0 r11 plus r9 ASR 31 PostIndex",
3366                             "al_r0_r11_plus_r9_ASR_31_PostIndex"},
3367                            {{al, r13, r11, plus, r14, ASR, 18, PostIndex},
3368                             false,
3369                             al,
3370                             "al r13 r11 plus r14 ASR 18 PostIndex",
3371                             "al_r13_r11_plus_r14_ASR_18_PostIndex"},
3372                            {{al, r4, r6, plus, r11, LSR, 2, PostIndex},
3373                             false,
3374                             al,
3375                             "al r4 r6 plus r11 LSR 2 PostIndex",
3376                             "al_r4_r6_plus_r11_LSR_2_PostIndex"},
3377                            {{al, r11, r12, plus, r13, LSR, 15, PreIndex},
3378                             false,
3379                             al,
3380                             "al r11 r12 plus r13 LSR 15 PreIndex",
3381                             "al_r11_r12_plus_r13_LSR_15_PreIndex"},
3382                            {{al, r9, r10, minus, r3, LSR, 10, PreIndex},
3383                             false,
3384                             al,
3385                             "al r9 r10 minus r3 LSR 10 PreIndex",
3386                             "al_r9_r10_minus_r3_LSR_10_PreIndex"},
3387                            {{al, r7, r10, plus, r12, LSR, 6, PostIndex},
3388                             false,
3389                             al,
3390                             "al r7 r10 plus r12 LSR 6 PostIndex",
3391                             "al_r7_r10_plus_r12_LSR_6_PostIndex"},
3392                            {{al, r0, r2, plus, r0, LSR, 1, PreIndex},
3393                             false,
3394                             al,
3395                             "al r0 r2 plus r0 LSR 1 PreIndex",
3396                             "al_r0_r2_plus_r0_LSR_1_PreIndex"},
3397                            {{al, r1, r5, minus, r12, LSR, 14, PreIndex},
3398                             false,
3399                             al,
3400                             "al r1 r5 minus r12 LSR 14 PreIndex",
3401                             "al_r1_r5_minus_r12_LSR_14_PreIndex"},
3402                            {{al, r6, r2, minus, r3, LSR, 16, PostIndex},
3403                             false,
3404                             al,
3405                             "al r6 r2 minus r3 LSR 16 PostIndex",
3406                             "al_r6_r2_minus_r3_LSR_16_PostIndex"},
3407                            {{al, r7, r5, plus, r3, LSR, 25, PostIndex},
3408                             false,
3409                             al,
3410                             "al r7 r5 plus r3 LSR 25 PostIndex",
3411                             "al_r7_r5_plus_r3_LSR_25_PostIndex"},
3412                            {{al, r5, r10, plus, r1, LSR, 6, PostIndex},
3413                             false,
3414                             al,
3415                             "al r5 r10 plus r1 LSR 6 PostIndex",
3416                             "al_r5_r10_plus_r1_LSR_6_PostIndex"},
3417                            {{al, r6, r3, minus, r4, ASR, 10, PreIndex},
3418                             false,
3419                             al,
3420                             "al r6 r3 minus r4 ASR 10 PreIndex",
3421                             "al_r6_r3_minus_r4_ASR_10_PreIndex"},
3422                            {{al, r2, r10, plus, r9, ASR, 13, PostIndex},
3423                             false,
3424                             al,
3425                             "al r2 r10 plus r9 ASR 13 PostIndex",
3426                             "al_r2_r10_plus_r9_ASR_13_PostIndex"},
3427                            {{al, r6, r0, plus, r4, LSR, 16, PostIndex},
3428                             false,
3429                             al,
3430                             "al r6 r0 plus r4 LSR 16 PostIndex",
3431                             "al_r6_r0_plus_r4_LSR_16_PostIndex"},
3432                            {{al, r3, r0, minus, r4, LSR, 19, PostIndex},
3433                             false,
3434                             al,
3435                             "al r3 r0 minus r4 LSR 19 PostIndex",
3436                             "al_r3_r0_minus_r4_LSR_19_PostIndex"},
3437                            {{al, r8, r2, minus, r6, LSR, 11, PostIndex},
3438                             false,
3439                             al,
3440                             "al r8 r2 minus r6 LSR 11 PostIndex",
3441                             "al_r8_r2_minus_r6_LSR_11_PostIndex"},
3442                            {{al, r0, r6, plus, r14, LSR, 21, PreIndex},
3443                             false,
3444                             al,
3445                             "al r0 r6 plus r14 LSR 21 PreIndex",
3446                             "al_r0_r6_plus_r14_LSR_21_PreIndex"},
3447                            {{al, r9, r12, plus, r5, ASR, 20, PostIndex},
3448                             false,
3449                             al,
3450                             "al r9 r12 plus r5 ASR 20 PostIndex",
3451                             "al_r9_r12_plus_r5_ASR_20_PostIndex"},
3452                            {{al, r9, r14, minus, r11, ASR, 17, PreIndex},
3453                             false,
3454                             al,
3455                             "al r9 r14 minus r11 ASR 17 PreIndex",
3456                             "al_r9_r14_minus_r11_ASR_17_PreIndex"},
3457                            {{al, r1, r8, minus, r14, LSR, 22, PostIndex},
3458                             false,
3459                             al,
3460                             "al r1 r8 minus r14 LSR 22 PostIndex",
3461                             "al_r1_r8_minus_r14_LSR_22_PostIndex"},
3462                            {{al, r5, r3, minus, r5, LSR, 27, PreIndex},
3463                             false,
3464                             al,
3465                             "al r5 r3 minus r5 LSR 27 PreIndex",
3466                             "al_r5_r3_minus_r5_LSR_27_PreIndex"},
3467                            {{al, r14, r9, plus, r4, LSR, 31, PreIndex},
3468                             false,
3469                             al,
3470                             "al r14 r9 plus r4 LSR 31 PreIndex",
3471                             "al_r14_r9_plus_r4_LSR_31_PreIndex"},
3472                            {{al, r8, r12, plus, r3, LSR, 12, PreIndex},
3473                             false,
3474                             al,
3475                             "al r8 r12 plus r3 LSR 12 PreIndex",
3476                             "al_r8_r12_plus_r3_LSR_12_PreIndex"},
3477                            {{al, r6, r4, minus, r9, ASR, 16, PostIndex},
3478                             false,
3479                             al,
3480                             "al r6 r4 minus r9 ASR 16 PostIndex",
3481                             "al_r6_r4_minus_r9_ASR_16_PostIndex"},
3482                            {{al, r4, r6, plus, r2, LSR, 11, PreIndex},
3483                             false,
3484                             al,
3485                             "al r4 r6 plus r2 LSR 11 PreIndex",
3486                             "al_r4_r6_plus_r2_LSR_11_PreIndex"},
3487                            {{al, r11, r7, plus, r0, ASR, 11, PostIndex},
3488                             false,
3489                             al,
3490                             "al r11 r7 plus r0 ASR 11 PostIndex",
3491                             "al_r11_r7_plus_r0_ASR_11_PostIndex"},
3492                            {{al, r8, r11, minus, r5, LSR, 25, PostIndex},
3493                             false,
3494                             al,
3495                             "al r8 r11 minus r5 LSR 25 PostIndex",
3496                             "al_r8_r11_minus_r5_LSR_25_PostIndex"},
3497                            {{al, r3, r14, minus, r12, LSR, 5, PreIndex},
3498                             false,
3499                             al,
3500                             "al r3 r14 minus r12 LSR 5 PreIndex",
3501                             "al_r3_r14_minus_r12_LSR_5_PreIndex"},
3502                            {{al, r10, r7, minus, r3, ASR, 23, PostIndex},
3503                             false,
3504                             al,
3505                             "al r10 r7 minus r3 ASR 23 PostIndex",
3506                             "al_r10_r7_minus_r3_ASR_23_PostIndex"},
3507                            {{al, r12, r5, minus, r6, ASR, 24, PreIndex},
3508                             false,
3509                             al,
3510                             "al r12 r5 minus r6 ASR 24 PreIndex",
3511                             "al_r12_r5_minus_r6_ASR_24_PreIndex"},
3512                            {{al, r8, r12, minus, r2, ASR, 30, PreIndex},
3513                             false,
3514                             al,
3515                             "al r8 r12 minus r2 ASR 30 PreIndex",
3516                             "al_r8_r12_minus_r2_ASR_30_PreIndex"},
3517                            {{al, r1, r9, minus, r12, LSR, 8, PostIndex},
3518                             false,
3519                             al,
3520                             "al r1 r9 minus r12 LSR 8 PostIndex",
3521                             "al_r1_r9_minus_r12_LSR_8_PostIndex"},
3522                            {{al, r5, r11, plus, r13, LSR, 3, PostIndex},
3523                             false,
3524                             al,
3525                             "al r5 r11 plus r13 LSR 3 PostIndex",
3526                             "al_r5_r11_plus_r13_LSR_3_PostIndex"},
3527                            {{al, r14, r7, plus, r13, LSR, 21, PostIndex},
3528                             false,
3529                             al,
3530                             "al r14 r7 plus r13 LSR 21 PostIndex",
3531                             "al_r14_r7_plus_r13_LSR_21_PostIndex"},
3532                            {{al, r9, r4, minus, r10, LSR, 15, PreIndex},
3533                             false,
3534                             al,
3535                             "al r9 r4 minus r10 LSR 15 PreIndex",
3536                             "al_r9_r4_minus_r10_LSR_15_PreIndex"},
3537                            {{al, r11, r9, plus, r1, LSR, 23, PostIndex},
3538                             false,
3539                             al,
3540                             "al r11 r9 plus r1 LSR 23 PostIndex",
3541                             "al_r11_r9_plus_r1_LSR_23_PostIndex"},
3542                            {{al, r3, r9, minus, r7, ASR, 15, PreIndex},
3543                             false,
3544                             al,
3545                             "al r3 r9 minus r7 ASR 15 PreIndex",
3546                             "al_r3_r9_minus_r7_ASR_15_PreIndex"},
3547                            {{al, r0, r4, minus, r8, ASR, 13, PostIndex},
3548                             false,
3549                             al,
3550                             "al r0 r4 minus r8 ASR 13 PostIndex",
3551                             "al_r0_r4_minus_r8_ASR_13_PostIndex"},
3552                            {{al, r12, r11, minus, r12, LSR, 31, PostIndex},
3553                             false,
3554                             al,
3555                             "al r12 r11 minus r12 LSR 31 PostIndex",
3556                             "al_r12_r11_minus_r12_LSR_31_PostIndex"},
3557                            {{al, r9, r12, minus, r10, LSR, 17, PostIndex},
3558                             false,
3559                             al,
3560                             "al r9 r12 minus r10 LSR 17 PostIndex",
3561                             "al_r9_r12_minus_r10_LSR_17_PostIndex"},
3562                            {{al, r6, r10, minus, r6, LSR, 8, PostIndex},
3563                             false,
3564                             al,
3565                             "al r6 r10 minus r6 LSR 8 PostIndex",
3566                             "al_r6_r10_minus_r6_LSR_8_PostIndex"},
3567                            {{al, r4, r1, plus, r9, ASR, 22, PostIndex},
3568                             false,
3569                             al,
3570                             "al r4 r1 plus r9 ASR 22 PostIndex",
3571                             "al_r4_r1_plus_r9_ASR_22_PostIndex"},
3572                            {{al, r1, r11, minus, r12, ASR, 21, PostIndex},
3573                             false,
3574                             al,
3575                             "al r1 r11 minus r12 ASR 21 PostIndex",
3576                             "al_r1_r11_minus_r12_ASR_21_PostIndex"},
3577                            {{al, r2, r7, plus, r4, ASR, 14, PreIndex},
3578                             false,
3579                             al,
3580                             "al r2 r7 plus r4 ASR 14 PreIndex",
3581                             "al_r2_r7_plus_r4_ASR_14_PreIndex"},
3582                            {{al, r2, r4, minus, r9, ASR, 16, PreIndex},
3583                             false,
3584                             al,
3585                             "al r2 r4 minus r9 ASR 16 PreIndex",
3586                             "al_r2_r4_minus_r9_ASR_16_PreIndex"},
3587                            {{al, r9, r10, plus, r4, LSR, 30, PreIndex},
3588                             false,
3589                             al,
3590                             "al r9 r10 plus r4 LSR 30 PreIndex",
3591                             "al_r9_r10_plus_r4_LSR_30_PreIndex"},
3592                            {{al, r6, r1, plus, r3, LSR, 32, PreIndex},
3593                             false,
3594                             al,
3595                             "al r6 r1 plus r3 LSR 32 PreIndex",
3596                             "al_r6_r1_plus_r3_LSR_32_PreIndex"},
3597                            {{al, r0, r9, plus, r14, ASR, 29, PostIndex},
3598                             false,
3599                             al,
3600                             "al r0 r9 plus r14 ASR 29 PostIndex",
3601                             "al_r0_r9_plus_r14_ASR_29_PostIndex"}};
3602 
3603 // These headers each contain an array of `TestResult` with the reference output
3604 // values. The reference arrays are names `kReference{mnemonic}`.
3605 #include "aarch32/traces/assembler-cond-rd-memop-rs-shift-amount-1to32-ldr-a32.h"
3606 #include "aarch32/traces/assembler-cond-rd-memop-rs-shift-amount-1to32-ldrb-a32.h"
3607 #include "aarch32/traces/assembler-cond-rd-memop-rs-shift-amount-1to32-str-a32.h"
3608 #include "aarch32/traces/assembler-cond-rd-memop-rs-shift-amount-1to32-strb-a32.h"
3609 
3610 
3611 // The maximum number of errors to report in detail for each test.
3612 const unsigned kErrorReportLimit = 8;
3613 
3614 typedef void (MacroAssembler::*Fn)(Condition cond,
3615                                    Register rd,
3616                                    const MemOperand& memop);
3617 
TestHelper(Fn instruction,const char * mnemonic,const TestResult reference[])3618 void TestHelper(Fn instruction,
3619                 const char* mnemonic,
3620                 const TestResult reference[]) {
3621   unsigned total_error_count = 0;
3622   MacroAssembler masm(BUF_SIZE);
3623 
3624   masm.UseA32();
3625 
3626   for (unsigned i = 0; i < ARRAY_SIZE(kTests); i++) {
3627     // Values to pass to the macro-assembler.
3628     Condition cond = kTests[i].operands.cond;
3629     Register rd = kTests[i].operands.rd;
3630     Register rn = kTests[i].operands.rn;
3631     Sign sign = kTests[i].operands.sign;
3632     Register rm = kTests[i].operands.rm;
3633     ShiftType shift = kTests[i].operands.shift;
3634     uint32_t amount = kTests[i].operands.amount;
3635     AddrMode addr_mode = kTests[i].operands.addr_mode;
3636     MemOperand memop(rn, sign, rm, shift, amount, addr_mode);
3637 
3638     int32_t start = masm.GetCursorOffset();
3639     {
3640       // We never generate more that 4 bytes, as IT instructions are only
3641       // allowed for narrow encodings.
3642       ExactAssemblyScope scope(&masm, 4, ExactAssemblyScope::kMaximumSize);
3643       if (kTests[i].in_it_block) {
3644         masm.it(kTests[i].it_condition);
3645       }
3646       (masm.*instruction)(cond, rd, memop);
3647     }
3648     int32_t end = masm.GetCursorOffset();
3649 
3650     const byte* result_ptr =
3651         masm.GetBuffer()->GetOffsetAddress<const byte*>(start);
3652     VIXL_ASSERT(start < end);
3653     uint32_t result_size = end - start;
3654 
3655     if (Test::generate_test_trace()) {
3656       // Print the result bytes.
3657       printf("const byte kInstruction_%s_%s[] = {\n",
3658              mnemonic,
3659              kTests[i].identifier);
3660       for (uint32_t j = 0; j < result_size; j++) {
3661         if (j == 0) {
3662           printf("  0x%02" PRIx8, result_ptr[j]);
3663         } else {
3664           printf(", 0x%02" PRIx8, result_ptr[j]);
3665         }
3666       }
3667       // This comment is meant to be used by external tools to validate
3668       // the encoding. We can parse the comment to figure out what
3669       // instruction this corresponds to.
3670       if (kTests[i].in_it_block) {
3671         printf(" // It %s; %s %s\n};\n",
3672                kTests[i].it_condition.GetName(),
3673                mnemonic,
3674                kTests[i].operands_description);
3675       } else {
3676         printf(" // %s %s\n};\n", mnemonic, kTests[i].operands_description);
3677       }
3678     } else {
3679       // Check we've emitted the exact same encoding as present in the
3680       // trace file. Only print up to `kErrorReportLimit` errors.
3681       if (((result_size != reference[i].size) ||
3682            (memcmp(result_ptr, reference[i].encoding, reference[i].size) !=
3683             0)) &&
3684           (++total_error_count <= kErrorReportLimit)) {
3685         printf("Error when testing \"%s\" with operands \"%s\":\n",
3686                mnemonic,
3687                kTests[i].operands_description);
3688         printf("  Expected: ");
3689         for (uint32_t j = 0; j < reference[i].size; j++) {
3690           if (j == 0) {
3691             printf("0x%02" PRIx8, reference[i].encoding[j]);
3692           } else {
3693             printf(", 0x%02" PRIx8, reference[i].encoding[j]);
3694           }
3695         }
3696         printf("\n");
3697         printf("  Found:    ");
3698         for (uint32_t j = 0; j < result_size; j++) {
3699           if (j == 0) {
3700             printf("0x%02" PRIx8, result_ptr[j]);
3701           } else {
3702             printf(", 0x%02" PRIx8, result_ptr[j]);
3703           }
3704         }
3705         printf("\n");
3706       }
3707     }
3708   }
3709 
3710   masm.FinalizeCode();
3711 
3712   if (Test::generate_test_trace()) {
3713     // Finalize the trace file by writing the final `TestResult` array
3714     // which links all generated instruction encodings.
3715     printf("const TestResult kReference%s[] = {\n", mnemonic);
3716     for (unsigned i = 0; i < ARRAY_SIZE(kTests); i++) {
3717       printf("  {\n");
3718       printf("    ARRAY_SIZE(kInstruction_%s_%s),\n",
3719              mnemonic,
3720              kTests[i].identifier);
3721       printf("    kInstruction_%s_%s,\n", mnemonic, kTests[i].identifier);
3722       printf("  },\n");
3723     }
3724     printf("};\n");
3725   } else {
3726     if (total_error_count > kErrorReportLimit) {
3727       printf("%u other errors follow.\n",
3728              total_error_count - kErrorReportLimit);
3729     }
3730     // Crash if the test failed.
3731     VIXL_CHECK(total_error_count == 0);
3732   }
3733 }
3734 
3735 // Instantiate tests for each instruction in the list.
3736 #define TEST(mnemonic)                                                      \
3737   void Test_##mnemonic() {                                                  \
3738     TestHelper(&MacroAssembler::mnemonic, #mnemonic, kReference##mnemonic); \
3739   }                                                                         \
3740   Test test_##mnemonic(                                                     \
3741       "AARCH32_ASSEMBLER_COND_RD_MEMOP_RS_SHIFT_AMOUNT_1TO32_" #mnemonic    \
3742       "_A32",                                                               \
3743       &Test_##mnemonic);
3744 FOREACH_INSTRUCTION(TEST)
3745 #undef TEST
3746 
3747 }  // namespace
3748 #endif
3749 
3750 }  // namespace aarch32
3751 }  // namespace vixl
3752