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/external/swiftshader/third_party/LLVM/test/CodeGen/X86/
Drotate.ll4 define i32 @rotl32(i32 %A, i8 %Amt) {
5 %shift.upgrd.1 = zext i8 %Amt to i32 ; <i32> [#uses=1]
7 %Amt2 = sub i8 32, %Amt ; <i8> [#uses=1]
14 define i32 @rotr32(i32 %A, i8 %Amt) {
15 %shift.upgrd.3 = zext i8 %Amt to i32 ; <i32> [#uses=1]
17 %Amt2 = sub i8 32, %Amt ; <i8> [#uses=1]
38 define i16 @rotl16(i16 %A, i8 %Amt) {
39 %shift.upgrd.5 = zext i8 %Amt to i16 ; <i16> [#uses=1]
41 %Amt2 = sub i8 16, %Amt ; <i8> [#uses=1]
48 define i16 @rotr16(i16 %A, i8 %Amt) {
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/external/llvm/test/CodeGen/X86/
Drotate.ll4 define i32 @rotl32(i32 %A, i8 %Amt) {
5 %shift.upgrd.1 = zext i8 %Amt to i32 ; <i32> [#uses=1]
7 %Amt2 = sub i8 32, %Amt ; <i8> [#uses=1]
14 define i32 @rotr32(i32 %A, i8 %Amt) {
15 %shift.upgrd.3 = zext i8 %Amt to i32 ; <i32> [#uses=1]
17 %Amt2 = sub i8 32, %Amt ; <i8> [#uses=1]
38 define i16 @rotl16(i16 %A, i8 %Amt) {
39 %shift.upgrd.5 = zext i8 %Amt to i16 ; <i16> [#uses=1]
41 %Amt2 = sub i8 16, %Amt ; <i8> [#uses=1]
48 define i16 @rotr16(i16 %A, i8 %Amt) {
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Dlegalize-shl-vec.ll4 %Amt = insertelement <2 x i256> undef, i256 -1, i32 0
5 %Out = shl <2 x i256> %In, %Amt
21 %Amt = insertelement <2 x i256> undef, i256 -1, i32 0
22 %Out = lshr <2 x i256> %In, %Amt
38 %Amt = insertelement <2 x i256> undef, i256 -1, i32 0
39 %Out = ashr <2 x i256> %In, %Amt
/external/swiftshader/third_party/LLVM/test/CodeGen/PowerPC/
Drotl-2.ll5 define i32 @rotl32(i32 %A, i8 %Amt) nounwind {
6 %shift.upgrd.1 = zext i8 %Amt to i32 ; <i32> [#uses=1]
8 %Amt2 = sub i8 32, %Amt ; <i8> [#uses=1]
15 define i32 @rotr32(i32 %A, i8 %Amt) nounwind {
16 %shift.upgrd.3 = zext i8 %Amt to i32 ; <i32> [#uses=1]
18 %Amt2 = sub i8 32, %Amt ; <i8> [#uses=1]
Drotl-64.ll12 define i64 @t2(i64 %A, i8 zeroext %Amt) {
13 %Amt1 = zext i8 %Amt to i64
15 %Amt2 = sub i8 64, %Amt
/external/llvm/test/CodeGen/PowerPC/
Drotl-2.ll6 define i32 @rotl32(i32 %A, i8 %Amt) nounwind {
7 %shift.upgrd.1 = zext i8 %Amt to i32 ; <i32> [#uses=1]
9 %Amt2 = sub i8 32, %Amt ; <i8> [#uses=1]
16 define i32 @rotr32(i32 %A, i8 %Amt) nounwind {
17 %shift.upgrd.3 = zext i8 %Amt to i32 ; <i32> [#uses=1]
19 %Amt2 = sub i8 32, %Amt ; <i8> [#uses=1]
Drotl-64.ll12 define i64 @t2(i64 %A, i8 zeroext %Amt) {
13 %Amt1 = zext i8 %Amt to i64
15 %Amt2 = sub i8 64, %Amt
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/
Drotl-2.ll6 define i32 @rotl32(i32 %A, i8 %Amt) nounwind {
7 %shift.upgrd.1 = zext i8 %Amt to i32 ; <i32> [#uses=1]
9 %Amt2 = sub i8 32, %Amt ; <i8> [#uses=1]
16 define i32 @rotr32(i32 %A, i8 %Amt) nounwind {
17 %shift.upgrd.3 = zext i8 %Amt to i32 ; <i32> [#uses=1]
19 %Amt2 = sub i8 32, %Amt ; <i8> [#uses=1]
Drotl-64.ll12 define i64 @t2(i64 %A, i8 zeroext %Amt) {
13 %Amt1 = zext i8 %Amt to i64
15 %Amt2 = sub i8 64, %Amt
/external/swiftshader/third_party/LLVM/test/CodeGen/CellSPU/
Drotate_ops.ll64 define i32 @rotr32_1(i32 %A, i8 %Amt) {
65 %tmp1 = zext i8 %Amt to i32 ; <i32> [#uses=1]
67 %Amt2 = sub i8 32, %Amt ; <i8> [#uses=1]
74 define i32 @rotr32_2(i32 %A, i8 %Amt) {
75 %Amt2 = sub i8 32, %Amt ; <i8> [#uses=1]
76 %tmp1 = zext i8 %Amt to i32 ; <i32> [#uses=1]
133 define i8 @rotl8(i8 %A, i8 %Amt) {
134 %B = shl i8 %A, %Amt ; <i8> [#uses=1]
135 %Amt2 = sub i8 8, %Amt ; <i8> [#uses=1]
141 define i8 @rotr8(i8 %A, i8 %Amt) {
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/MCTargetDesc/
DARMAddressingModes.h85 static inline unsigned rotr32(unsigned Val, unsigned Amt) { in rotr32() argument
86 assert(Amt < 32 && "Invalid rotate amount"); in rotr32()
87 return (Val >> Amt) | (Val << ((32-Amt)&31)); in rotr32()
92 static inline unsigned rotl32(unsigned Val, unsigned Amt) { in rotl32() argument
93 assert(Amt < 32 && "Invalid rotate amount"); in rotl32()
94 return (Val << Amt) | (Val >> ((32-Amt)&31)); in rotl32()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Drotate.ll5 define i64 @rotl64(i64 %A, i8 %Amt) nounwind {
49 %shift.upgrd.1 = zext i8 %Amt to i64
51 %Amt2 = sub i8 64, %Amt
58 define i64 @rotr64(i64 %A, i8 %Amt) nounwind {
102 %shift.upgrd.3 = zext i8 %Amt to i64
104 %Amt2 = sub i8 64, %Amt
195 define i32 @rotl32(i32 %A, i8 %Amt) nounwind {
209 %shift.upgrd.1 = zext i8 %Amt to i32
211 %Amt2 = sub i8 32, %Amt
218 define i32 @rotr32(i32 %A, i8 %Amt) nounwind {
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/external/swiftshader/third_party/LLVM/include/llvm/ADT/
DAPSInt.h114 APSInt operator>>(unsigned Amt) const {
115 return IsUnsigned ? APSInt(lshr(Amt), true) : APSInt(ashr(Amt), false);
117 APSInt& operator>>=(unsigned Amt) {
118 *this = *this >> Amt;
145 APSInt& operator<<=(unsigned Amt) {
146 *this = *this << Amt;
/external/llvm/lib/Target/ARM/MCTargetDesc/
DARMAddressingModes.h86 static inline unsigned rotr32(unsigned Val, unsigned Amt) { in rotr32() argument
87 assert(Amt < 32 && "Invalid rotate amount"); in rotr32()
88 return (Val >> Amt) | (Val << ((32-Amt)&31)); in rotr32()
93 static inline unsigned rotl32(unsigned Val, unsigned Amt) { in rotl32() argument
94 assert(Amt < 32 && "Invalid rotate amount"); in rotl32()
95 return (Val << Amt) | (Val >> ((32-Amt)&31)); in rotl32()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/MCTargetDesc/
DARMAddressingModes.h84 inline unsigned rotr32(unsigned Val, unsigned Amt) { in rotr32() argument
85 assert(Amt < 32 && "Invalid rotate amount"); in rotr32()
86 return (Val >> Amt) | (Val << ((32-Amt)&31)); in rotr32()
91 inline unsigned rotl32(unsigned Val, unsigned Amt) { in rotl32() argument
92 assert(Amt < 32 && "Invalid rotate amount"); in rotl32()
93 return (Val << Amt) | (Val >> ((32-Amt)&31)); in rotl32()
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/ADT/
DAPSInt.h124 APSInt operator>>(unsigned Amt) const {
125 return IsUnsigned ? APSInt(lshr(Amt), true) : APSInt(ashr(Amt), false);
127 APSInt& operator>>=(unsigned Amt) {
129 lshrInPlace(Amt);
131 ashrInPlace(Amt);
184 APSInt& operator<<=(unsigned Amt) {
185 static_cast<APInt&>(*this) <<= Amt;
/external/capstone/arch/ARM/
DARMAddressingModes.h87 static inline unsigned rotr32(unsigned Val, unsigned Amt) in rotr32() argument
90 return (Val >> Amt) | (Val << ((32-Amt)&31)); in rotr32()
95 static inline unsigned rotl32(unsigned Val, unsigned Amt) in rotl32() argument
98 return (Val << Amt) | (Val >> ((32-Amt)&31)); in rotl32()
/external/clang/lib/Analysis/
DFormatString.cpp83 const OptionalAmount &Amt = ParseAmount(I, E); in ParsePositionAmount() local
85 if (Amt.getHowSpecified() == OptionalAmount::NotSpecified) { in ParsePositionAmount()
96 assert(Amt.getHowSpecified() == OptionalAmount::Constant); in ParsePositionAmount()
102 if (Amt.getConstantAmount() == 0) { in ParsePositionAmount()
110 return OptionalAmount(OptionalAmount::Arg, Amt.getConstantAmount() - 1, in ParsePositionAmount()
133 const OptionalAmount Amt = in ParseFieldWidth() local
137 if (Amt.isInvalid()) in ParseFieldWidth()
139 CS.setFieldWidth(Amt); in ParseFieldWidth()
152 const OptionalAmount &Amt = ParseAmount(I, E); in ParseArgPosition() local
160 if (Amt.getHowSpecified() == OptionalAmount::Constant && *(I++) == '$') { in ParseArgPosition()
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/external/clang/lib/StaticAnalyzer/Core/
DBasicValueFactory.cpp182 uint64_t Amt = V2.getZExtValue(); in evalAPSInt() local
184 if (Amt >= V1.getBitWidth()) in evalAPSInt()
187 return &getValue( V1.operator<<( (unsigned) Amt )); in evalAPSInt()
200 uint64_t Amt = V2.getZExtValue(); in evalAPSInt() local
202 if (Amt >= V1.getBitWidth()) in evalAPSInt()
205 return &getValue( V1.operator>>( (unsigned) Amt )); in evalAPSInt()
/external/llvm/include/llvm/ADT/
DAPSInt.h124 APSInt operator>>(unsigned Amt) const {
125 return IsUnsigned ? APSInt(lshr(Amt), true) : APSInt(ashr(Amt), false);
127 APSInt& operator>>=(unsigned Amt) {
128 *this = *this >> Amt;
181 APSInt& operator<<=(unsigned Amt) {
182 *this = *this << Amt;
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Generic/
Dshift-int64.ll8 define i64 @test_variable(i64 %X, i8 %Amt) {
9 %shift.upgrd.1 = zext i8 %Amt to i64 ; <i64> [#uses=1]
/external/llvm/test/CodeGen/Generic/
Dshift-int64.ll8 define i64 @test_variable(i64 %X, i8 %Amt) {
9 %shift.upgrd.1 = zext i8 %Amt to i64 ; <i64> [#uses=1]
/external/swiftshader/third_party/LLVM/test/CodeGen/Generic/
Dshift-int64.ll8 define i64 @test_variable(i64 %X, i8 %Amt) {
9 %shift.upgrd.1 = zext i8 %Amt to i64 ; <i64> [#uses=1]
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DLegalizeIntegerTypes.cpp1254 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt, in ExpandShiftByConstant() argument
1267 if (Amt > VTBits) { in ExpandShiftByConstant()
1269 } else if (Amt > NVTBits) { in ExpandShiftByConstant()
1272 NVT, InL, DAG.getConstant(Amt-NVTBits, ShTy)); in ExpandShiftByConstant()
1273 } else if (Amt == NVTBits) { in ExpandShiftByConstant()
1276 } else if (Amt == 1 && in ExpandShiftByConstant()
1286 Lo = DAG.getNode(ISD::SHL, DL, NVT, InL, DAG.getConstant(Amt, ShTy)); in ExpandShiftByConstant()
1289 DAG.getConstant(Amt, ShTy)), in ExpandShiftByConstant()
1291 DAG.getConstant(NVTBits-Amt, ShTy))); in ExpandShiftByConstant()
1297 if (Amt > VTBits) { in ExpandShiftByConstant()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Transforms/InstCombine/
DInstCombineCasts.cpp128 Value *Amt = nullptr; in PromoteCastOfAllocation() local
130 Amt = NumElements; in PromoteCastOfAllocation()
132 Amt = ConstantInt::get(AI.getArraySize()->getType(), Scale); in PromoteCastOfAllocation()
134 Amt = AllocaBuilder.CreateMul(Amt, NumElements); in PromoteCastOfAllocation()
140 Amt = AllocaBuilder.CreateAdd(Amt, Off); in PromoteCastOfAllocation()
143 AllocaInst *New = AllocaBuilder.CreateAlloca(CastElTy, Amt); in PromoteCastOfAllocation()
379 const APInt *Amt; in canEvaluateTruncated() local
380 if (match(I->getOperand(1), m_APInt(Amt))) { in canEvaluateTruncated()
382 if (Amt->getLimitedValue(BitWidth) < BitWidth) in canEvaluateTruncated()
391 const APInt *Amt; in canEvaluateTruncated() local
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