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Searched refs:BEGIN_BATCH (Results 1 – 25 of 48) sorted by relevance

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/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_misc_state.c61 BEGIN_BATCH(1); in upload_pipelined_state_pointers()
66 BEGIN_BATCH(7); in upload_pipelined_state_pointers()
381 BEGIN_BATCH(len); in brw_emit_depth_stencil_hiz()
438 BEGIN_BATCH(2); in brw_emit_select_pipeline()
484 BEGIN_BATCH(1); in brw_emit_select_pipeline()
490 BEGIN_BATCH(1); in brw_emit_select_pipeline()
509 BEGIN_BATCH(7); in brw_emit_select_pipeline()
549 BEGIN_BATCH(3); in brw_upload_invariant_state()
555 BEGIN_BATCH(2); in brw_upload_invariant_state()
563 BEGIN_BATCH(3); in brw_upload_invariant_state()
[all …]
Dbrw_compute.c52 BEGIN_BATCH(7); in prepare_indirect_gpgpu_walker()
66 BEGIN_BATCH(1); in prepare_indirect_gpgpu_walker()
77 BEGIN_BATCH(1); in prepare_indirect_gpgpu_walker()
88 BEGIN_BATCH(1); in prepare_indirect_gpgpu_walker()
96 BEGIN_BATCH(1); in prepare_indirect_gpgpu_walker()
135 BEGIN_BATCH(dwords); in brw_emit_gpgpu_walker()
159 BEGIN_BATCH(2); in brw_emit_gpgpu_walker()
Dgen6_depth_state.c110 BEGIN_BATCH(7); in gen6_emit_depth_stencil_hiz()
166 BEGIN_BATCH(3); in gen6_emit_depth_stencil_hiz()
172 BEGIN_BATCH(3); in gen6_emit_depth_stencil_hiz()
188 BEGIN_BATCH(3); in gen6_emit_depth_stencil_hiz()
194 BEGIN_BATCH(3); in gen6_emit_depth_stencil_hiz()
210 BEGIN_BATCH(2); in gen6_emit_depth_stencil_hiz()
Dgen7_misc_state.c104 BEGIN_BATCH(7); in gen7_emit_depth_stencil_hiz()
141 BEGIN_BATCH(3); in gen7_emit_depth_stencil_hiz()
149 BEGIN_BATCH(3); in gen7_emit_depth_stencil_hiz()
158 BEGIN_BATCH(3); in gen7_emit_depth_stencil_hiz()
167 BEGIN_BATCH(3); in gen7_emit_depth_stencil_hiz()
176 BEGIN_BATCH(3); in gen7_emit_depth_stencil_hiz()
Dhsw_sol.c103 BEGIN_BATCH(9); in tally_prims_written()
126 BEGIN_BATCH(5); in tally_prims_written()
135 BEGIN_BATCH(9); in tally_prims_written()
172 BEGIN_BATCH(1 + 2 * BRW_MAX_XFB_STREAMS); in hsw_begin_transform_feedback()
207 BEGIN_BATCH(3); in hsw_pause_transform_feedback()
234 BEGIN_BATCH(3); in hsw_resume_transform_feedback()
Dgen8_depth_state.c64 BEGIN_BATCH(8); in emit_depth_packets()
86 BEGIN_BATCH(5); in emit_depth_packets()
95 BEGIN_BATCH(5); in emit_depth_packets()
104 BEGIN_BATCH(5); in emit_depth_packets()
112 BEGIN_BATCH(5); in emit_depth_packets()
121 BEGIN_BATCH(3); in emit_depth_packets()
Dhsw_queryobj.c76 BEGIN_BATCH(1 + ARRAY_SIZE(maths)); in mult_gpr0_by_80()
101 BEGIN_BATCH(1 + ARRAY_SIZE(maths)); in keep_gpr0_lower_n_bits()
132 BEGIN_BATCH(batch_len); in shl_gpr0_by_30_bits()
180 BEGIN_BATCH(1 + ARRAY_SIZE(maths)); in gpr0_to_bool()
236 BEGIN_BATCH(1 + ARRAY_SIZE(maths)); in calc_overflow_for_stream()
319 BEGIN_BATCH(5); in hsw_result_to_gpr0()
396 BEGIN_BATCH(1); in set_predicate()
419 BEGIN_BATCH(dwords * cmd_size); in store_query_result_reg()
Dbrw_binding_tables.c88 BEGIN_BATCH(2); in brw_upload_binding_table()
251 BEGIN_BATCH(6); in gen4_upload_binding_table_pointers()
281 BEGIN_BATCH(4); in gen6_upload_binding_table_pointers()
Dintel_batchbuffer.c763 BEGIN_BATCH(2); in brw_finish_batch()
1206 BEGIN_BATCH(4 * size); in load_sized_register_mem()
1214 BEGIN_BATCH(3 * size); in load_sized_register_mem()
1254 BEGIN_BATCH(4); in brw_store_register_mem32()
1260 BEGIN_BATCH(3); in brw_store_register_mem32()
1283 BEGIN_BATCH(8); in brw_store_register_mem64()
1292 BEGIN_BATCH(6); in brw_store_register_mem64()
1311 BEGIN_BATCH(3); in brw_load_register_imm32()
1326 BEGIN_BATCH(5); in brw_load_register_imm64()
1343 BEGIN_BATCH(3); in brw_load_register_reg()
[all …]
Dgen7_sol_state.c113 BEGIN_BATCH(3); in gen7_pause_transform_feedback()
140 BEGIN_BATCH(3); in gen7_resume_transform_feedback()
Dbrw_pipe_control.c164 BEGIN_BATCH(6); in brw_emit_pipe_control()
195 BEGIN_BATCH(5); in brw_emit_pipe_control()
207 BEGIN_BATCH(4); in brw_emit_pipe_control()
Dbrw_curbe.c167 BEGIN_BATCH(2); in brw_upload_cs_urb_state()
305 BEGIN_BATCH(2); in brw_upload_constant_buffer()
335 BEGIN_BATCH(2); in brw_upload_constant_buffer()
Dgen6_sol.c419 BEGIN_BATCH(4); in brw_begin_transform_feedback()
431 BEGIN_BATCH(4); in brw_begin_transform_feedback()
501 BEGIN_BATCH(4); in brw_resume_transform_feedback()
513 BEGIN_BATCH(4); in brw_resume_transform_feedback()
Dgen7_urb.c121 BEGIN_BATCH(10); in gen7_emit_push_constant_state()
230 BEGIN_BATCH(8); in gen7_upload_urb()
Dgen6_sampler_state.c36 BEGIN_BATCH(4); in upload_sampler_state_pointers()
/external/mesa3d/src/gallium/drivers/i915/
Di915_blit.c74 if (!BEGIN_BATCH(6)) { in i915_fill_blit()
76 assert(BEGIN_BATCH(6)); in i915_fill_blit()
146 if (!BEGIN_BATCH(8)) { in i915_copy_blit()
148 assert(BEGIN_BATCH(8)); in i915_copy_blit()
Di915_clear.c124 if (!BEGIN_BATCH(1 + 2*(7 + 7))) { in i915_clear_emit()
130 assert(BEGIN_BATCH(1 + 2*(7 + 7))); in i915_clear_emit()
175 if (!BEGIN_BATCH(1 + 7 + 7)) { in i915_clear_emit()
181 assert(BEGIN_BATCH(1 + 7 + 7)); in i915_clear_emit()
Di915_prim_vbuf.c468 if (!BEGIN_BATCH(1 + (nr_indices + 1)/2)) { in draw_arrays_fallback()
476 if (!BEGIN_BATCH(1 + (nr_indices + 1)/2)) { in draw_arrays_fallback()
516 if (!BEGIN_BATCH(2)) { in i915_vbuf_render_draw_arrays()
524 if (!BEGIN_BATCH(2)) { in i915_vbuf_render_draw_arrays()
636 if (!BEGIN_BATCH(1 + (nr_indices + 1)/2)) { in i915_vbuf_render_draw_elements()
644 if (!BEGIN_BATCH(1 + (nr_indices + 1)/2)) { in i915_vbuf_render_draw_elements()
Di915_prim_emit.c147 if (!BEGIN_BATCH( 1 + nr * vertex_size / 4)) { in emit_prim()
154 if (!BEGIN_BATCH( 1 + nr * vertex_size / 4)) { in emit_prim()
Di915_batch.h35 #define BEGIN_BATCH(dwords) \ macro
/external/mesa3d/src/mesa/drivers/dri/radeon/
Dradeon_ioctl.c101 BEGIN_BATCH(6); in radeonEmitScissor()
112 BEGIN_BATCH(2); in radeonEmitScissor()
135 BEGIN_BATCH(8); in radeonEmitVbufPrim()
154 BEGIN_BATCH(4); in radeonEmitVbufPrim()
237 BEGIN_BATCH(2+ELTS_BUFSZ(align_min_nr)/4); in radeonAllocEltsOpenEnded()
247 BEGIN_BATCH(ELTS_BUFSZ(align_min_nr)/4); in radeonAllocEltsOpenEnded()
289 BEGIN_BATCH(7); in radeonEmitVertexAOS()
320 BEGIN_BATCH(sz+2+(nr * 2)); in radeonEmitAOS()
Dradeon_blit.c93 BEGIN_BATCH(8); in emit_vtx_state()
134 BEGIN_BATCH(18); in emit_tx_setup()
209 BEGIN_BATCH(18); in emit_cb_setup()
297 BEGIN_BATCH(15); in emit_draw_packet()
/external/mesa3d/src/mesa/drivers/dri/r200/
Dr200_blit.c99 BEGIN_BATCH(14); in emit_vtx_state()
167 BEGIN_BATCH(10); in emit_tx_setup()
188 BEGIN_BATCH(10); in emit_tx_setup()
218 BEGIN_BATCH(34); in emit_tx_setup()
291 BEGIN_BATCH(18); in emit_tx_setup()
359 BEGIN_BATCH(22); in emit_cb_setup()
449 BEGIN_BATCH(14); in emit_draw_packet()
Dr200_cmdbuf.c130 BEGIN_BATCH(3); in r200EmitVbufPrim()
142 BEGIN_BATCH(8+2); in r200FireEB()
214 BEGIN_BATCH(2); in r200EmitMaxVtxIndex()
231 BEGIN_BATCH(7); in r200EmitVertexAOS()
250 BEGIN_BATCH(sz+2+ (nr*2)); in r200EmitAOS()
/external/mesa3d/src/mesa/drivers/dri/i915/
Dintel_blit.c319 BEGIN_BATCH(8); in intelEmitCopyBlit()
494 BEGIN_BATCH(6); in intelClearWithBlit()
564 BEGIN_BATCH(8 + 3); in intelEmitImmediateColorExpandBlit()
678 BEGIN_BATCH(6); in intel_miptree_set_alpha_to_one()

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