1 /*
2 * Copyright © 2011 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "main/mtypes.h"
25 #include "intel_batchbuffer.h"
26 #include "intel_mipmap_tree.h"
27 #include "intel_fbo.h"
28 #include "brw_context.h"
29 #include "brw_state.h"
30 #include "brw_defines.h"
31
32 void
gen7_emit_depth_stencil_hiz(struct brw_context * brw,struct intel_mipmap_tree * depth_mt,uint32_t depth_offset,uint32_t depthbuffer_format,uint32_t depth_surface_type,struct intel_mipmap_tree * stencil_mt,bool hiz,bool separate_stencil,uint32_t width,uint32_t height,uint32_t tile_x,uint32_t tile_y)33 gen7_emit_depth_stencil_hiz(struct brw_context *brw,
34 struct intel_mipmap_tree *depth_mt,
35 uint32_t depth_offset, uint32_t depthbuffer_format,
36 uint32_t depth_surface_type,
37 struct intel_mipmap_tree *stencil_mt,
38 bool hiz, bool separate_stencil,
39 uint32_t width, uint32_t height,
40 uint32_t tile_x, uint32_t tile_y)
41 {
42 const struct gen_device_info *devinfo = &brw->screen->devinfo;
43 struct gl_context *ctx = &brw->ctx;
44 const uint8_t mocs = GEN7_MOCS_L3;
45 struct gl_framebuffer *fb = ctx->DrawBuffer;
46 uint32_t surftype;
47 unsigned int depth = 1;
48 unsigned int min_array_element;
49 GLenum gl_target = GL_TEXTURE_2D;
50 unsigned int lod;
51 const struct intel_mipmap_tree *mt = depth_mt ? depth_mt : stencil_mt;
52 const struct intel_renderbuffer *irb = NULL;
53 const struct gl_renderbuffer *rb = NULL;
54
55 /* Skip repeated NULL depth/stencil emits (think 2D rendering). */
56 if (!mt && brw->no_depth_or_stencil) {
57 assert(brw->hw_ctx);
58 return;
59 }
60
61 brw_emit_depth_stall_flushes(brw);
62
63 irb = intel_get_renderbuffer(fb, BUFFER_DEPTH);
64 if (!irb)
65 irb = intel_get_renderbuffer(fb, BUFFER_STENCIL);
66 rb = (struct gl_renderbuffer*) irb;
67
68 if (rb) {
69 depth = MAX2(irb->layer_count, 1);
70 if (rb->TexImage)
71 gl_target = rb->TexImage->TexObject->Target;
72 }
73
74 switch (gl_target) {
75 case GL_TEXTURE_CUBE_MAP_ARRAY:
76 case GL_TEXTURE_CUBE_MAP:
77 /* The PRM claims that we should use BRW_SURFACE_CUBE for this
78 * situation, but experiments show that gl_Layer doesn't work when we do
79 * this. So we use BRW_SURFACE_2D, since for rendering purposes this is
80 * equivalent.
81 */
82 surftype = BRW_SURFACE_2D;
83 depth *= 6;
84 break;
85 case GL_TEXTURE_3D:
86 assert(mt);
87 depth = mt->surf.logical_level0_px.depth;
88 /* fallthrough */
89 default:
90 surftype = translate_tex_target(gl_target);
91 break;
92 }
93
94 min_array_element = irb ? irb->mt_layer : 0;
95
96 lod = irb ? irb->mt_level - irb->mt->first_level : 0;
97
98 if (mt) {
99 width = mt->surf.logical_level0_px.width;
100 height = mt->surf.logical_level0_px.height;
101 }
102
103 /* _NEW_DEPTH, _NEW_STENCIL, _NEW_BUFFERS */
104 BEGIN_BATCH(7);
105 /* 3DSTATE_DEPTH_BUFFER dw0 */
106 OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
107
108 /* 3DSTATE_DEPTH_BUFFER dw1 */
109 OUT_BATCH((depth_mt ? depth_mt->surf.row_pitch - 1 : 0) |
110 (depthbuffer_format << 18) |
111 ((hiz ? 1 : 0) << 22) |
112 ((stencil_mt != NULL && brw->stencil_write_enabled) << 27) |
113 (brw_depth_writes_enabled(brw) << 28) |
114 (surftype << 29));
115
116 /* 3DSTATE_DEPTH_BUFFER dw2 */
117 if (depth_mt) {
118 OUT_RELOC(depth_mt->bo, RELOC_WRITE, 0);
119 } else {
120 OUT_BATCH(0);
121 }
122
123 /* 3DSTATE_DEPTH_BUFFER dw3 */
124 OUT_BATCH(((width - 1) << 4) |
125 ((height - 1) << 18) |
126 lod);
127
128 /* 3DSTATE_DEPTH_BUFFER dw4 */
129 OUT_BATCH(((depth - 1) << 21) |
130 (min_array_element << 10) |
131 mocs);
132
133 /* 3DSTATE_DEPTH_BUFFER dw5 */
134 OUT_BATCH(0);
135
136 /* 3DSTATE_DEPTH_BUFFER dw6 */
137 OUT_BATCH((depth - 1) << 21);
138 ADVANCE_BATCH();
139
140 if (!hiz) {
141 BEGIN_BATCH(3);
142 OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
143 OUT_BATCH(0);
144 OUT_BATCH(0);
145 ADVANCE_BATCH();
146 } else {
147 assert(depth_mt);
148
149 BEGIN_BATCH(3);
150 OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
151 OUT_BATCH((mocs << 25) |
152 (depth_mt->hiz_buf->pitch - 1));
153 OUT_RELOC(depth_mt->hiz_buf->bo, RELOC_WRITE, 0);
154 ADVANCE_BATCH();
155 }
156
157 if (stencil_mt == NULL) {
158 BEGIN_BATCH(3);
159 OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2));
160 OUT_BATCH(0);
161 OUT_BATCH(0);
162 ADVANCE_BATCH();
163 } else {
164 stencil_mt->r8stencil_needs_update = true;
165 const int enabled = devinfo->is_haswell ? HSW_STENCIL_ENABLED : 0;
166
167 BEGIN_BATCH(3);
168 OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2));
169 OUT_BATCH(enabled |
170 mocs << 25 |
171 (stencil_mt->surf.row_pitch - 1));
172 OUT_RELOC(stencil_mt->bo, RELOC_WRITE, 0);
173 ADVANCE_BATCH();
174 }
175
176 BEGIN_BATCH(3);
177 OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS << 16 | (3 - 2));
178 if (depth_mt) {
179 OUT_BATCH(brw_convert_depth_value(depth_mt->format,
180 depth_mt->fast_clear_color.f32[0]));
181 } else {
182 OUT_BATCH(0);
183 }
184 OUT_BATCH(1);
185 ADVANCE_BATCH();
186
187 brw->no_depth_or_stencil = !mt;
188 }
189
190 /**
191 * \see brw_context.state.depth_region
192 */
193 const struct brw_tracked_state gen7_depthbuffer = {
194 .dirty = {
195 .mesa = _NEW_BUFFERS |
196 _NEW_DEPTH |
197 _NEW_STENCIL,
198 .brw = BRW_NEW_BATCH |
199 BRW_NEW_BLORP,
200 },
201 .emit = brw_emit_depthbuffer,
202 };
203