/external/swiftshader/third_party/llvm-7.0/llvm/unittests/ObjectYAML/ |
D | YAMLTest.cpp | 24 static void mapping(IO &IO, BinaryHolder &BH) { in mapping() 25 IO.mapRequired("Binary", BH.Binary); in mapping() 32 BinaryHolder BH; in TEST() local 36 YOut << BH; in TEST()
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/external/llvm/unittests/ObjectYAML/ |
D | YAMLTest.cpp | 24 static void mapping(IO &IO, BinaryHolder &BH) { in mapping() 25 IO.mapRequired("Binary", BH.Binary); in mapping() 32 BinaryHolder BH; in TEST() local 36 YOut << BH; in TEST()
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/external/llvm/test/CodeGen/Generic/ |
D | i128-addsub.ll | 3 define void @test_add(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) { 10 %tmp89 = zext i64 %BH to i128 ; <i128> [#uses=1] 22 define void @test_sub(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) { 29 %tmp89 = zext i64 %BH to i128 ; <i128> [#uses=1]
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Generic/ |
D | i128-addsub.ll | 3 define void @test_add(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) { 10 %tmp89 = zext i64 %BH to i128 ; <i128> [#uses=1] 22 define void @test_sub(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) { 29 %tmp89 = zext i64 %BH to i128 ; <i128> [#uses=1]
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/external/swiftshader/third_party/LLVM/test/CodeGen/Generic/ |
D | i128-addsub.ll | 3 define void @test_add(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) { 10 %tmp89 = zext i64 %BH to i128 ; <i128> [#uses=1] 22 define void @test_sub(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) { 29 %tmp89 = zext i64 %BH to i128 ; <i128> [#uses=1]
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/external/swiftshader/third_party/LLVM/test/CodeGen/Blackfin/ |
D | addsub-i128.ll | 6 define void @test_add(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) { 13 %tmp89 = zext i64 %BH to i128 ; <i128> [#uses=1] 25 define void @test_sub(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) { 32 %tmp89 = zext i64 %BH to i128 ; <i128> [#uses=1]
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/external/libvpx/libvpx/vp9/encoder/ |
D | vp9_temporal_filter.c | 45 int i, j, k = 0, ys = (BH >> 1), xs = (BW >> 1); in temporal_filter_predictors_mb_c() 66 scale, BW, BH, which_mv, kernel, in temporal_filter_predictors_mb_c() 84 BH, which_mv, kernel, MV_PRECISION_Q3, x, y); in temporal_filter_predictors_mb_c() 101 for (i = 0; i < BH; i += ys) { in temporal_filter_predictors_mb_c() 548 BH, USE_8_TAPS_SHARP); in temporal_filter_find_matching_mb_c() 556 for (i = 0; i < BH; i += SUB_BH) { in temporal_filter_find_matching_mb_c() 601 int mb_rows = (frames[alt_ref_index]->y_crop_height + BH - 1) >> BH_LOG2; in vp9_temporal_filter_iterate_row_c() 614 const int mb_uv_height = BH >> mbd->plane[1].subsampling_y; in vp9_temporal_filter_iterate_row_c() 617 int mb_y_offset = mb_row * BH * (f->y_stride) + BW * mb_col_start; in vp9_temporal_filter_iterate_row_c() 640 td->mb.mv_limits.row_min = -((mb_row * BH) + (17 - 2 * VP9_INTERP_EXTEND)); in vp9_temporal_filter_iterate_row_c() [all …]
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D | vp9_temporal_filter.h | 23 #define BH 32 macro
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/external/libaom/libaom/av1/encoder/ |
D | temporal_filter.c | 79 BH, &conv_params, interp_filters, &warp_types, x, in temporal_filter_predictors_mb_c() 98 int i, j, k = 0, ys = (BH >> 1), xs = (BW >> 1); in temporal_filter_predictors_mb_c() 100 for (i = 0; i < BH; i += ys) { in temporal_filter_predictors_mb_c() 734 0, 0, BW, BH, USE_8_TAPS, 1); in temporal_filter_find_matching_mb_c() 745 for (i = 0; i < BH; i += SUB_BH) { in temporal_filter_find_matching_mb_c() 790 int mb_rows = (frames[alt_ref_index]->y_crop_height + BH - 1) >> BH_LOG2; in temporal_filter_iterate_c() 803 const int mb_uv_height = BH >> mbd->plane[1].subsampling_y; in temporal_filter_iterate_c() 834 -((mb_row * BH) + (17 - 2 * AOM_INTERP_EXTEND)); in temporal_filter_iterate_c() 836 ((mb_rows - 1 - mb_row) * BH) + (17 - 2 * AOM_INTERP_EXTEND); in temporal_filter_iterate_c() 879 frames[frame]->y_stride, mb_col * BW, mb_row * BH, blk_mvs, in temporal_filter_iterate_c() [all …]
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D | temporal_filter.h | 23 #define BH 32 macro
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/external/llvm/test/CodeGen/Hexagon/ |
D | sube.ll | 12 define void @check_sube_subc(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) { 19 %tmp89 = zext i64 %BH to i128
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D | adde.ll | 17 define void @check_adde_addc (i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) { 24 %tmp89 = zext i64 %BH to i128
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/external/llvm/lib/Target/X86/MCTargetDesc/ |
D | X86MCTargetDesc.cpp | 78 X86::DH, X86::BH, X86::AX, X86::CX, X86::DX, X86::BX, in initLLVMToSEHAndCVRegMapping() 299 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero() 300 return X86::BH; in getX86SubSuperRegisterOrZero() 311 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero() 348 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero() 384 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero() 420 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero()
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/external/swiftshader/third_party/LLVM/lib/Target/X86/ |
D | X86RegisterInfo.td | 70 def BH : Register<"bh">; 77 def BX : RegisterWithSubRegs<"bx", [BL,BH]>; 283 // FIXME: Allow AH, CH, DH, BH to be used as general-purpose registers in 289 (add AL, CL, DL, AH, CH, DH, BL, BH, SIL, DIL, BPL, SPL, 291 let AltOrders = [(sub GR8, AH, BH, CH, DH)]; 338 def GR8_ABCD_H : RegisterClass<"X86", [i8], 8, (add AH, CH, DH, BH)>; 368 (add AL, CL, DL, AH, CH, DH, BL, BH)> { 369 let AltOrders = [(sub GR8_NOREX, AH, BH, CH, DH)];
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D | X86RegisterInfo.cpp | 675 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegister() 676 return X86::BH; in getX86SubSuperRegister() 687 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegister() 724 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegister() 760 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegister() 796 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegister()
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/external/swiftshader/third_party/LLVM/test/CodeGen/X86/ |
D | norex-subreg.ll | 7 ; %R8B<def> = COPY %BH, %EBX<imp-use,kill> 10 ; The register allocation above is invalid, %BH can only be encoded without an
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/external/llvm/test/CodeGen/X86/ |
D | norex-subreg.ll | 7 ; %R8B<def> = COPY %BH, %EBX<imp-use,kill> 10 ; The register allocation above is invalid, %BH can only be encoded without an
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/MCTargetDesc/ |
D | X86MCTargetDesc.cpp | 91 { codeview::RegisterId::CVRegBH, X86::BH}, in initLLVMToSEHAndCVRegMapping() 515 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero() 516 return X86::BH; in getX86SubSuperRegisterOrZero() 527 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero() 564 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero() 600 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero() 636 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero()
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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
D | thumb2-ldrb-ldrh.s | 4 @ Thumb2 LDRS?[BH] are not valid when Rt == PC (these encodings are used for
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/external/llvm/test/MC/ARM/ |
D | thumb2-ldrb-ldrh.s | 4 @ Thumb2 LDRS?[BH] are not valid when Rt == PC (these encodings are used for
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/external/llvm/lib/Target/X86/ |
D | X86RegisterInfo.td | 58 def BH : X86Reg<"bh", 7>; 81 def BX : X86Reg<"bx", 3, [BL,BH]>; 323 // FIXME: Allow AH, CH, DH, BH to be used as general-purpose registers in 329 (add AL, CL, DL, AH, CH, DH, BL, BH, SIL, DIL, BPL, SPL, 331 let AltOrders = [(sub GR8, AH, BH, CH, DH)]; 370 def GR8_ABCD_H : RegisterClass<"X86", [i8], 8, (add AH, CH, DH, BH)>; 382 (add AL, CL, DL, AH, CH, DH, BL, BH)> { 383 let AltOrders = [(sub GR8_NOREX, AH, BH, CH, DH)];
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
D | X86RegisterInfo.td | 60 def BH : X86Reg<"bh", 7>; 117 def BX : X86Reg<"bx", 3, [BL,BH]>; 375 // FIXME: Allow AH, CH, DH, BH to be used as general-purpose registers in 381 (add AL, CL, DL, AH, CH, DH, BL, BH, SIL, DIL, BPL, SPL, 383 let AltOrders = [(sub GR8, AH, BH, CH, DH)]; 435 def GR8_ABCD_H : RegisterClass<"X86", [i8], 8, (add AH, CH, DH, BH)>; 447 (add AL, CL, DL, AH, CH, DH, BL, BH)> { 448 let AltOrders = [(sub GR8_NOREX, AH, BH, CH, DH)];
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/external/cldr/tools/java/org/unicode/cldr/util/data/external/ |
D | alternate_locode_name.txt | 10 BHAMH ; Manama # BH : Bahrain
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/external/icu/icu4c/source/data/region/ |
D | nus.txt | 24 BH{"Ba̱reen"}
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/external/libphonenumber/ |
D | release_notes.txt | 116 BE, BF, BG, BH, BI, BJ, BL, BM, BN, BO, BQ, BR, BS, BT, BW, BY, BZ, CA, CC, 202 - Updated phone metadata for region code(s): AZ, BH, HN, IN, US 476 AR, BH, BY, CI, CN, GH, KR, KW, LU, ME, NZ, SB, WS 486 BD, BH, EH, GH, IN, JM, LU, MA, MY, NF, NG, PK, SB, TT, TZ 632 BF, BH, BR, CN, GR, IN, MY, PA, TN, US 678 AF, AG, AI, AM, AR, AS, AW, AZ, BD, BH, BI, BM, BO, BQ, BT, BW, BY, CA, CH, 730 YE, OM, PS, AE, IL, BH, QA, BT, NP, IR, TJ, TM, AZ, GE, KG and UZ in English. 799 AR, BF, BH, BR, BY, CH, CM, CN, GE, GW, HN, JM, KH, LT, LU, MU, NP, RO, SO 821 BF, BH, BI, BJ, BR, CR, EH, GA, GE, GN, GU, IL, IN, IR, KH, KW, KZ, MA, MT, 839 AS, BG, BH, BJ, BL, CD, CI, DE, DZ, EH, FJ, GF, GP, IN, KH, KZ, MA, MD, MF, [all …]
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