| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/ |
| D | quadint-return.ll | 19 ; CHECK-NEXT: BLR
|
| /external/llvm/test/CodeGen/PowerPC/ |
| D | quadint-return.ll | 19 ; CHECK-NEXT: BLR
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Target/ |
| D | TargetInstrPredicate.td | 25 // CheckOpcode<[BLR]>,
30 // input is a BLR, and that operand at index 0 is register `LR`.
36 // MI->getOpcode() == AArch64::BLR &&
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCEarlyReturn.cpp | 65 (I->getOpcode() != PPC::BLR && I->getOpcode() != PPC::BLR8) || in processBlock()
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCEarlyReturn.cpp | 65 (I->getOpcode() != PPC::BLR && I->getOpcode() != PPC::BLR8) || in processBlock()
|
| D | PPCInstrInfo.cpp | 1329 if (OpC == PPC::BLR || OpC == PPC::BLR8) { in PredicateInstruction()
1489 case PPC::BLR: in isPredicable()
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64AsmPrinter.cpp | 411 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::BLR).addReg(ScratchReg)); in LowerPATCHPOINT()
555 Blr.setOpcode(AArch64::BLR); in EmitInstruction()
|
| D | AArch64SchedM1.td | 230 def : InstRW<[M1WriteBLR], (instrs BLR)>;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/GlobalISel/ |
| D | irtranslator-exceptions.ll | 53 ; CHECK: BLR [[CALLEE]]
|
| D | call-translator.ll | 40 ; CHECK: BLR %[[FUNC]](p0), csr_aarch64_aapcs, implicit-def $lr, implicit $sp
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | RegisterCoalescer.cpp | 430 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx); in AdjustCopiesBackFrom() local
431 if (BLR == IntB.end()) return false; in AdjustCopiesBackFrom()
432 VNInfo *BValNo = BLR->valno; in AdjustCopiesBackFrom()
489 if (ValLR+1 != BLR) return false; in AdjustCopiesBackFrom()
510 SlotIndex FillerStart = ValLR->end, FillerEnd = BLR->start; in AdjustCopiesBackFrom()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64AsmPrinter.cpp | 492 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::BLR).addReg(ScratchReg)); in LowerPATCHPOINT()
656 Blr.setOpcode(AArch64::BLR); in EmitInstruction()
|
| D | AArch64CallLowering.cpp | 362 auto MIB = MIRBuilder.buildInstrNoInsert(Callee.isReg() ? AArch64::BLR in lowerCall()
|
| D | AArch64SchedThunderX.td | 255 def : InstRW<[THXT8XWriteBRR], (instregex "^BLR$")>;
|
| D | AArch64SchedExynosM1.td | 67 def M1BranchLinkFastPred : SchedPredicate<[{MI->getOpcode() == AArch64::BLR &&
437 def : InstRW<[M1WriteBX], (instrs BLR)>;
|
| D | AArch64SchedExynosM3.td | 112 def M3BranchLinkFastPred : SchedPredicate<[{MI->getOpcode() == AArch64::BLR &&
494 def : InstRW<[M3WriteBX], (instrs BLR)>;
|
| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeARM_64.c | 79 #define BLR 0xd63f0000 macro
1642 PTR_FAIL_IF(push_inst(compiler, ((type >= SLJIT_FAST_CALL) ? BLR : BR) | RN(TMP_REG1))); in sljit_emit_jump()
1709 return push_inst(compiler, ((type >= SLJIT_FAST_CALL) ? BLR : BR) | RN(src)); in sljit_emit_ijump()
1720 return push_inst(compiler, ((type >= SLJIT_FAST_CALL) ? BLR : BR) | RN(TMP_REG1)); in sljit_emit_ijump()
|
| D | sljitNativePPC_common.c | 152 #define BLR (HI(19) | LO(16) | (0x14 << 21)) macro
728 FAIL_IF(push_inst(compiler, BLR)); in sljit_emit_return()
1783 return push_inst(compiler, BLR); in sljit_emit_fast_return()
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCFrameLowering.cpp | 513 assert((RetOpcode == PPC::BLR || in emitEpilogue()
658 if (GuaranteedTailCallOpt && RetOpcode == PPC::BLR && in emitEpilogue()
|
| /external/v8/src/arm64/ |
| D | instructions-arm64.h | 363 return Mask(UnconditionalBranchToRegisterMask) == BLR; in IsBranchAndLinkToRegister()
|
| /external/selinux/mcstrans/share/examples/nato/setrans.d/ |
| D | eyes-only.conf | 97 ~c228=BLR # Belarus
|
| D | rel.conf | 103 ~c200,~c228=BLR # Belarus
|
| /external/cldr/tools/java/org/unicode/cldr/util/data/ |
| D | territory_codes.txt | 47 BY 112 BLR by BO
|
| /external/u-boot/arch/arm/include/asm/arch-imx/ |
| D | imx-regs.h | 353 #define BLR(x) __REG2( IMX_DMAC_BASE + 0x94, (x) << 6) /* Burst length Registers */ macro
|
| /external/cldr/tools/java/org/unicode/cldr/util/data/external/ |
| D | world_bank_data.csv | 36 Belarus,BLR,"Population, total",SP.POP.TOTL,9979610,9928549,9865548,9796749,9730146,9663915,9604924…
37 Belarus,BLR,"GNI, PPP (current international $)",NY.GNP.MKTP.PP.CD,59604001770.5209,63814442373.752…
|