1//==- AArch64SchedThunderX.td - Cavium ThunderX T8X Scheduling Definitions -*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the itinerary class data for the ARM ThunderX T8X 11// (T88, T81, T83) processors. 12// Loosely based on Cortex-A53 which is somewhat similar. 13// 14//===----------------------------------------------------------------------===// 15 16// ===---------------------------------------------------------------------===// 17// The following definitions describe the simpler per-operand machine model. 18// This works with MachineScheduler. See llvm/MC/MCSchedule.h for details. 19 20// Cavium ThunderX T8X scheduling machine model. 21def ThunderXT8XModel : SchedMachineModel { 22 let IssueWidth = 2; // 2 micro-ops dispatched per cycle. 23 let MicroOpBufferSize = 0; // ThunderX T88/T81/T83 are in-order. 24 let LoadLatency = 3; // Optimistic load latency. 25 let MispredictPenalty = 8; // Branch mispredict penalty. 26 let PostRAScheduler = 1; // Use PostRA scheduler. 27 let CompleteModel = 1; 28 29 list<Predicate> UnsupportedFeatures = [HasSVE]; 30 31 // FIXME: Remove when all errors have been fixed. 32 let FullInstRWOverlapCheck = 0; 33} 34 35// Modeling each pipeline with BufferSize == 0 since T8X is in-order. 36def THXT8XUnitALU : ProcResource<2> { let BufferSize = 0; } // Int ALU 37def THXT8XUnitMAC : ProcResource<1> { let BufferSize = 0; } // Int MAC 38def THXT8XUnitDiv : ProcResource<1> { let BufferSize = 0; } // Int Division 39def THXT8XUnitLdSt : ProcResource<1> { let BufferSize = 0; } // Load/Store 40def THXT8XUnitBr : ProcResource<1> { let BufferSize = 0; } // Branch 41def THXT8XUnitFPALU : ProcResource<1> { let BufferSize = 0; } // FP ALU 42def THXT8XUnitFPMDS : ProcResource<1> { let BufferSize = 0; } // FP Mul/Div/Sqrt 43 44//===----------------------------------------------------------------------===// 45// Subtarget-specific SchedWrite types mapping the ProcResources and 46// latencies. 47 48let SchedModel = ThunderXT8XModel in { 49 50// ALU 51def : WriteRes<WriteImm, [THXT8XUnitALU]> { let Latency = 1; } 52def : WriteRes<WriteI, [THXT8XUnitALU]> { let Latency = 1; } 53def : WriteRes<WriteISReg, [THXT8XUnitALU]> { let Latency = 2; } 54def : WriteRes<WriteIEReg, [THXT8XUnitALU]> { let Latency = 2; } 55def : WriteRes<WriteIS, [THXT8XUnitALU]> { let Latency = 2; } 56def : WriteRes<WriteExtr, [THXT8XUnitALU]> { let Latency = 2; } 57 58// MAC 59def : WriteRes<WriteIM32, [THXT8XUnitMAC]> { 60 let Latency = 4; 61 let ResourceCycles = [1]; 62} 63 64def : WriteRes<WriteIM64, [THXT8XUnitMAC]> { 65 let Latency = 4; 66 let ResourceCycles = [1]; 67} 68 69// Div 70def : WriteRes<WriteID32, [THXT8XUnitDiv]> { 71 let Latency = 12; 72 let ResourceCycles = [6]; 73} 74 75def : WriteRes<WriteID64, [THXT8XUnitDiv]> { 76 let Latency = 14; 77 let ResourceCycles = [8]; 78} 79 80// Load 81def : WriteRes<WriteLD, [THXT8XUnitLdSt]> { let Latency = 3; } 82def : WriteRes<WriteLDIdx, [THXT8XUnitLdSt]> { let Latency = 3; } 83def : WriteRes<WriteLDHi, [THXT8XUnitLdSt]> { let Latency = 3; } 84 85// Vector Load 86def : WriteRes<WriteVLD, [THXT8XUnitLdSt]> { 87 let Latency = 8; 88 let ResourceCycles = [3]; 89} 90 91def THXT8XWriteVLD1 : SchedWriteRes<[THXT8XUnitLdSt]> { 92 let Latency = 6; 93 let ResourceCycles = [1]; 94} 95 96def THXT8XWriteVLD2 : SchedWriteRes<[THXT8XUnitLdSt]> { 97 let Latency = 11; 98 let ResourceCycles = [7]; 99} 100 101def THXT8XWriteVLD3 : SchedWriteRes<[THXT8XUnitLdSt]> { 102 let Latency = 12; 103 let ResourceCycles = [8]; 104} 105 106def THXT8XWriteVLD4 : SchedWriteRes<[THXT8XUnitLdSt]> { 107 let Latency = 13; 108 let ResourceCycles = [9]; 109} 110 111def THXT8XWriteVLD5 : SchedWriteRes<[THXT8XUnitLdSt]> { 112 let Latency = 13; 113 let ResourceCycles = [9]; 114} 115 116// Pre/Post Indexing 117def : WriteRes<WriteAdr, []> { let Latency = 0; } 118 119// Store 120def : WriteRes<WriteST, [THXT8XUnitLdSt]> { let Latency = 1; } 121def : WriteRes<WriteSTP, [THXT8XUnitLdSt]> { let Latency = 1; } 122def : WriteRes<WriteSTIdx, [THXT8XUnitLdSt]> { let Latency = 1; } 123def : WriteRes<WriteSTX, [THXT8XUnitLdSt]> { let Latency = 1; } 124 125// Vector Store 126def : WriteRes<WriteVST, [THXT8XUnitLdSt]>; 127def THXT8XWriteVST1 : SchedWriteRes<[THXT8XUnitLdSt]>; 128 129def THXT8XWriteVST2 : SchedWriteRes<[THXT8XUnitLdSt]> { 130 let Latency = 10; 131 let ResourceCycles = [9]; 132} 133 134def THXT8XWriteVST3 : SchedWriteRes<[THXT8XUnitLdSt]> { 135 let Latency = 11; 136 let ResourceCycles = [10]; 137} 138 139def : WriteRes<WriteAtomic, []> { let Unsupported = 1; } 140 141// Branch 142def : WriteRes<WriteBr, [THXT8XUnitBr]>; 143def THXT8XWriteBR : SchedWriteRes<[THXT8XUnitBr]>; 144def : WriteRes<WriteBrReg, [THXT8XUnitBr]>; 145def THXT8XWriteBRR : SchedWriteRes<[THXT8XUnitBr]>; 146def THXT8XWriteRET : SchedWriteRes<[THXT8XUnitALU]>; 147def : WriteRes<WriteSys, [THXT8XUnitBr]>; 148def : WriteRes<WriteBarrier, [THXT8XUnitBr]>; 149def : WriteRes<WriteHint, [THXT8XUnitBr]>; 150 151// FP ALU 152def : WriteRes<WriteF, [THXT8XUnitFPALU]> { let Latency = 6; } 153def : WriteRes<WriteFCmp, [THXT8XUnitFPALU]> { let Latency = 6; } 154def : WriteRes<WriteFCvt, [THXT8XUnitFPALU]> { let Latency = 6; } 155def : WriteRes<WriteFCopy, [THXT8XUnitFPALU]> { let Latency = 6; } 156def : WriteRes<WriteFImm, [THXT8XUnitFPALU]> { let Latency = 6; } 157def : WriteRes<WriteV, [THXT8XUnitFPALU]> { let Latency = 6; } 158 159// FP Mul, Div, Sqrt 160def : WriteRes<WriteFMul, [THXT8XUnitFPMDS]> { let Latency = 6; } 161def : WriteRes<WriteFDiv, [THXT8XUnitFPMDS]> { 162 let Latency = 22; 163 let ResourceCycles = [19]; 164} 165 166def THXT8XWriteFMAC : SchedWriteRes<[THXT8XUnitFPMDS]> { let Latency = 10; } 167 168def THXT8XWriteFDivSP : SchedWriteRes<[THXT8XUnitFPMDS]> { 169 let Latency = 12; 170 let ResourceCycles = [9]; 171} 172 173def THXT8XWriteFDivDP : SchedWriteRes<[THXT8XUnitFPMDS]> { 174 let Latency = 22; 175 let ResourceCycles = [19]; 176} 177 178def THXT8XWriteFSqrtSP : SchedWriteRes<[THXT8XUnitFPMDS]> { 179 let Latency = 17; 180 let ResourceCycles = [14]; 181} 182 183def THXT8XWriteFSqrtDP : SchedWriteRes<[THXT8XUnitFPMDS]> { 184 let Latency = 31; 185 let ResourceCycles = [28]; 186} 187 188//===----------------------------------------------------------------------===// 189// Subtarget-specific SchedRead types. 190 191// No forwarding for these reads. 192def : ReadAdvance<ReadExtrHi, 1>; 193def : ReadAdvance<ReadAdrBase, 2>; 194def : ReadAdvance<ReadVLD, 2>; 195 196// FIXME: This needs more targeted benchmarking. 197// ALU - Most operands in the ALU pipes are not needed for two cycles. Shiftable 198// operands are needed one cycle later if and only if they are to be 199// shifted. Otherwise, they too are needed two cycles later. This same 200// ReadAdvance applies to Extended registers as well, even though there is 201// a separate SchedPredicate for them. 202def : ReadAdvance<ReadI, 2, [WriteImm, WriteI, 203 WriteISReg, WriteIEReg, WriteIS, 204 WriteID32, WriteID64, 205 WriteIM32, WriteIM64]>; 206def THXT8XReadShifted : SchedReadAdvance<1, [WriteImm, WriteI, 207 WriteISReg, WriteIEReg, WriteIS, 208 WriteID32, WriteID64, 209 WriteIM32, WriteIM64]>; 210def THXT8XReadNotShifted : SchedReadAdvance<2, [WriteImm, WriteI, 211 WriteISReg, WriteIEReg, WriteIS, 212 WriteID32, WriteID64, 213 WriteIM32, WriteIM64]>; 214def THXT8XReadISReg : SchedReadVariant<[ 215 SchedVar<RegShiftedPred, [THXT8XReadShifted]>, 216 SchedVar<NoSchedPred, [THXT8XReadNotShifted]>]>; 217def : SchedAlias<ReadISReg, THXT8XReadISReg>; 218 219def THXT8XReadIEReg : SchedReadVariant<[ 220 SchedVar<RegExtendedPred, [THXT8XReadShifted]>, 221 SchedVar<NoSchedPred, [THXT8XReadNotShifted]>]>; 222def : SchedAlias<ReadIEReg, THXT8XReadIEReg>; 223 224// MAC - Operands are generally needed one cycle later in the MAC pipe. 225// Accumulator operands are needed two cycles later. 226def : ReadAdvance<ReadIM, 1, [WriteImm,WriteI, 227 WriteISReg, WriteIEReg, WriteIS, 228 WriteID32, WriteID64, 229 WriteIM32, WriteIM64]>; 230def : ReadAdvance<ReadIMA, 2, [WriteImm, WriteI, 231 WriteISReg, WriteIEReg, WriteIS, 232 WriteID32, WriteID64, 233 WriteIM32, WriteIM64]>; 234 235// Div 236def : ReadAdvance<ReadID, 1, [WriteImm, WriteI, 237 WriteISReg, WriteIEReg, WriteIS, 238 WriteID32, WriteID64, 239 WriteIM32, WriteIM64]>; 240 241//===----------------------------------------------------------------------===// 242// Subtarget-specific InstRW. 243 244//--- 245// Branch 246//--- 247def : InstRW<[THXT8XWriteBR], (instregex "^B$")>; 248def : InstRW<[THXT8XWriteBR], (instregex "^BL$")>; 249def : InstRW<[THXT8XWriteBR], (instregex "^B..$")>; 250def : InstRW<[THXT8XWriteBR], (instregex "^CBNZ")>; 251def : InstRW<[THXT8XWriteBR], (instregex "^CBZ")>; 252def : InstRW<[THXT8XWriteBR], (instregex "^TBNZ")>; 253def : InstRW<[THXT8XWriteBR], (instregex "^TBZ")>; 254def : InstRW<[THXT8XWriteBRR], (instregex "^BR$")>; 255def : InstRW<[THXT8XWriteBRR], (instregex "^BLR$")>; 256 257//--- 258// Ret 259//--- 260def : InstRW<[THXT8XWriteRET], (instregex "^RET$")>; 261 262//--- 263// Miscellaneous 264//--- 265def : InstRW<[WriteI], (instrs COPY)>; 266 267//--- 268// Vector Loads 269//--- 270def : InstRW<[THXT8XWriteVLD1], (instregex "LD1i(8|16|32|64)$")>; 271def : InstRW<[THXT8XWriteVLD1], (instregex "LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 272def : InstRW<[THXT8XWriteVLD1], (instregex "LD1Onev(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 273def : InstRW<[THXT8XWriteVLD2], (instregex "LD1Twov(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 274def : InstRW<[THXT8XWriteVLD3], (instregex "LD1Threev(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 275def : InstRW<[THXT8XWriteVLD4], (instregex "LD1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 276def : InstRW<[THXT8XWriteVLD1, WriteAdr], (instregex "LD1i(8|16|32|64)_POST$")>; 277def : InstRW<[THXT8XWriteVLD1, WriteAdr], (instregex "LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 278def : InstRW<[THXT8XWriteVLD1, WriteAdr], (instregex "LD1Onev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 279def : InstRW<[THXT8XWriteVLD2, WriteAdr], (instregex "LD1Twov(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 280def : InstRW<[THXT8XWriteVLD3, WriteAdr], (instregex "LD1Threev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 281def : InstRW<[THXT8XWriteVLD4, WriteAdr], (instregex "LD1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 282 283def : InstRW<[THXT8XWriteVLD1], (instregex "LD2i(8|16|32|64)$")>; 284def : InstRW<[THXT8XWriteVLD1], (instregex "LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 285def : InstRW<[THXT8XWriteVLD2], (instregex "LD2Twov(8b|4h|2s)$")>; 286def : InstRW<[THXT8XWriteVLD4], (instregex "LD2Twov(16b|8h|4s|2d)$")>; 287def : InstRW<[THXT8XWriteVLD1, WriteAdr], (instregex "LD2i(8|16|32|64)(_POST)?$")>; 288def : InstRW<[THXT8XWriteVLD1, WriteAdr], (instregex "LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)(_POST)?$")>; 289def : InstRW<[THXT8XWriteVLD2, WriteAdr], (instregex "LD2Twov(8b|4h|2s)(_POST)?$")>; 290def : InstRW<[THXT8XWriteVLD4, WriteAdr], (instregex "LD2Twov(16b|8h|4s|2d)(_POST)?$")>; 291 292def : InstRW<[THXT8XWriteVLD2], (instregex "LD3i(8|16|32|64)$")>; 293def : InstRW<[THXT8XWriteVLD2], (instregex "LD3Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 294def : InstRW<[THXT8XWriteVLD4], (instregex "LD3Threev(8b|4h|2s|1d|16b|8h|4s)$")>; 295def : InstRW<[THXT8XWriteVLD3], (instregex "LD3Threev(2d)$")>; 296def : InstRW<[THXT8XWriteVLD2, WriteAdr], (instregex "LD3i(8|16|32|64)_POST$")>; 297def : InstRW<[THXT8XWriteVLD2, WriteAdr], (instregex "LD3Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 298def : InstRW<[THXT8XWriteVLD4, WriteAdr], (instregex "LD3Threev(8b|4h|2s|1d|16b|8h|4s)_POST$")>; 299def : InstRW<[THXT8XWriteVLD3, WriteAdr], (instregex "LD3Threev(2d)_POST$")>; 300 301def : InstRW<[THXT8XWriteVLD2], (instregex "LD4i(8|16|32|64)$")>; 302def : InstRW<[THXT8XWriteVLD2], (instregex "LD4Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 303def : InstRW<[THXT8XWriteVLD5], (instregex "LD4Fourv(8b|4h|2s|1d|16b|8h|4s)$")>; 304def : InstRW<[THXT8XWriteVLD4], (instregex "LD4Fourv(2d)$")>; 305def : InstRW<[THXT8XWriteVLD2, WriteAdr], (instregex "LD4i(8|16|32|64)_POST$")>; 306def : InstRW<[THXT8XWriteVLD2, WriteAdr], (instregex "LD4Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 307def : InstRW<[THXT8XWriteVLD5, WriteAdr], (instregex "LD4Fourv(8b|4h|2s|1d|16b|8h|4s)_POST$")>; 308def : InstRW<[THXT8XWriteVLD4, WriteAdr], (instregex "LD4Fourv(2d)_POST$")>; 309 310//--- 311// Vector Stores 312//--- 313def : InstRW<[THXT8XWriteVST1], (instregex "ST1i(8|16|32|64)$")>; 314def : InstRW<[THXT8XWriteVST1], (instregex "ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 315def : InstRW<[THXT8XWriteVST1], (instregex "ST1Twov(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 316def : InstRW<[THXT8XWriteVST2], (instregex "ST1Threev(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 317def : InstRW<[THXT8XWriteVST2], (instregex "ST1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; 318def : InstRW<[THXT8XWriteVST1, WriteAdr], (instregex "ST1i(8|16|32|64)_POST$")>; 319def : InstRW<[THXT8XWriteVST1, WriteAdr], (instregex "ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 320def : InstRW<[THXT8XWriteVST1, WriteAdr], (instregex "ST1Twov(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 321def : InstRW<[THXT8XWriteVST2, WriteAdr], (instregex "ST1Threev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 322def : InstRW<[THXT8XWriteVST2, WriteAdr], (instregex "ST1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>; 323 324def : InstRW<[THXT8XWriteVST1], (instregex "ST2i(8|16|32|64)$")>; 325def : InstRW<[THXT8XWriteVST1], (instregex "ST2Twov(8b|4h|2s)$")>; 326def : InstRW<[THXT8XWriteVST2], (instregex "ST2Twov(16b|8h|4s|2d)$")>; 327def : InstRW<[THXT8XWriteVST1, WriteAdr], (instregex "ST2i(8|16|32|64)_POST$")>; 328def : InstRW<[THXT8XWriteVST1, WriteAdr], (instregex "ST2Twov(8b|4h|2s)_POST$")>; 329def : InstRW<[THXT8XWriteVST2, WriteAdr], (instregex "ST2Twov(16b|8h|4s|2d)_POST$")>; 330 331def : InstRW<[THXT8XWriteVST2], (instregex "ST3i(8|16|32|64)$")>; 332def : InstRW<[THXT8XWriteVST3], (instregex "ST3Threev(8b|4h|2s|1d|16b|8h|4s)$")>; 333def : InstRW<[THXT8XWriteVST2], (instregex "ST3Threev(2d)$")>; 334def : InstRW<[THXT8XWriteVST2, WriteAdr], (instregex "ST3i(8|16|32|64)_POST$")>; 335def : InstRW<[THXT8XWriteVST3, WriteAdr], (instregex "ST3Threev(8b|4h|2s|1d|16b|8h|4s)_POST$")>; 336def : InstRW<[THXT8XWriteVST2, WriteAdr], (instregex "ST3Threev(2d)_POST$")>; 337 338def : InstRW<[THXT8XWriteVST2], (instregex "ST4i(8|16|32|64)$")>; 339def : InstRW<[THXT8XWriteVST3], (instregex "ST4Fourv(8b|4h|2s|1d|16b|8h|4s)$")>; 340def : InstRW<[THXT8XWriteVST2], (instregex "ST4Fourv(2d)$")>; 341def : InstRW<[THXT8XWriteVST2, WriteAdr], (instregex "ST4i(8|16|32|64)_POST$")>; 342def : InstRW<[THXT8XWriteVST3, WriteAdr], (instregex "ST4Fourv(8b|4h|2s|1d|16b|8h|4s)_POST$")>; 343def : InstRW<[THXT8XWriteVST2, WriteAdr], (instregex "ST4Fourv(2d)_POST$")>; 344 345//--- 346// Floating Point MAC, DIV, SQRT 347//--- 348def : InstRW<[THXT8XWriteFMAC], (instregex "^FN?M(ADD|SUB).*")>; 349def : InstRW<[THXT8XWriteFMAC], (instregex "^FML(A|S).*")>; 350def : InstRW<[THXT8XWriteFDivSP], (instrs FDIVSrr)>; 351def : InstRW<[THXT8XWriteFDivDP], (instrs FDIVDrr)>; 352def : InstRW<[THXT8XWriteFDivSP], (instregex "^FDIVv.*32$")>; 353def : InstRW<[THXT8XWriteFDivDP], (instregex "^FDIVv.*64$")>; 354def : InstRW<[THXT8XWriteFSqrtSP], (instregex "^.*SQRT.*32$")>; 355def : InstRW<[THXT8XWriteFSqrtDP], (instregex "^.*SQRT.*64$")>; 356 357} 358