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Searched refs:Bank (Results 1 – 25 of 55) sorted by relevance

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/external/u-boot/board/toradex/colibri_imx6/
Dpf0100_otp.inc72 {pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
73 {pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
74 {pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
75 {pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
76 {pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
77 {pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
78 {pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
79 {pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
80 {pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
81 {pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
[all …]
/external/u-boot/board/toradex/apalis_imx6/
Dpf0100_otp.inc74 {pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
75 {pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
76 {pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
77 {pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
78 {pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
79 {pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
80 {pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
81 {pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
82 {pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
83 {pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/
DRegisterBankEmitter.cpp136 for (const auto &Bank : Banks) in emitHeader() local
137 OS << " " << Bank.getEnumeratorName() << ",\n"; in emitHeader()
219 for (const auto &Bank : Banks) { in emitBaseClassImplementation() local
223 for (const auto &RC : Bank.register_classes()) in emitBaseClassImplementation()
226 OS << "const uint32_t " << Bank.getCoverageArrayName() << "[] = {\n"; in emitBaseClassImplementation()
243 for (const auto &Bank : Banks) { in emitBaseClassImplementation() local
245 (TargetName + "::" + Bank.getEnumeratorName()).str(); in emitBaseClassImplementation()
246 const CodeGenRegisterClass &RC = *Bank.getRCWithLargestRegsSize(); in emitBaseClassImplementation()
248 OS << "RegisterBank " << Bank.getInstanceVarName() << "(/* ID */ " in emitBaseClassImplementation()
249 << QualifiedBankID << ", /* Name */ \"" << Bank.getName() in emitBaseClassImplementation()
[all …]
DRegisterInfoEmitter.cpp68 void runEnums(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
71 void runMCDesc(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
75 CodeGenRegBank &Bank);
79 CodeGenRegBank &Bank);
104 CodeGenTarget &Target, CodeGenRegBank &Bank) { in runEnums() argument
105 const auto &Registers = Bank.getRegisters(); in runEnums()
136 const auto &RegisterClasses = Bank.getRegClasses(); in runEnums()
171 auto &SubRegIndices = Bank.getSubRegIndices(); in runEnums()
/external/swiftshader/third_party/LLVM/utils/TableGen/
DRegisterInfoEmitter.h34 void runEnums(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
37 void runMCDesc(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
41 CodeGenRegBank &Bank);
45 CodeGenRegBank &Bank);
/external/u-boot/arch/powerpc/cpu/mpc8xx/
DKconfig98 bool "Define Bank 1"
109 bool "Define Bank 2"
120 bool "Define Bank 3"
131 bool "Define Bank 4"
142 bool "Define Bank 5"
153 bool "Define Bank 6"
164 bool "Define Bank 7"
/external/u-boot/arch/arm/dts/
Dmeson-gxl-s905x-khadas-vim.dts131 gpio-line-names = /* Bank GPIOZ */
136 /* Bank GPIOH */
144 /* Bank BOOT */
149 /* Bank CARD */
152 /* Bank GPIODV */
157 /* Bank GPIOX */
167 /* Bank GPIOCLK */
Dmeson-gxl-s905x-libretech-cc.dts182 gpio-line-names = /* Bank GPIOZ */
186 /* Bank GPIOH */
194 /* Bank BOOT */
199 /* Bank CARD */
202 /* Bank GPIODV */
208 /* Bank GPIOX */
219 /* Bank GPIOCLK */
Dmeson-gxbb-odroidc2.dts201 gpio-line-names = /* Bank GPIOZ */
207 /* Bank GPIOH */
209 /* Bank BOOT */
214 /* Bank CARD */
217 /* Bank GPIODV */
222 /* Bank GPIOY */
227 /* Bank GPIOX */
237 /* Bank GPIOCLK */
Dam437x-sk-evm.dts81 gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 0 */
88 gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 1 */
95 gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 2 */
102 gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 3 */
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DAMDGPURegisterBankInfo.cpp197 const RegisterBank *Bank = getRegBank(Reg, MRI, *TRI); in isSALUMapping() local
198 if (Bank && Bank->getID() != AMDGPU::SGPRRegBankID) in isSALUMapping()
283 const RegisterBank *Bank = getRegBank(Reg, MRI, TRI); in getRegBankID() local
284 return Bank ? Bank->getID() : Default; in getRegBankID()
344 unsigned Bank = isSALUMapping(MI) ? in getInstrMapping() local
349 OpdsMapping[0] = AMDGPU::getValueMapping(Bank, DstSize); in getInstrMapping()
352 OpdsMapping[i] = AMDGPU::getValueMapping(Bank, SrcSize); in getInstrMapping()
364 unsigned Bank = getRegBankID(Src, MRI, *TRI); in getInstrMapping() local
367 OpdsMapping[0] = AMDGPU::getValueMapping(Bank, DstSize); in getInstrMapping()
368 OpdsMapping[1] = AMDGPU::getValueMapping(Bank, SrcSize); in getInstrMapping()
/external/brotli/c/enc/
Dhash_forgetful_chain_inc.h43 typedef struct FN(Bank) {
45 } FN(Bank);
52 FN(Bank) banks[NUM_BANKS];
/external/u-boot/drivers/mtd/spi/
DKconfig38 bool "SPI flash Bank/Extended address register support"
41 Enable the SPI flash Bank/Extended address register support.
42 Bank/Extended address registers are used to access the flash
/external/llvm/utils/TableGen/
DRegisterInfoEmitter.cpp55 void runEnums(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
58 void runMCDesc(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
62 CodeGenRegBank &Bank);
66 CodeGenRegBank &Bank);
89 CodeGenTarget &Target, CodeGenRegBank &Bank) { in runEnums() argument
90 const auto &Registers = Bank.getRegisters(); in runEnums()
122 const auto &RegisterClasses = Bank.getRegClasses(); in runEnums()
157 auto &SubRegIndices = Bank.getSubRegIndices(); in runEnums()
/external/cldr/tools/java/org/unicode/cldr/util/
DWorldBankInfo.txt1 # Code; World-Bank Country Name; 2004 GDP (or most recent)
138 PS; West Bank and Gaza; 3454453000
/external/u-boot/doc/SPI/
Dstatus.txt11 - Bank Address Register (Accessing flashes > 16Mbytes in 3-byte addressing)
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/
DMipsGenRegisterBank.inc3 |* Register Bank Source Fragments *|
/external/u-boot/board/rockchip/evb_rv1108/
DREADME28 Bus Width=16 Col=10 Bank=8 Row=15 CS=1 Die Bus-Width=16 Size=512MB
/external/u-boot/doc/
DREADME.N121339 - Bank numbers: 1 or 2.
DREADME.fsl_iim29 using "Word y of Bank x" from the register summary in 30.3.2. This is
DREADME.mpc85xxcds210 Flash Bank 1 @ 0xfe000000
211 Flash Bank 2 @ 0xff000000
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/
DARMGenRegisterBank.inc3 |* Register Bank Source Fragments *|
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/
DAArch64GenRegisterBank.inc3 |* Register Bank Source Fragments *|
/external/cldr/tools/java/org/unicode/cldr/util/data/external/
Dfactbook_literacy.txt99 99 West Bank 95.30
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/
DX86GenRegisterBank.inc3 |* Register Bank Source Fragments *|

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