1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2|* *| 3|* Register Bank Source Fragments *| 4|* *| 5|* Automatically generated file, do not edit! *| 6|* *| 7\*===----------------------------------------------------------------------===*/ 8 9#ifdef GET_REGBANK_DECLARATIONS 10#undef GET_REGBANK_DECLARATIONS 11namespace llvm { 12namespace X86 { 13enum { 14 GPRRegBankID, 15 VECRRegBankID, 16 NumRegisterBanks, 17}; 18} // end namespace X86 19} // end namespace llvm 20#endif // GET_REGBANK_DECLARATIONS 21 22#ifdef GET_TARGET_REGBANK_CLASS 23#undef GET_TARGET_REGBANK_CLASS 24private: 25 static RegisterBank *RegBanks[]; 26 27protected: 28 X86GenRegisterBankInfo(); 29 30#endif // GET_TARGET_REGBANK_CLASS 31 32#ifdef GET_TARGET_REGBANK_IMPL 33#undef GET_TARGET_REGBANK_IMPL 34namespace llvm { 35namespace X86 { 36const uint32_t GPRRegBankCoverageData[] = { 37 // 0-31 38 (1u << (X86::GR8RegClassID - 0)) | 39 (1u << (X86::GR16RegClassID - 0)) | 40 (1u << (X86::LOW32_ADDR_ACCESS_RBPRegClassID - 0)) | 41 (1u << (X86::LOW32_ADDR_ACCESSRegClassID - 0)) | 42 (1u << (X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID - 0)) | 43 (1u << (X86::GR32RegClassID - 0)) | 44 (1u << (X86::GR32_NOSPRegClassID - 0)) | 45 (1u << (X86::GR8_NOREXRegClassID - 0)) | 46 (1u << (X86::GR8_ABCD_HRegClassID - 0)) | 47 (1u << (X86::GR8_ABCD_LRegClassID - 0)) | 48 (1u << (X86::GR16_NOREXRegClassID - 0)) | 49 (1u << (X86::GR16_ABCDRegClassID - 0)) | 50 (1u << (X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID - 0)) | 51 (1u << (X86::GR32_NOREXRegClassID - 0)) | 52 0, 53 // 32-63 54 (1u << (X86::GR64RegClassID - 32)) | 55 (1u << (X86::GR64_with_sub_8bitRegClassID - 32)) | 56 (1u << (X86::GR64_NOSPRegClassID - 32)) | 57 (1u << (X86::GR64_NOSP_and_GR64_TCRegClassID - 32)) | 58 (1u << (X86::GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClassID - 32)) | 59 (1u << (X86::GR32_NOREX_NOSPRegClassID - 32)) | 60 (1u << (X86::GR32_ABCDRegClassID - 32)) | 61 (1u << (X86::GR32_TCRegClassID - 32)) | 62 (1u << (X86::GR32_ADRegClassID - 32)) | 63 (1u << (X86::GR64_NOREX_NOSP_and_GR64_TCRegClassID - 32)) | 64 (1u << (X86::GR64_NOREX_NOSPRegClassID - 32)) | 65 (1u << (X86::GR64_NOSP_and_GR64_TCW64RegClassID - 32)) | 66 (1u << (X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID - 32)) | 67 (1u << (X86::GR64_NOREXRegClassID - 32)) | 68 (1u << (X86::GR64_NOREX_and_GR64_TCRegClassID - 32)) | 69 (1u << (X86::GR64_TCRegClassID - 32)) | 70 (1u << (X86::GR64_TC_and_GR64_TCW64RegClassID - 32)) | 71 (1u << (X86::GR64_TCW64RegClassID - 32)) | 72 0, 73 // 64-95 74 (1u << (X86::GR64_with_sub_32bit_in_GR32_TCRegClassID - 64)) | 75 (1u << (X86::GR64_ADRegClassID - 64)) | 76 (1u << (X86::GR64_ABCDRegClassID - 64)) | 77 (1u << (X86::GR64_NOREX_NOSP_and_LOW32_ADDR_ACCESS_RBPRegClassID - 64)) | 78 (1u << (X86::GR64_NOREX_and_GR64_TCW64RegClassID - 64)) | 79 (1u << (X86::GR64_and_LOW32_ADDR_ACCESSRegClassID - 64)) | 80 (1u << (X86::GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID - 64)) | 81 0, 82}; 83const uint32_t VECRRegBankCoverageData[] = { 84 // 0-31 85 (1u << (X86::FR32XRegClassID - 0)) | 86 (1u << (X86::FR32RegClassID - 0)) | 87 0, 88 // 32-63 89 (1u << (X86::FR64XRegClassID - 32)) | 90 (1u << (X86::FR64RegClassID - 32)) | 91 0, 92 // 64-95 93 (1u << (X86::VR512RegClassID - 64)) | 94 (1u << (X86::VR128XRegClassID - 64)) | 95 (1u << (X86::VR256XRegClassID - 64)) | 96 (1u << (X86::VR512_with_sub_xmm_in_FR32RegClassID - 64)) | 97 (1u << (X86::VR128RegClassID - 64)) | 98 (1u << (X86::VR256RegClassID - 64)) | 99 (1u << (X86::VR512_with_sub_xmm_in_VR128HRegClassID - 64)) | 100 (1u << (X86::VR128HRegClassID - 64)) | 101 (1u << (X86::VR256HRegClassID - 64)) | 102 (1u << (X86::VR512_with_sub_xmm_in_VR128LRegClassID - 64)) | 103 (1u << (X86::VR128LRegClassID - 64)) | 104 (1u << (X86::VR256LRegClassID - 64)) | 105 0, 106}; 107 108RegisterBank GPRRegBank(/* ID */ X86::GPRRegBankID, /* Name */ "GPR", /* Size */ 64, /* CoveredRegClasses */ GPRRegBankCoverageData, /* NumRegClasses */ 86); 109RegisterBank VECRRegBank(/* ID */ X86::VECRRegBankID, /* Name */ "VECR", /* Size */ 512, /* CoveredRegClasses */ VECRRegBankCoverageData, /* NumRegClasses */ 86); 110} // end namespace X86 111 112RegisterBank *X86GenRegisterBankInfo::RegBanks[] = { 113 &X86::GPRRegBank, 114 &X86::VECRRegBank, 115}; 116 117X86GenRegisterBankInfo::X86GenRegisterBankInfo() 118 : RegisterBankInfo(RegBanks, X86::NumRegisterBanks) { 119 // Assert that RegBank indices match their ID's 120#ifndef NDEBUG 121 unsigned Index = 0; 122 for (const auto &RB : RegBanks) 123 assert(Index++ == RB->getID() && "Index != ID"); 124#endif // NDEBUG 125} 126} // end namespace llvm 127#endif // GET_TARGET_REGBANK_IMPL 128