Home
last modified time | relevance | path

Searched refs:BaseOpcode (Results 1 – 25 of 50) sorted by relevance

12

/external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/
DX86MCCodeEmitter.cpp881 unsigned char BaseOpcode = X86II::getBaseOpcodeFor(TSFlags); in EncodeInstruction() local
884 BaseOpcode = 0x0F; // Weird 3DNow! encoding. in EncodeInstruction()
895 EmitByte(BaseOpcode, CurByte, OS); in EncodeInstruction()
898 EmitByte(BaseOpcode, CurByte, OS); in EncodeInstruction()
905 EmitByte(BaseOpcode, CurByte, OS); in EncodeInstruction()
913 EmitByte(BaseOpcode + GetX86RegNum(MI.getOperand(CurOp++)), CurByte, OS); in EncodeInstruction()
917 EmitByte(BaseOpcode, CurByte, OS); in EncodeInstruction()
924 EmitByte(BaseOpcode, CurByte, OS); in EncodeInstruction()
937 EmitByte(BaseOpcode, CurByte, OS); in EncodeInstruction()
956 EmitByte(BaseOpcode, CurByte, OS); in EncodeInstruction()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86InstrFMA3Info.cpp136 uint8_t BaseOpcode = X86II::getBaseOpcodeFor(TSFlags); in getFMA3Group() local
141 ((BaseOpcode >= 0x96 && BaseOpcode <= 0x9F) || in getFMA3Group()
142 (BaseOpcode >= 0xA6 && BaseOpcode <= 0xAF) || in getFMA3Group()
143 (BaseOpcode >= 0xB6 && BaseOpcode <= 0xBF)); in getFMA3Group()
160 unsigned FormIndex = ((BaseOpcode - 0x90) >> 4) & 0x3; in getFMA3Group()
/external/llvm/lib/Target/Hexagon/
DHexagon.td82 // Instructions with the same BaseOpcode and isNVStore values form a row.
83 let RowFields = ["BaseOpcode", "isNVStore", "PNewValue", "isNT"];
98 let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken", "isNT"];
110 let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken", "isNT"];
122 let RowFields = ["BaseOpcode", "PredSense", "isNVStore", "isBrTaken"];
134 let RowFields = ["BaseOpcode", "PredSense", "isNVStore"];
146 let RowFields = ["BaseOpcode", "PredSense", "PNewValue", "addrMode", "isNT"];
158 let RowFields = ["BaseOpcode", "PredSense", "PNewValue", "addrMode", "isNT"];
224 let RowFields = ["BaseOpcode", "PNewValue", "PredSense", "isBranch", "isPredicated"];
232 let RowFields = ["BaseOpcode", "PNewValue", "PredSense", "isBranch", "isPredicated"];
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMicroMipsInstrFPU.td259 let BaseOpcode = "RECIP_D32";
271 let BaseOpcode = "RSQRT_D32";
282 let BaseOpcode = "LDC132";
296 let BaseOpcode = "c.f."#NAME;
301 let BaseOpcode = "c.un."#NAME;
306 let BaseOpcode = "c.eq."#NAME;
311 let BaseOpcode = "c.ueq."#NAME;
316 let BaseOpcode = "c.olt."#NAME;
320 let BaseOpcode = "c.ult."#NAME;
324 let BaseOpcode = "c.ole."#NAME;
[all …]
DMipsEVAInstrInfo.td62 string BaseOpcode = instr_asm;
81 string BaseOpcode = instr_asm;
98 string BaseOpcode = instr_asm;
116 string BaseOpcode = instr_asm;
132 string BaseOpcode = instr_asm;
146 string BaseOpcode = instr_asm;
172 string BaseOpcode = instr_asm;
DMipsInstrFPU.td275 let BaseOpcode = "c.f."#NAME;
280 let BaseOpcode = "c.un."#NAME;
285 let BaseOpcode = "c.eq."#NAME;
290 let BaseOpcode = "c.ueq."#NAME;
295 let BaseOpcode = "c.olt."#NAME;
299 let BaseOpcode = "c.ult."#NAME;
303 let BaseOpcode = "c.ole."#NAME;
307 let BaseOpcode = "c.ule."#NAME;
311 let BaseOpcode = "c.sf."#NAME;
316 let BaseOpcode = "c.ngle."#NAME;
[all …]
DMipsDSPInstrInfo.td268 string BaseOpcode = instr_asm;
279 string BaseOpcode = instr_asm;
290 string BaseOpcode = instr_asm;
301 string BaseOpcode = instr_asm;
313 string BaseOpcode = instr_asm;
324 string BaseOpcode = instr_asm;
335 string BaseOpcode = instr_asm;
345 string BaseOpcode = instr_asm;
357 string BaseOpcode = instr_asm;
368 string BaseOpcode = instr_asm;
[all …]
DMicroMips32r6InstrInfo.td611 string BaseOpcode = opstr;
646 string BaseOpcode = instr_asm;
661 string BaseOpcode = opstr;
674 string BaseOpcode = opstr;
685 string BaseOpcode = opstr;
697 string BaseOpcode = opstr;
719 string BaseOpcode = opstr;
732 string BaseOpcode = opstr;
741 string BaseOpcode = opstr;
762 string BaseOpcode = "ldc1";
[all …]
DMipsDSPInstrFormats.td14 // Instructions with the same BaseOpcode and isNVStore values form a row.
15 let RowFields = ["BaseOpcode"];
50 string BaseOpcode = opstr;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DMIMGInstructions.td27 MIMGBaseOpcode BaseOpcode = !cast<MIMGBaseOpcode>(NAME);
46 let Fields = ["BaseOpcode", "Store", "Atomic", "AtomicX2", "Sampler",
51 let PrimaryKey = ["BaseOpcode"];
111 MIMGBaseOpcode BaseOpcode;
120 let Fields = ["Opcode", "BaseOpcode", "MIMGEncoding", "VDataDwords", "VAddrDwords"];
124 let PrimaryKey = ["BaseOpcode", "MIMGEncoding", "VDataDwords", "VAddrDwords"];
140 let d16 = !if(BaseOpcode.HasD16, ?, 0);
145 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
147 #!if(BaseOpcode.HasD16, "$d16", "");
172 let BaseOpcode = !cast<MIMGBaseOpcode>(NAME),
[all …]
DAMDGPUInstrInfo.h54 unsigned BaseOpcode; member
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagon.td115 // Instructions with the same BaseOpcode and isNVStore values form a row.
116 let RowFields = ["BaseOpcode", "isNVStore", "PNewValue", "isBrTaken", "isNT"];
131 let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken", "isNT"];
143 let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken", "isNT"];
155 let RowFields = ["BaseOpcode", "PredSense", "isNVStore", "isBrTaken"];
167 let RowFields = ["BaseOpcode", "PredSense", "isNVStore", "isBrTaken"];
179 let RowFields = ["BaseOpcode", "PredSense", "PNewValue", "addrMode", "isNT"];
191 let RowFields = ["BaseOpcode", "PredSense", "PNewValue", "addrMode", "isNT"];
273 let RowFields = ["BaseOpcode", "PNewValue", "PredSense", "isBranch", "isPredicated"];
281 let RowFields = ["BaseOpcode", "PNewValue", "PredSense", "isBranch", "isPredicated"];
[all …]
DHexagonDepInstrInfo.td57 let BaseOpcode = "A2_add";
221 let BaseOpcode = "A2_addi";
307 let BaseOpcode = "A2_and";
346 let BaseOpcode = "A2_aslh";
358 let BaseOpcode = "A2_asrh";
433 let BaseOpcode = "A2_combinew";
592 let BaseOpcode = "A2_or";
636 let BaseOpcode = "A2_add";
653 let BaseOpcode = "A2_add";
668 let BaseOpcode = "A2_addi";
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86CodeEmitter.cpp725 unsigned char BaseOpcode = X86II::getBaseOpcodeFor(Desc->TSFlags); in emitInstruction() local
760 MCE.emitByte(BaseOpcode); in emitInstruction()
772 MCE.emitByte(BaseOpcode); in emitInstruction()
820 MCE.emitByte(BaseOpcode + in emitInstruction()
854 MCE.emitByte(BaseOpcode); in emitInstruction()
864 MCE.emitByte(BaseOpcode); in emitInstruction()
876 MCE.emitByte(BaseOpcode); in emitInstruction()
891 MCE.emitByte(BaseOpcode); in emitInstruction()
905 MCE.emitByte(BaseOpcode); in emitInstruction()
944 MCE.emitByte(BaseOpcode); in emitInstruction()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/MCTargetDesc/
DX86MCCodeEmitter.cpp1270 uint8_t BaseOpcode = X86II::getBaseOpcodeFor(TSFlags); in encodeInstruction() local
1273 BaseOpcode = 0x0F; // Weird 3DNow! encoding. in encodeInstruction()
1295 EmitByte(BaseOpcode, CurByte, OS); in encodeInstruction()
1308 EmitByte(BaseOpcode, CurByte, OS); in encodeInstruction()
1318 EmitByte(BaseOpcode, CurByte, OS); in encodeInstruction()
1322 EmitByte(BaseOpcode, CurByte, OS); in encodeInstruction()
1336 EmitByte(BaseOpcode, CurByte, OS); in encodeInstruction()
1343 EmitByte(BaseOpcode, CurByte, OS); in encodeInstruction()
1351 EmitByte(BaseOpcode, CurByte, OS); in encodeInstruction()
1360 EmitByte(BaseOpcode + GetX86RegNum(MI.getOperand(CurOp++)), CurByte, OS); in encodeInstruction()
[all …]
/external/llvm/lib/Target/X86/MCTargetDesc/
DX86MCCodeEmitter.cpp1191 uint8_t BaseOpcode = X86II::getBaseOpcodeFor(TSFlags); in encodeInstruction() local
1194 BaseOpcode = 0x0F; // Weird 3DNow! encoding. in encodeInstruction()
1216 EmitByte(BaseOpcode, CurByte, OS); in encodeInstruction()
1229 EmitByte(BaseOpcode, CurByte, OS); in encodeInstruction()
1239 EmitByte(BaseOpcode, CurByte, OS); in encodeInstruction()
1243 EmitByte(BaseOpcode, CurByte, OS); in encodeInstruction()
1248 EmitByte(BaseOpcode, CurByte, OS); in encodeInstruction()
1255 EmitByte(BaseOpcode, CurByte, OS); in encodeInstruction()
1263 EmitByte(BaseOpcode, CurByte, OS); in encodeInstruction()
1272 EmitByte(BaseOpcode + GetX86RegNum(MI.getOperand(CurOp++)), CurByte, OS); in encodeInstruction()
[all …]
/external/llvm/lib/Target/Mips/
DMipsDSPInstrInfo.td267 string BaseOpcode = instr_asm;
278 string BaseOpcode = instr_asm;
289 string BaseOpcode = instr_asm;
300 string BaseOpcode = instr_asm;
312 string BaseOpcode = instr_asm;
323 string BaseOpcode = instr_asm;
334 string BaseOpcode = instr_asm;
344 string BaseOpcode = instr_asm;
356 string BaseOpcode = instr_asm;
367 string BaseOpcode = instr_asm;
[all …]
DMicroMips64r6InstrInfo.td105 string BaseOpcode = instr_asm;
139 string BaseOpcode = "dclo";
149 string BaseOpcode = "dclz";
183 string BaseOpcode = instr_asm;
218 string BaseOpcode = instr_asm;
235 string BaseOpcode = instr_asm;
247 string BaseOpcode = instr_asm;
278 string BaseOpcode = instr_asm;
295 string BaseOpcode = "lld";
307 string BaseOpcode = "sd";
DMipsDSPInstrFormats.td14 // Instructions with the same BaseOpcode and isNVStore values form a row.
15 let RowFields = ["BaseOpcode"];
50 string BaseOpcode = opstr;
DMicroMips32r6InstrInfo.td569 string BaseOpcode = "lwp";
582 string BaseOpcode = "swp";
618 string BaseOpcode = opstr;
662 string BaseOpcode = instr_asm;
675 string BaseOpcode = opstr;
687 string BaseOpcode = opstr;
698 string BaseOpcode = opstr;
710 string BaseOpcode = opstr;
731 string BaseOpcode = opstr;
743 string BaseOpcode = opstr;
[all …]
DMipsInstrFormats.td43 // Instructions with the same BaseOpcode and isNVStore values form a row.
44 let RowFields = ["BaseOpcode"];
57 // Instructions with the same BaseOpcode and isNVStore values form a row.
58 let RowFields = ["BaseOpcode"];
117 string BaseOpcode = opstr;
/external/swiftshader/third_party/llvm-7.0/llvm/docs/
DHowToUseInstrMappings.rst84 // instructions need to have same value for BaseOpcode field. It can be any
87 let RowFields = ["BaseOpcode"];
146 let BaseOpcode = "ADD";
154 let BaseOpcode = "ADD";
162 let BaseOpcode = "ADD";
169 ``PredRel`` is excluded from the analysis. ``BaseOpcode`` is another important
/external/llvm/docs/
DHowToUseInstrMappings.rst84 // instructions need to have same value for BaseOpcode field. It can be any
87 let RowFields = ["BaseOpcode"];
146 let BaseOpcode = "ADD";
154 let BaseOpcode = "ADD";
162 let BaseOpcode = "ADD";
169 ``PredRel`` is excluded from the analysis. ``BaseOpcode`` is another important
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/Utils/
DAMDGPUBaseInfo.h189 MIMGBaseOpcode BaseOpcode; member
203 const MIMGBaseOpcodeInfo *getMIMGBaseOpcodeInfo(unsigned BaseOpcode);
224 int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding,
DAMDGPUBaseInfo.cpp104 uint16_t BaseOpcode; member
116 int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding, in getMIMGOpcode() argument
118 const MIMGInfo *Info = getMIMGOpcodeHelper(BaseOpcode, MIMGEncoding, in getMIMGOpcode()
126 getMIMGOpcodeHelper(OrigInfo->BaseOpcode, OrigInfo->MIMGEncoding, in getMaskedMIMGOp()

12