1//===-- MipsInstrFormats.td - Mips Instruction Formats -----*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Describe MIPS instructions format 12// 13// CPU INSTRUCTION FORMATS 14// 15// opcode - operation code. 16// rs - src reg. 17// rt - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr). 18// rd - dst reg, only used on 3 regs instr. 19// shamt - only used on shift instructions, contains the shift amount. 20// funct - combined with opcode field give us an operation code. 21// 22//===----------------------------------------------------------------------===// 23 24// Format specifies the encoding used by the instruction. This is part of the 25// ad-hoc solution used to emit machine instruction encodings by our machine 26// code emitter. 27class Format<bits<4> val> { 28 bits<4> Value = val; 29} 30 31def Pseudo : Format<0>; 32def FrmR : Format<1>; 33def FrmI : Format<2>; 34def FrmJ : Format<3>; 35def FrmFR : Format<4>; 36def FrmFI : Format<5>; 37def FrmOther : Format<6>; // Instruction w/ a custom format 38 39class MMRel; 40 41def Std2MicroMips : InstrMapping { 42 let FilterClass = "MMRel"; 43 // Instructions with the same BaseOpcode and isNVStore values form a row. 44 let RowFields = ["BaseOpcode"]; 45 // Instructions with the same predicate sense form a column. 46 let ColFields = ["Arch"]; 47 // The key column is the unpredicated instructions. 48 let KeyCol = ["se"]; 49 // Value columns are PredSense=true and PredSense=false 50 let ValueCols = [["se"], ["micromips"]]; 51} 52 53class StdMMR6Rel; 54 55def Std2MicroMipsR6 : InstrMapping { 56 let FilterClass = "StdMMR6Rel"; 57 // Instructions with the same BaseOpcode and isNVStore values form a row. 58 let RowFields = ["BaseOpcode"]; 59 // Instructions with the same predicate sense form a column. 60 let ColFields = ["Arch"]; 61 // The key column is the unpredicated instructions. 62 let KeyCol = ["se"]; 63 // Value columns are PredSense=true and PredSense=false 64 let ValueCols = [["se"], ["micromipsr6"]]; 65} 66 67class StdArch { 68 string Arch = "se"; 69} 70 71// Generic Mips Format 72class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern, 73 InstrItinClass itin, Format f>: Instruction 74{ 75 field bits<32> Inst; 76 Format Form = f; 77 78 let Namespace = "Mips"; 79 80 let Size = 4; 81 82 bits<6> Opcode = 0; 83 84 // Top 6 bits are the 'opcode' field 85 let Inst{31-26} = Opcode; 86 87 let OutOperandList = outs; 88 let InOperandList = ins; 89 90 let AsmString = asmstr; 91 let Pattern = pattern; 92 let Itinerary = itin; 93 94 // 95 // Attributes specific to Mips instructions... 96 // 97 bits<4> FormBits = Form.Value; 98 bit isCTI = 0; // Any form of Control Transfer Instruction. 99 // Required for MIPSR6 100 bit hasForbiddenSlot = 0; // Instruction has a forbidden slot. 101 102 // TSFlags layout should be kept in sync with MipsInstrInfo.h. 103 let TSFlags{3-0} = FormBits; 104 let TSFlags{4} = isCTI; 105 let TSFlags{5} = hasForbiddenSlot; 106 107 let DecoderNamespace = "Mips"; 108 109 field bits<32> SoftFail = 0; 110} 111 112// Mips32/64 Instruction Format 113class InstSE<dag outs, dag ins, string asmstr, list<dag> pattern, 114 InstrItinClass itin, Format f, string opstr = ""> : 115 MipsInst<outs, ins, asmstr, pattern, itin, f>, PredicateControl { 116 let EncodingPredicates = [HasStdEnc]; 117 string BaseOpcode = opstr; 118 string Arch; 119} 120 121// Mips Pseudo Instructions Format 122class MipsPseudo<dag outs, dag ins, list<dag> pattern, 123 InstrItinClass itin = IIPseudo> : 124 MipsInst<outs, ins, "", pattern, itin, Pseudo> { 125 let isCodeGenOnly = 1; 126 let isPseudo = 1; 127} 128 129// Mips32/64 Pseudo Instruction Format 130class PseudoSE<dag outs, dag ins, list<dag> pattern, 131 InstrItinClass itin = IIPseudo> : 132 MipsPseudo<outs, ins, pattern, itin>, PredicateControl { 133 let EncodingPredicates = [HasStdEnc]; 134} 135 136// Pseudo-instructions for alternate assembly syntax (never used by codegen). 137// These are aliases that require C++ handling to convert to the target 138// instruction, while InstAliases can be handled directly by tblgen. 139class MipsAsmPseudoInst<dag outs, dag ins, string asmstr>: 140 MipsInst<outs, ins, asmstr, [], IIPseudo, Pseudo>, PredicateControl { 141 let isPseudo = 1; 142 let Pattern = []; 143} 144//===----------------------------------------------------------------------===// 145// Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|> 146//===----------------------------------------------------------------------===// 147 148class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr, 149 list<dag> pattern, InstrItinClass itin>: 150 InstSE<outs, ins, asmstr, pattern, itin, FrmR> 151{ 152 bits<5> rd; 153 bits<5> rs; 154 bits<5> rt; 155 bits<5> shamt; 156 bits<6> funct; 157 158 let Opcode = op; 159 let funct = _funct; 160 161 let Inst{25-21} = rs; 162 let Inst{20-16} = rt; 163 let Inst{15-11} = rd; 164 let Inst{10-6} = shamt; 165 let Inst{5-0} = funct; 166} 167 168//===----------------------------------------------------------------------===// 169// Format I instruction class in Mips : <|opcode|rs|rt|immediate|> 170//===----------------------------------------------------------------------===// 171 172class FI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern, 173 InstrItinClass itin>: InstSE<outs, ins, asmstr, pattern, itin, FrmI> 174{ 175 bits<5> rt; 176 bits<5> rs; 177 bits<16> imm16; 178 179 let Opcode = op; 180 181 let Inst{25-21} = rs; 182 let Inst{20-16} = rt; 183 let Inst{15-0} = imm16; 184} 185 186class BranchBase<bits<6> op, dag outs, dag ins, string asmstr, 187 list<dag> pattern, InstrItinClass itin>: 188 InstSE<outs, ins, asmstr, pattern, itin, FrmI> 189{ 190 bits<5> rs; 191 bits<5> rt; 192 bits<16> imm16; 193 194 let Opcode = op; 195 196 let Inst{25-21} = rs; 197 let Inst{20-16} = rt; 198 let Inst{15-0} = imm16; 199} 200 201//===----------------------------------------------------------------------===// 202// Format J instruction class in Mips : <|opcode|address|> 203//===----------------------------------------------------------------------===// 204 205class FJ<bits<6> op> : StdArch 206{ 207 bits<26> target; 208 209 bits<32> Inst; 210 211 let Inst{31-26} = op; 212 let Inst{25-0} = target; 213} 214 215//===----------------------------------------------------------------------===// 216// MFC instruction class in Mips : <|op|mf|rt|rd|0000000|sel|> 217//===----------------------------------------------------------------------===// 218class MFC3OP_FM<bits<6> op, bits<5> mfmt> 219{ 220 bits<5> rt; 221 bits<5> rd; 222 bits<3> sel; 223 224 bits<32> Inst; 225 226 let Inst{31-26} = op; 227 let Inst{25-21} = mfmt; 228 let Inst{20-16} = rt; 229 let Inst{15-11} = rd; 230 let Inst{10-3} = 0; 231 let Inst{2-0} = sel; 232} 233 234class MFC2OP_FM<bits<6> op, bits<5> mfmt> : StdArch { 235 bits<5> rt; 236 bits<16> imm16; 237 238 bits<32> Inst; 239 240 let Inst{31-26} = op; 241 let Inst{25-21} = mfmt; 242 let Inst{20-16} = rt; 243 let Inst{15-0} = imm16; 244} 245 246class ADD_FM<bits<6> op, bits<6> funct> : StdArch { 247 bits<5> rd; 248 bits<5> rs; 249 bits<5> rt; 250 251 bits<32> Inst; 252 253 let Inst{31-26} = op; 254 let Inst{25-21} = rs; 255 let Inst{20-16} = rt; 256 let Inst{15-11} = rd; 257 let Inst{10-6} = 0; 258 let Inst{5-0} = funct; 259} 260 261class ADDI_FM<bits<6> op> : StdArch { 262 bits<5> rs; 263 bits<5> rt; 264 bits<16> imm16; 265 266 bits<32> Inst; 267 268 let Inst{31-26} = op; 269 let Inst{25-21} = rs; 270 let Inst{20-16} = rt; 271 let Inst{15-0} = imm16; 272} 273 274class SRA_FM<bits<6> funct, bit rotate> : StdArch { 275 bits<5> rd; 276 bits<5> rt; 277 bits<5> shamt; 278 279 bits<32> Inst; 280 281 let Inst{31-26} = 0; 282 let Inst{25-22} = 0; 283 let Inst{21} = rotate; 284 let Inst{20-16} = rt; 285 let Inst{15-11} = rd; 286 let Inst{10-6} = shamt; 287 let Inst{5-0} = funct; 288} 289 290class SRLV_FM<bits<6> funct, bit rotate> : StdArch { 291 bits<5> rd; 292 bits<5> rt; 293 bits<5> rs; 294 295 bits<32> Inst; 296 297 let Inst{31-26} = 0; 298 let Inst{25-21} = rs; 299 let Inst{20-16} = rt; 300 let Inst{15-11} = rd; 301 let Inst{10-7} = 0; 302 let Inst{6} = rotate; 303 let Inst{5-0} = funct; 304} 305 306class BEQ_FM<bits<6> op> : StdArch { 307 bits<5> rs; 308 bits<5> rt; 309 bits<16> offset; 310 311 bits<32> Inst; 312 313 let Inst{31-26} = op; 314 let Inst{25-21} = rs; 315 let Inst{20-16} = rt; 316 let Inst{15-0} = offset; 317} 318 319class BGEZ_FM<bits<6> op, bits<5> funct> : StdArch { 320 bits<5> rs; 321 bits<16> offset; 322 323 bits<32> Inst; 324 325 let Inst{31-26} = op; 326 let Inst{25-21} = rs; 327 let Inst{20-16} = funct; 328 let Inst{15-0} = offset; 329} 330 331class BBIT_FM<bits<6> op> : StdArch { 332 bits<5> rs; 333 bits<5> p; 334 bits<16> offset; 335 336 bits<32> Inst; 337 338 let Inst{31-26} = op; 339 let Inst{25-21} = rs; 340 let Inst{20-16} = p; 341 let Inst{15-0} = offset; 342} 343 344class SLTI_FM<bits<6> op> : StdArch { 345 bits<5> rt; 346 bits<5> rs; 347 bits<16> imm16; 348 349 bits<32> Inst; 350 351 let Inst{31-26} = op; 352 let Inst{25-21} = rs; 353 let Inst{20-16} = rt; 354 let Inst{15-0} = imm16; 355} 356 357class MFLO_FM<bits<6> funct> : StdArch { 358 bits<5> rd; 359 360 bits<32> Inst; 361 362 let Inst{31-26} = 0; 363 let Inst{25-16} = 0; 364 let Inst{15-11} = rd; 365 let Inst{10-6} = 0; 366 let Inst{5-0} = funct; 367} 368 369class MTLO_FM<bits<6> funct> : StdArch { 370 bits<5> rs; 371 372 bits<32> Inst; 373 374 let Inst{31-26} = 0; 375 let Inst{25-21} = rs; 376 let Inst{20-6} = 0; 377 let Inst{5-0} = funct; 378} 379 380class SEB_FM<bits<5> funct, bits<6> funct2> : StdArch { 381 bits<5> rd; 382 bits<5> rt; 383 384 bits<32> Inst; 385 386 let Inst{31-26} = 0x1f; 387 let Inst{25-21} = 0; 388 let Inst{20-16} = rt; 389 let Inst{15-11} = rd; 390 let Inst{10-6} = funct; 391 let Inst{5-0} = funct2; 392} 393 394class CLO_FM<bits<6> funct> : StdArch { 395 bits<5> rd; 396 bits<5> rs; 397 bits<5> rt; 398 399 bits<32> Inst; 400 401 let Inst{31-26} = 0x1c; 402 let Inst{25-21} = rs; 403 let Inst{20-16} = rt; 404 let Inst{15-11} = rd; 405 let Inst{10-6} = 0; 406 let Inst{5-0} = funct; 407 let rt = rd; 408} 409 410class LUI_FM : StdArch { 411 bits<5> rt; 412 bits<16> imm16; 413 414 bits<32> Inst; 415 416 let Inst{31-26} = 0xf; 417 let Inst{25-21} = 0; 418 let Inst{20-16} = rt; 419 let Inst{15-0} = imm16; 420} 421 422class JALR_FM { 423 bits<5> rd; 424 bits<5> rs; 425 426 bits<32> Inst; 427 428 let Inst{31-26} = 0; 429 let Inst{25-21} = rs; 430 let Inst{20-16} = 0; 431 let Inst{15-11} = rd; 432 let Inst{10-6} = 0; 433 let Inst{5-0} = 9; 434} 435 436class BGEZAL_FM<bits<5> funct> : StdArch { 437 bits<5> rs; 438 bits<16> offset; 439 440 bits<32> Inst; 441 442 let Inst{31-26} = 1; 443 let Inst{25-21} = rs; 444 let Inst{20-16} = funct; 445 let Inst{15-0} = offset; 446} 447 448class SYNC_FM : StdArch { 449 bits<5> stype; 450 451 bits<32> Inst; 452 453 let Inst{31-26} = 0; 454 let Inst{10-6} = stype; 455 let Inst{5-0} = 0xf; 456} 457 458class SYNCI_FM : StdArch { 459 // Produced by the mem_simm16 address as reg << 16 | imm (see getMemEncoding). 460 bits<21> addr; 461 bits<5> rs = addr{20-16}; 462 bits<16> offset = addr{15-0}; 463 464 bits<32> Inst; 465 466 let Inst{31-26} = 0b000001; 467 let Inst{25-21} = rs; 468 let Inst{20-16} = 0b11111; 469 let Inst{15-0} = offset; 470} 471 472class MULT_FM<bits<6> op, bits<6> funct> : StdArch { 473 bits<5> rs; 474 bits<5> rt; 475 476 bits<32> Inst; 477 478 let Inst{31-26} = op; 479 let Inst{25-21} = rs; 480 let Inst{20-16} = rt; 481 let Inst{15-6} = 0; 482 let Inst{5-0} = funct; 483} 484 485class EXT_FM<bits<6> funct> : StdArch { 486 bits<5> rt; 487 bits<5> rs; 488 bits<5> pos; 489 bits<5> size; 490 491 bits<32> Inst; 492 493 let Inst{31-26} = 0x1f; 494 let Inst{25-21} = rs; 495 let Inst{20-16} = rt; 496 let Inst{15-11} = size; 497 let Inst{10-6} = pos; 498 let Inst{5-0} = funct; 499} 500 501class RDHWR_FM : StdArch { 502 bits<5> rt; 503 bits<5> rd; 504 505 bits<32> Inst; 506 507 let Inst{31-26} = 0x1f; 508 let Inst{25-21} = 0; 509 let Inst{20-16} = rt; 510 let Inst{15-11} = rd; 511 let Inst{10-6} = 0; 512 let Inst{5-0} = 0x3b; 513} 514 515class TEQ_FM<bits<6> funct> : StdArch { 516 bits<5> rs; 517 bits<5> rt; 518 bits<10> code_; 519 520 bits<32> Inst; 521 522 let Inst{31-26} = 0; 523 let Inst{25-21} = rs; 524 let Inst{20-16} = rt; 525 let Inst{15-6} = code_; 526 let Inst{5-0} = funct; 527} 528 529class TEQI_FM<bits<5> funct> : StdArch { 530 bits<5> rs; 531 bits<16> imm16; 532 533 bits<32> Inst; 534 535 let Inst{31-26} = 1; 536 let Inst{25-21} = rs; 537 let Inst{20-16} = funct; 538 let Inst{15-0} = imm16; 539} 540 541class WAIT_FM : StdArch { 542 bits<32> Inst; 543 544 let Inst{31-26} = 0x10; 545 let Inst{25} = 1; 546 let Inst{24-6} = 0; 547 let Inst{5-0} = 0x20; 548} 549 550class EXTS_FM<bits<6> funct> : StdArch { 551 bits<5> rt; 552 bits<5> rs; 553 bits<5> pos; 554 bits<5> lenm1; 555 556 bits<32> Inst; 557 558 let Inst{31-26} = 0x1c; 559 let Inst{25-21} = rs; 560 let Inst{20-16} = rt; 561 let Inst{15-11} = lenm1; 562 let Inst{10-6} = pos; 563 let Inst{5-0} = funct; 564} 565 566class MTMR_FM<bits<6> funct> : StdArch { 567 bits<5> rs; 568 569 bits<32> Inst; 570 571 let Inst{31-26} = 0x1c; 572 let Inst{25-21} = rs; 573 let Inst{20-6} = 0; 574 let Inst{5-0} = funct; 575} 576 577class POP_FM<bits<6> funct> : StdArch { 578 bits<5> rd; 579 bits<5> rs; 580 581 bits<32> Inst; 582 583 let Inst{31-26} = 0x1c; 584 let Inst{25-21} = rs; 585 let Inst{20-16} = 0; 586 let Inst{15-11} = rd; 587 let Inst{10-6} = 0; 588 let Inst{5-0} = funct; 589} 590 591class SEQ_FM<bits<6> funct> : StdArch { 592 bits<5> rd; 593 bits<5> rs; 594 bits<5> rt; 595 596 bits<32> Inst; 597 598 let Inst{31-26} = 0x1c; 599 let Inst{25-21} = rs; 600 let Inst{20-16} = rt; 601 let Inst{15-11} = rd; 602 let Inst{10-6} = 0; 603 let Inst{5-0} = funct; 604} 605 606class SEQI_FM<bits<6> funct> : StdArch { 607 bits<5> rs; 608 bits<5> rt; 609 bits<10> imm10; 610 611 bits<32> Inst; 612 613 let Inst{31-26} = 0x1c; 614 let Inst{25-21} = rs; 615 let Inst{20-16} = rt; 616 let Inst{15-6} = imm10; 617 let Inst{5-0} = funct; 618} 619 620//===----------------------------------------------------------------------===// 621// System calls format <op|code_|funct> 622//===----------------------------------------------------------------------===// 623 624class SYS_FM<bits<6> funct> : StdArch 625{ 626 bits<20> code_; 627 bits<32> Inst; 628 let Inst{31-26} = 0x0; 629 let Inst{25-6} = code_; 630 let Inst{5-0} = funct; 631} 632 633//===----------------------------------------------------------------------===// 634// Break instruction format <op|code_1|funct> 635//===----------------------------------------------------------------------===// 636 637class BRK_FM<bits<6> funct> : StdArch 638{ 639 bits<10> code_1; 640 bits<10> code_2; 641 bits<32> Inst; 642 let Inst{31-26} = 0x0; 643 let Inst{25-16} = code_1; 644 let Inst{15-6} = code_2; 645 let Inst{5-0} = funct; 646} 647 648//===----------------------------------------------------------------------===// 649// Exception return format <Cop0|1|0|funct> 650//===----------------------------------------------------------------------===// 651 652class ER_FM<bits<6> funct, bit LLBit> : StdArch 653{ 654 bits<32> Inst; 655 let Inst{31-26} = 0x10; 656 let Inst{25} = 1; 657 let Inst{24-7} = 0; 658 let Inst{6} = LLBit; 659 let Inst{5-0} = funct; 660} 661 662//===----------------------------------------------------------------------===// 663// Enable/disable interrupt instruction format <Cop0|MFMC0|rt|12|0|sc|0|0> 664//===----------------------------------------------------------------------===// 665 666class EI_FM<bits<1> sc> : StdArch 667{ 668 bits<32> Inst; 669 bits<5> rt; 670 let Inst{31-26} = 0x10; 671 let Inst{25-21} = 0xb; 672 let Inst{20-16} = rt; 673 let Inst{15-11} = 0xc; 674 let Inst{10-6} = 0; 675 let Inst{5} = sc; 676 let Inst{4-0} = 0; 677} 678 679//===----------------------------------------------------------------------===// 680// 681// FLOATING POINT INSTRUCTION FORMATS 682// 683// opcode - operation code. 684// fs - src reg. 685// ft - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr). 686// fd - dst reg, only used on 3 regs instr. 687// fmt - double or single precision. 688// funct - combined with opcode field give us an operation code. 689// 690//===----------------------------------------------------------------------===// 691 692//===----------------------------------------------------------------------===// 693// Format FI instruction class in Mips : <|opcode|base|ft|immediate|> 694//===----------------------------------------------------------------------===// 695 696class FFI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern>: 697 InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmFI> 698{ 699 bits<5> ft; 700 bits<5> base; 701 bits<16> imm16; 702 703 let Opcode = op; 704 705 let Inst{25-21} = base; 706 let Inst{20-16} = ft; 707 let Inst{15-0} = imm16; 708} 709 710class ADDS_FM<bits<6> funct, bits<5> fmt> : StdArch { 711 bits<5> fd; 712 bits<5> fs; 713 bits<5> ft; 714 715 bits<32> Inst; 716 717 let Inst{31-26} = 0x11; 718 let Inst{25-21} = fmt; 719 let Inst{20-16} = ft; 720 let Inst{15-11} = fs; 721 let Inst{10-6} = fd; 722 let Inst{5-0} = funct; 723} 724 725class ABSS_FM<bits<6> funct, bits<5> fmt> : StdArch { 726 bits<5> fd; 727 bits<5> fs; 728 729 bits<32> Inst; 730 731 let Inst{31-26} = 0x11; 732 let Inst{25-21} = fmt; 733 let Inst{20-16} = 0; 734 let Inst{15-11} = fs; 735 let Inst{10-6} = fd; 736 let Inst{5-0} = funct; 737} 738 739class MFC1_FM<bits<5> funct> : StdArch { 740 bits<5> rt; 741 bits<5> fs; 742 743 bits<32> Inst; 744 745 let Inst{31-26} = 0x11; 746 let Inst{25-21} = funct; 747 let Inst{20-16} = rt; 748 let Inst{15-11} = fs; 749 let Inst{10-0} = 0; 750} 751 752class LW_FM<bits<6> op> : StdArch { 753 bits<5> rt; 754 bits<21> addr; 755 756 bits<32> Inst; 757 758 let Inst{31-26} = op; 759 let Inst{25-21} = addr{20-16}; 760 let Inst{20-16} = rt; 761 let Inst{15-0} = addr{15-0}; 762} 763 764class MADDS_FM<bits<3> funct, bits<3> fmt> : StdArch { 765 bits<5> fd; 766 bits<5> fr; 767 bits<5> fs; 768 bits<5> ft; 769 770 bits<32> Inst; 771 772 let Inst{31-26} = 0x13; 773 let Inst{25-21} = fr; 774 let Inst{20-16} = ft; 775 let Inst{15-11} = fs; 776 let Inst{10-6} = fd; 777 let Inst{5-3} = funct; 778 let Inst{2-0} = fmt; 779} 780 781class LWXC1_FM<bits<6> funct> : StdArch { 782 bits<5> fd; 783 bits<5> base; 784 bits<5> index; 785 786 bits<32> Inst; 787 788 let Inst{31-26} = 0x13; 789 let Inst{25-21} = base; 790 let Inst{20-16} = index; 791 let Inst{15-11} = 0; 792 let Inst{10-6} = fd; 793 let Inst{5-0} = funct; 794} 795 796class SWXC1_FM<bits<6> funct> : StdArch { 797 bits<5> fs; 798 bits<5> base; 799 bits<5> index; 800 801 bits<32> Inst; 802 803 let Inst{31-26} = 0x13; 804 let Inst{25-21} = base; 805 let Inst{20-16} = index; 806 let Inst{15-11} = fs; 807 let Inst{10-6} = 0; 808 let Inst{5-0} = funct; 809} 810 811class BC1F_FM<bit nd, bit tf> : StdArch { 812 bits<3> fcc; 813 bits<16> offset; 814 815 bits<32> Inst; 816 817 let Inst{31-26} = 0x11; 818 let Inst{25-21} = 0x8; 819 let Inst{20-18} = fcc; 820 let Inst{17} = nd; 821 let Inst{16} = tf; 822 let Inst{15-0} = offset; 823} 824 825class CEQS_FM<bits<5> fmt> : StdArch { 826 bits<5> fs; 827 bits<5> ft; 828 bits<4> cond; 829 830 bits<32> Inst; 831 832 let Inst{31-26} = 0x11; 833 let Inst{25-21} = fmt; 834 let Inst{20-16} = ft; 835 let Inst{15-11} = fs; 836 let Inst{10-8} = 0; // cc 837 let Inst{7-4} = 0x3; 838 let Inst{3-0} = cond; 839} 840 841class C_COND_FM<bits<5> fmt, bits<4> c> : CEQS_FM<fmt> { 842 let cond = c; 843} 844 845class CMov_I_F_FM<bits<6> funct, bits<5> fmt> : StdArch { 846 bits<5> fd; 847 bits<5> fs; 848 bits<5> rt; 849 850 bits<32> Inst; 851 852 let Inst{31-26} = 0x11; 853 let Inst{25-21} = fmt; 854 let Inst{20-16} = rt; 855 let Inst{15-11} = fs; 856 let Inst{10-6} = fd; 857 let Inst{5-0} = funct; 858} 859 860class CMov_F_I_FM<bit tf> : StdArch { 861 bits<5> rd; 862 bits<5> rs; 863 bits<3> fcc; 864 865 bits<32> Inst; 866 867 let Inst{31-26} = 0; 868 let Inst{25-21} = rs; 869 let Inst{20-18} = fcc; 870 let Inst{17} = 0; 871 let Inst{16} = tf; 872 let Inst{15-11} = rd; 873 let Inst{10-6} = 0; 874 let Inst{5-0} = 1; 875} 876 877class CMov_F_F_FM<bits<5> fmt, bit tf> : StdArch { 878 bits<5> fd; 879 bits<5> fs; 880 bits<3> fcc; 881 882 bits<32> Inst; 883 884 let Inst{31-26} = 0x11; 885 let Inst{25-21} = fmt; 886 let Inst{20-18} = fcc; 887 let Inst{17} = 0; 888 let Inst{16} = tf; 889 let Inst{15-11} = fs; 890 let Inst{10-6} = fd; 891 let Inst{5-0} = 0x11; 892} 893 894class BARRIER_FM<bits<5> op> : StdArch { 895 bits<32> Inst; 896 897 let Inst{31-26} = 0; // SPECIAL 898 let Inst{25-21} = 0; 899 let Inst{20-16} = 0; // rt = 0 900 let Inst{15-11} = 0; // rd = 0 901 let Inst{10-6} = op; // Operation 902 let Inst{5-0} = 0; // SLL 903} 904 905class SDBBP_FM : StdArch { 906 bits<20> code_; 907 908 bits<32> Inst; 909 910 let Inst{31-26} = 0b011100; // SPECIAL2 911 let Inst{25-6} = code_; 912 let Inst{5-0} = 0b111111; // SDBBP 913} 914 915class JR_HB_FM<bits<6> op> : StdArch{ 916 bits<5> rs; 917 918 bits<32> Inst; 919 920 let Inst{31-26} = 0; // SPECIAL 921 let Inst{25-21} = rs; 922 let Inst{20-11} = 0; 923 let Inst{10} = 1; 924 let Inst{9-6} = 0; 925 let Inst{5-0} = op; 926} 927 928class JALR_HB_FM<bits<6> op> : StdArch { 929 bits<5> rd; 930 bits<5> rs; 931 932 bits<32> Inst; 933 934 let Inst{31-26} = 0; // SPECIAL 935 let Inst{25-21} = rs; 936 let Inst{20-16} = 0; 937 let Inst{15-11} = rd; 938 let Inst{10} = 1; 939 let Inst{9-6} = 0; 940 let Inst{5-0} = op; 941} 942 943class COP0_TLB_FM<bits<6> op> : StdArch { 944 bits<32> Inst; 945 946 let Inst{31-26} = 0x10; // COP0 947 let Inst{25} = 1; // CO 948 let Inst{24-6} = 0; 949 let Inst{5-0} = op; // Operation 950} 951 952class CACHEOP_FM<bits<6> op> : StdArch { 953 bits<21> addr; 954 bits<5> hint; 955 bits<5> base = addr{20-16}; 956 bits<16> offset = addr{15-0}; 957 958 bits<32> Inst; 959 960 let Inst{31-26} = op; 961 let Inst{25-21} = base; 962 let Inst{20-16} = hint; 963 let Inst{15-0} = offset; 964} 965