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Searched refs:CLKMGR_PLLC0_DIV_MASK (Results 1 – 2 of 2) sorted by relevance

/external/u-boot/arch/arm/mach-socfpga/
Dclock_manager_s10.c245 CLKMGR_PLLC0_DIV_MASK); in cm_get_mpu_clk_hz()
282 CLKMGR_PLLC0_DIV_MASK); in cm_get_l3_main_clk_hz()
/external/u-boot/arch/arm/mach-socfpga/include/mach/
Dclock_manager_s10.h176 #define CLKMGR_PLLC0_DIV_MASK 0xff macro