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1 /* SPDX-License-Identifier: GPL-2.0
2  *
3  * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
4  *
5  */
6 
7 #ifndef	_CLOCK_MANAGER_S10_
8 #define	_CLOCK_MANAGER_S10_
9 
10 /* Clock speed accessors */
11 unsigned long cm_get_mpu_clk_hz(void);
12 unsigned long cm_get_sdram_clk_hz(void);
13 unsigned int cm_get_l4_sp_clk_hz(void);
14 unsigned int cm_get_mmc_controller_clk_hz(void);
15 unsigned int cm_get_qspi_controller_clk_hz(void);
16 unsigned int cm_get_spi_controller_clk_hz(void);
17 const unsigned int cm_get_osc_clk_hz(void);
18 const unsigned int cm_get_f2s_per_ref_clk_hz(void);
19 const unsigned int cm_get_f2s_sdr_ref_clk_hz(void);
20 const unsigned int cm_get_intosc_clk_hz(void);
21 const unsigned int cm_get_fpga_clk_hz(void);
22 
23 #define CLKMGR_EOSC1_HZ		25000000
24 #define CLKMGR_INTOSC_HZ	460000000
25 #define CLKMGR_FPGA_CLK_HZ	50000000
26 
27 /* Clock configuration accessors */
28 const struct cm_config * const cm_get_default_config(void);
29 
30 struct cm_config {
31 	/* main group */
32 	u32 main_pll_mpuclk;
33 	u32 main_pll_nocclk;
34 	u32 main_pll_cntr2clk;
35 	u32 main_pll_cntr3clk;
36 	u32 main_pll_cntr4clk;
37 	u32 main_pll_cntr5clk;
38 	u32 main_pll_cntr6clk;
39 	u32 main_pll_cntr7clk;
40 	u32 main_pll_cntr8clk;
41 	u32 main_pll_cntr9clk;
42 	u32 main_pll_nocdiv;
43 	u32 main_pll_pllglob;
44 	u32 main_pll_fdbck;
45 	u32 main_pll_pllc0;
46 	u32 main_pll_pllc1;
47 	u32 spare;
48 
49 	/* peripheral group */
50 	u32 per_pll_cntr2clk;
51 	u32 per_pll_cntr3clk;
52 	u32 per_pll_cntr4clk;
53 	u32 per_pll_cntr5clk;
54 	u32 per_pll_cntr6clk;
55 	u32 per_pll_cntr7clk;
56 	u32 per_pll_cntr8clk;
57 	u32 per_pll_cntr9clk;
58 	u32 per_pll_emacctl;
59 	u32 per_pll_gpiodiv;
60 	u32 per_pll_pllglob;
61 	u32 per_pll_fdbck;
62 	u32 per_pll_pllc0;
63 	u32 per_pll_pllc1;
64 
65 	/* incoming clock */
66 	u32 hps_osc_clk_hz;
67 	u32 fpga_clk_hz;
68 };
69 
70 void cm_basic_init(const struct cm_config * const cfg);
71 
72 struct socfpga_clock_manager_main_pll {
73 	u32	en;
74 	u32	ens;
75 	u32	enr;
76 	u32	bypass;
77 	u32	bypasss;
78 	u32	bypassr;
79 	u32	mpuclk;
80 	u32	nocclk;
81 	u32	cntr2clk;
82 	u32	cntr3clk;
83 	u32	cntr4clk;
84 	u32	cntr5clk;
85 	u32	cntr6clk;
86 	u32	cntr7clk;
87 	u32	cntr8clk;
88 	u32	cntr9clk;
89 	u32	nocdiv;
90 	u32	pllglob;
91 	u32	fdbck;
92 	u32	mem;
93 	u32	memstat;
94 	u32	pllc0;
95 	u32	pllc1;
96 	u32	vcocalib;
97 	u32	_pad_0x90_0xA0[5];
98 };
99 
100 struct socfpga_clock_manager_per_pll {
101 	u32	en;
102 	u32	ens;
103 	u32	enr;
104 	u32	bypass;
105 	u32	bypasss;
106 	u32	bypassr;
107 	u32	cntr2clk;
108 	u32	cntr3clk;
109 	u32	cntr4clk;
110 	u32	cntr5clk;
111 	u32	cntr6clk;
112 	u32	cntr7clk;
113 	u32	cntr8clk;
114 	u32	cntr9clk;
115 	u32	emacctl;
116 	u32	gpiodiv;
117 	u32	pllglob;
118 	u32	fdbck;
119 	u32	mem;
120 	u32	memstat;
121 	u32	pllc0;
122 	u32	pllc1;
123 	u32	vcocalib;
124 	u32	_pad_0x100_0x124[10];
125 };
126 
127 struct socfpga_clock_manager {
128 	u32	ctrl;
129 	u32	stat;
130 	u32	testioctrl;
131 	u32	intrgen;
132 	u32	intrmsk;
133 	u32	intrclr;
134 	u32	intrsts;
135 	u32	intrstk;
136 	u32	intrraw;
137 	u32	_pad_0x24_0x2c[3];
138 	struct socfpga_clock_manager_main_pll main_pll;
139 	struct socfpga_clock_manager_per_pll per_pll;
140 };
141 
142 #define CLKMGR_CTRL_SAFEMODE				BIT(0)
143 #define CLKMGR_BYPASS_MAINPLL_ALL			0x00000007
144 #define CLKMGR_BYPASS_PERPLL_ALL			0x0000007f
145 
146 #define CLKMGR_INTER_MAINPLLLOCKED_MASK			0x00000001
147 #define CLKMGR_INTER_PERPLLLOCKED_MASK			0x00000002
148 #define CLKMGR_INTER_MAINPLLLOST_MASK			0x00000004
149 #define CLKMGR_INTER_PERPLLLOST_MASK			0x00000008
150 #define CLKMGR_STAT_BUSY				BIT(0)
151 #define CLKMGR_STAT_MAINPLL_LOCKED			BIT(8)
152 #define CLKMGR_STAT_PERPLL_LOCKED			BIT(9)
153 
154 #define CLKMGR_PLLGLOB_PD_MASK				0x00000001
155 #define CLKMGR_PLLGLOB_RST_MASK				0x00000002
156 #define CLKMGR_PLLGLOB_VCO_PSRC_MASK			0X3
157 #define CLKMGR_PLLGLOB_VCO_PSRC_OFFSET			16
158 #define CLKMGR_VCO_PSRC_EOSC1				0
159 #define CLKMGR_VCO_PSRC_INTOSC				1
160 #define CLKMGR_VCO_PSRC_F2S				2
161 #define CLKMGR_PLLGLOB_REFCLKDIV_MASK			0X3f
162 #define CLKMGR_PLLGLOB_REFCLKDIV_OFFSET			8
163 
164 #define CLKMGR_CLKSRC_MASK				0x7
165 #define CLKMGR_CLKSRC_OFFSET				16
166 #define CLKMGR_CLKSRC_MAIN				0
167 #define CLKMGR_CLKSRC_PER				1
168 #define CLKMGR_CLKSRC_OSC1				2
169 #define CLKMGR_CLKSRC_INTOSC				3
170 #define CLKMGR_CLKSRC_FPGA				4
171 #define CLKMGR_CLKCNT_MSK				0x7ff
172 
173 #define CLKMGR_FDBCK_MDIV_MASK				0xff
174 #define CLKMGR_FDBCK_MDIV_OFFSET			24
175 
176 #define CLKMGR_PLLC0_DIV_MASK				0xff
177 #define CLKMGR_PLLC1_DIV_MASK				0xff
178 #define CLKMGR_PLLC0_EN_OFFSET				27
179 #define CLKMGR_PLLC1_EN_OFFSET				24
180 
181 #define CLKMGR_NOCDIV_L4MAIN_OFFSET			0
182 #define CLKMGR_NOCDIV_L4MPCLK_OFFSET			8
183 #define CLKMGR_NOCDIV_L4SPCLK_OFFSET			16
184 #define CLKMGR_NOCDIV_CSATCLK_OFFSET			24
185 #define CLKMGR_NOCDIV_CSTRACECLK_OFFSET			26
186 #define CLKMGR_NOCDIV_CSPDBGCLK_OFFSET			28
187 
188 #define CLKMGR_NOCDIV_L4SPCLK_MASK			0X3
189 #define CLKMGR_NOCDIV_DIV1				0
190 #define CLKMGR_NOCDIV_DIV2				1
191 #define CLKMGR_NOCDIV_DIV4				2
192 #define CLKMGR_NOCDIV_DIV8				3
193 #define CLKMGR_CSPDBGCLK_DIV1				0
194 #define CLKMGR_CSPDBGCLK_DIV4				1
195 
196 #define CLKMGR_MSCNT_CONST				200
197 #define CLKMGR_MDIV_CONST				6
198 #define CLKMGR_HSCNT_CONST				9
199 
200 #define CLKMGR_VCOCALIB_MSCNT_MASK			0xff
201 #define CLKMGR_VCOCALIB_MSCNT_OFFSET			9
202 #define CLKMGR_VCOCALIB_HSCNT_MASK			0xff
203 
204 #define CLKMGR_EMACCTL_EMAC0SEL_OFFSET			26
205 #define CLKMGR_EMACCTL_EMAC1SEL_OFFSET			27
206 #define CLKMGR_EMACCTL_EMAC2SEL_OFFSET			28
207 
208 #define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK		0x00000020
209 
210 #endif /* _CLOCK_MANAGER_S10_ */
211