Home
last modified time | relevance | path

Searched refs:COPY_TO_REGCLASS (Results 1 – 25 of 112) sorted by relevance

12345

/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
DSPU64InstrInfo.td57 CodeFrag<(CGTIv4i32 (GBv4i32 (CEQv4i32 (COPY_TO_REGCLASS R64C:$rA, VECREG),
58 (COPY_TO_REGCLASS R64C:$rB, VECREG))), 0xb)>;
70 def r64: CodeFrag<(i32 (COPY_TO_REGCLASS CEQr64compare.Fragment, R32C))>;
71 def v2i64: CodeFrag<(i32 (COPY_TO_REGCLASS CEQv2i64compare.Fragment, R32C))>;
74 def r64mask: CodeFrag<(i32 (COPY_TO_REGCLASS
76 def v2i64mask: CodeFrag<(i32 (COPY_TO_REGCLASS
94 CodeFrag<(CLGTv4i32 (COPY_TO_REGCLASS R64C:$rA, VECREG),
95 (COPY_TO_REGCLASS R64C:$rB, VECREG))>;
98 CodeFrag<(CEQv4i32 (COPY_TO_REGCLASS R64C:$rA, VECREG),
99 (COPY_TO_REGCLASS R64C:$rB, VECREG))>;
[all …]
DSPUISelDAGToDAG.cpp766 CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, OpVT, in Select()
850 Result = CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, VT, in Select()
923 VecOp0 = CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, VecVT, in SelectSHLi64()
968 return CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, in SelectSHLi64()
990 VecOp0 = CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, VecVT, in SelectSRLi64()
1037 return CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, in SelectSRLi64()
1059 CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, in SelectSRAi64()
1067 CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, in SelectSRAi64()
1115 return CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, in SelectSRAi64()
1143 return CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, OpVT, in SelectI64Constant()
[all …]
DSPUInstrInfo.td1428 (COPY_TO_REGCLASS R8C:$rA, VECREG)>;
1431 (COPY_TO_REGCLASS R16C:$rA, VECREG)>;
1434 (COPY_TO_REGCLASS R32C:$rA, VECREG)>;
1437 (COPY_TO_REGCLASS R64C:$rA, VECREG)>;
1440 (COPY_TO_REGCLASS R32FP:$rA, VECREG)>;
1443 (COPY_TO_REGCLASS R64FP:$rA, VECREG)>;
1446 (COPY_TO_REGCLASS (v16i8 VECREG:$rA), R8C)>;
1449 (COPY_TO_REGCLASS (v8i16 VECREG:$rA), R16C)>;
1452 (COPY_TO_REGCLASS (v4i32 VECREG:$rA), R32C)>;
1455 (COPY_TO_REGCLASS (v2i64 VECREG:$rA), R64C)>;
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86InstrVecCompiler.td125 (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>;
127 (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64)>;
131 (COPY_TO_REGCLASS FR32:$src, VR128)>;
134 (COPY_TO_REGCLASS FR64:$src, VR128)>;
335 (COPY_TO_REGCLASS VK1:$src, VK32)>;
338 (COPY_TO_REGCLASS VK8:$src, VK32)>;
341 (COPY_TO_REGCLASS VK16:$src, VK32)>;
345 (COPY_TO_REGCLASS VK1:$src, VK64)>;
348 (COPY_TO_REGCLASS VK8:$src, VK64)>;
351 (COPY_TO_REGCLASS VK16:$src, VK64)>;
[all …]
DX86InstrFMA.td340 VR128:$src1, (VT (COPY_TO_REGCLASS RC:$src2, VR128)),
341 (VT (COPY_TO_REGCLASS RC:$src3, VR128)))>;
347 VR128:$src1, (VT (COPY_TO_REGCLASS RC:$src2, VR128)),
348 (VT (COPY_TO_REGCLASS RC:$src3, VR128)))>;
355 VR128:$src1, (VT (COPY_TO_REGCLASS RC:$src2, VR128)),
362 VR128:$src1, (VT (COPY_TO_REGCLASS RC:$src2, VR128)),
369 VR128:$src1, (VT (COPY_TO_REGCLASS RC:$src2, VR128)),
608 (VT (COPY_TO_REGCLASS RC:$src1, VR128)),
609 (VT (COPY_TO_REGCLASS RC:$src2, VR128)),
610 (VT (COPY_TO_REGCLASS RC:$src3, VR128)))>;
[all …]
DX86InstrAVX512.td1125 (SrcInfo.VT (COPY_TO_REGCLASS SrcInfo.FRC:$src, SrcInfo.RC)))>;
1131 (SrcInfo.VT (COPY_TO_REGCLASS SrcInfo.FRC:$src, SrcInfo.RC)))>;
1136 DestInfo.KRCWM:$mask, (SrcInfo.VT (COPY_TO_REGCLASS SrcInfo.FRC:$src, SrcInfo.RC)))>;
2866 (COPY_TO_REGCLASS (i32 (INSERT_SUBREG (IMPLICIT_DEF), GR16:$src, sub_16bit)), VK16)>;
2868 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS VK16:$src, GR32)), sub_16bit)>;
2871 (COPY_TO_REGCLASS (i32 (INSERT_SUBREG (IMPLICIT_DEF), GR8:$src, sub_8bit)), VK8)>;
2873 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS VK8:$src, GR32)), sub_8bit)>;
2878 (COPY_TO_REGCLASS VK16:$src, GR32)>;
2883 (COPY_TO_REGCLASS VK8:$src, GR32)>;
2886 (COPY_TO_REGCLASS GR32:$src, VK32)>;
[all …]
DX86InstrSSE.td256 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
258 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
260 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
265 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
267 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
269 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
271 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
289 (VMOVSSmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32))>;
334 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
336 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCInstrVSX.td998 (COPY_TO_REGCLASS $A, VSRC)>;
1000 (COPY_TO_REGCLASS $A, VSRC)>;
1002 (COPY_TO_REGCLASS $A, VSRC)>;
1004 (COPY_TO_REGCLASS $A, VSRC)>;
1007 (COPY_TO_REGCLASS $A, VRRC)>;
1009 (COPY_TO_REGCLASS $A, VRRC)>;
1011 (COPY_TO_REGCLASS $A, VRRC)>;
1013 (COPY_TO_REGCLASS $A, VRRC)>;
1016 (COPY_TO_REGCLASS $A, VSRC)>;
1018 (COPY_TO_REGCLASS $A, VSRC)>;
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/GlobalISel/
Darm-select-copy_to_regclass-of-fptosi.mir8 # G_FPTOSI selects to a (COPY_TO_REGCLASS (VTOSIZS SPR:$a), GPR), where
9 # COPY_TO_REGCLASS doesn't constrain its source register class. It exposes the
11 # register class as COPY_TO_REGCLASS' source (which is fine) nor as VTOSIZS'
/external/llvm/lib/Target/X86/
DX86InstrAVX512.td607 (COPY_TO_REGCLASS To.MRC:$mask, To.KRCWM),
616 (COPY_TO_REGCLASS To.MRC:$mask, To.KRCWM),
1337 (v16f32 (VBLENDMPSZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1344 (v16i32 (VPBLENDMDZrrk (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1548 (COPY_TO_REGCLASS (VPCMPGTDZrr
1553 (COPY_TO_REGCLASS (VPCMPEQDZrr
1807 (COPY_TO_REGCLASS (VCMPPSZrri
1812 (COPY_TO_REGCLASS (VPCMPDZrri
1817 (COPY_TO_REGCLASS (VPCMPUDZrri
2032 (KMOVBmk addr:$dst, (COPY_TO_REGCLASS VK4:$src, VK8))>;
[all …]
DX86InstrSSE.td334 (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>;
336 (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64)>;
374 (COPY_TO_REGCLASS FR32:$src, VR128)>;
376 (COPY_TO_REGCLASS FR32:$src, VR128)>;
379 (COPY_TO_REGCLASS FR64:$src, VR128)>;
381 (COPY_TO_REGCLASS FR64:$src, VR128)>;
588 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
590 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
592 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
597 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
[all …]
DX86InstrCompiler.td1447 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
1454 (i16 (COPY_TO_REGCLASS GR16:$src1, GR16_ABCD)), sub_8bit)),
1489 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1496 (i32 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), sub_8bit))),
1528 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1532 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1550 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1554 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1558 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1564 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
[all …]
/external/llvm/lib/Target/PowerPC/
DPPCInstrVSX.td883 (COPY_TO_REGCLASS $A, VSRC)>;
885 (COPY_TO_REGCLASS $A, VSRC)>;
887 (COPY_TO_REGCLASS $A, VSRC)>;
889 (COPY_TO_REGCLASS $A, VSRC)>;
892 (COPY_TO_REGCLASS $A, VRRC)>;
894 (COPY_TO_REGCLASS $A, VRRC)>;
896 (COPY_TO_REGCLASS $A, VRRC)>;
898 (COPY_TO_REGCLASS $A, VRRC)>;
901 (COPY_TO_REGCLASS $A, VSRC)>;
903 (COPY_TO_REGCLASS $A, VSRC)>;
[all …]
/external/swiftshader/third_party/LLVM/include/llvm/Target/
DTargetOpcodes.h66 COPY_TO_REGCLASS = 10, enumerator
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrCompiler.td1224 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
1231 (i16 (COPY_TO_REGCLASS GR16:$src1, GR16_ABCD)), sub_8bit)),
1259 (MOVSX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src,
1266 (i32 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), sub_8bit))),
1298 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1302 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1320 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1324 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1330 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1335 (MOVZX32rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src,
[all …]
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/
DMipsGenDAGISel.inc550 /* 900*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
555 …// Dst: (SW (COPY_TO_REGCLASS:{ *:[i32] } DSPR:{ *:[v2i16] }:$val, GPR32:{ *:[i32] }), addr:{ *:[i…
565 /* 933*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
570 …// Dst: (SW (COPY_TO_REGCLASS:{ *:[i32] } DSPR:{ *:[v4i8] }:$val, GPR32:{ *:[i32] }), addr:{ *:[iP…
1334 /* 2380*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0|OPFL_Chain,
1337 … // Dst: (COPY_TO_REGCLASS:{ *:[v2i16] } (LW:{ *:[i32] } addr:{ *:[iPTR] }:$a), DSPR:{ *:[i32] })
1345 /* 2407*/ OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0|OPFL_Chain,
1348 … // Dst: (COPY_TO_REGCLASS:{ *:[v4i8] } (LW:{ *:[i32] } addr:{ *:[iPTR] }:$a), DSPR:{ *:[i32] })
22344 /* 41320*/ OPC_EmitNode1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
22350 …// Dst: (SRA:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } (SPLAT_B:{ *:[v…
[all …]
DMipsGenGlobalISel.inc2789 …// (bitconvert:{ *:[i32] } DSPR:{ *:[v2i16] }:$src) => (COPY_TO_REGCLASS:{ *:[i32] } DSPR:{ *:[v…
2800 …// (bitconvert:{ *:[i32] } DSPR:{ *:[v4i8] }:$src) => (COPY_TO_REGCLASS:{ *:[i32] } DSPR:{ *:[v4…
2811 …// (bitconvert:{ *:[f32] } DSPR:{ *:[v2i16] }:$src) => (COPY_TO_REGCLASS:{ *:[f32] } DSPR:{ *:[v…
2822 …// (bitconvert:{ *:[f32] } DSPR:{ *:[v4i8] }:$src) => (COPY_TO_REGCLASS:{ *:[f32] } DSPR:{ *:[v4…
2862 …// (bitconvert:{ *:[v2i16] } GPR32:{ *:[i32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i16] } GPR32:{ …
2871 …// (bitconvert:{ *:[v2i16] } FGR32:{ *:[f32] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i16] } FGR32:{ …
2885 …// (bitconvert:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v2f64:…
2895 …// (bitconvert:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$src) => (COPY_TO_REGCLASS:{ *:[v2f64] } v2i64:…
2905 …// (bitconvert:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v16i8:…
2915 …// (bitconvert:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$src) => (COPY_TO_REGCLASS:{ *:[v2i64] } v8i16:…
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/
Dfast-isel-fpconv.ll4 ; of COPY_TO_REGCLASS in the FastISel pass. Verify that this is fixed.
/external/llvm/test/CodeGen/PowerPC/
Dfast-isel-fpconv.ll4 ; of COPY_TO_REGCLASS in the FastISel pass. Verify that this is fixed.
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMInstrVFP.td686 (VCVTBHS (COPY_TO_REGCLASS HPR:$Sm, SPR))>;
688 (VCVTBHS (COPY_TO_REGCLASS GPR:$a, SPR))>;
697 (COPY_TO_REGCLASS (VCVTBSH SPR:$Sm), HPR)>;
699 (i32 (COPY_TO_REGCLASS (VCVTBSH SPR:$a), GPR))>;
728 (VCVTBHD (COPY_TO_REGCLASS HPR:$Sm, SPR))>;
730 (VCVTBHD (COPY_TO_REGCLASS GPR:$a, SPR))>;
749 (COPY_TO_REGCLASS (VCVTBDH DPR:$Dm), HPR)>;
751 (i32 (COPY_TO_REGCLASS (VCVTBDH DPR:$a), GPR))>;
849 (COPY_TO_REGCLASS
854 (COPY_TO_REGCLASS
[all …]
/external/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td3555 (COPY_TO_REGCLASS SrcVT:$src, DstRC), preds>;
3613 (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 27),
3621 (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 177),
3636 (COPY_TO_REGCLASS
3638 (COPY_TO_REGCLASS
3639 (SHF_B (COPY_TO_REGCLASS SrcVT:$src, MSA128B), 27),
3756 (SRA (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_B v16i8:$ws,
3761 (SRA (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_H v8i16:$ws,
3766 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_W v4i32:$ws,
3771 (COPY_TO_REGCLASS (i64 (EXTRACT_SUBREG (SPLAT_D v2i64:$ws,
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td3576 (COPY_TO_REGCLASS SrcVT:$src, DstRC), preds>;
3634 (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 27),
3642 (COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 177),
3657 (COPY_TO_REGCLASS
3659 (COPY_TO_REGCLASS
3660 (SHF_B (COPY_TO_REGCLASS SrcVT:$src, MSA128B), 27),
3902 (SRA (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_B v16i8:$ws,
3907 (SRA (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_H v8i16:$ws,
3912 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_W v4i32:$ws,
3917 (COPY_TO_REGCLASS (i64 (EXTRACT_SUBREG (SPLAT_D v2i64:$ws,
[all …]
/external/llvm/lib/Target/ARM/
DARMInstrVFP.td742 (i32 (COPY_TO_REGCLASS (VCVTBSH SPR:$a), GPR))>;
745 (i32 (COPY_TO_REGCLASS (VCVTBDH DPR:$a), GPR))>;
748 (VCVTBHS (COPY_TO_REGCLASS GPR:$a, SPR))>;
751 (VCVTBHD (COPY_TO_REGCLASS GPR:$a, SPR))>;
821 (COPY_TO_REGCLASS
825 (COPY_TO_REGCLASS
831 (COPY_TO_REGCLASS
835 (COPY_TO_REGCLASS
1263 (VSITOD (COPY_TO_REGCLASS GPR:$a, SPR))>;
1281 (VSITOS (COPY_TO_REGCLASS GPR:$a, SPR))>;
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/Blackfin/
DBlackfinISelDAGToDAG.cpp169 DAG.getMachineNode(TargetOpcode::COPY_TO_REGCLASS, in FixRegisterClasses()
/external/llvm/include/llvm/Target/
DTargetOpcodes.def64 /// COPY_TO_REGCLASS - This instruction is a placeholder for a plain
70 HANDLE_TARGET_OPCODE(COPY_TO_REGCLASS, 10)

12345