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1 //===-- SPUISelDAGToDAG.cpp - CellSPU pattern matching inst selector ------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines a pattern matching instruction selector for the Cell SPU,
11 // converting from a legalized dag to a SPU-target dag.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "SPU.h"
16 #include "SPUTargetMachine.h"
17 #include "SPUHazardRecognizers.h"
18 #include "SPUFrameLowering.h"
19 #include "SPUTargetMachine.h"
20 #include "llvm/CodeGen/MachineConstantPool.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
24 #include "llvm/CodeGen/SelectionDAGISel.h"
25 #include "llvm/CodeGen/PseudoSourceValue.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/ADT/Statistic.h"
28 #include "llvm/Constants.h"
29 #include "llvm/GlobalValue.h"
30 #include "llvm/Intrinsics.h"
31 #include "llvm/LLVMContext.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/MathExtras.h"
35 #include "llvm/Support/Compiler.h"
36 #include "llvm/Support/raw_ostream.h"
37 
38 using namespace llvm;
39 
40 namespace {
41   //! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
42   bool
isI32IntS10Immediate(ConstantSDNode * CN)43   isI32IntS10Immediate(ConstantSDNode *CN)
44   {
45     return isInt<10>(CN->getSExtValue());
46   }
47 
48   //! ConstantSDNode predicate for i32 unsigned 10-bit immediate values
49   bool
isI32IntU10Immediate(ConstantSDNode * CN)50   isI32IntU10Immediate(ConstantSDNode *CN)
51   {
52     return isUInt<10>(CN->getSExtValue());
53   }
54 
55   //! ConstantSDNode predicate for i16 sign-extended, 10-bit immediate values
56   bool
isI16IntS10Immediate(ConstantSDNode * CN)57   isI16IntS10Immediate(ConstantSDNode *CN)
58   {
59     return isInt<10>(CN->getSExtValue());
60   }
61 
62   //! ConstantSDNode predicate for i16 unsigned 10-bit immediate values
63   bool
isI16IntU10Immediate(ConstantSDNode * CN)64   isI16IntU10Immediate(ConstantSDNode *CN)
65   {
66     return isUInt<10>((short) CN->getZExtValue());
67   }
68 
69   //! ConstantSDNode predicate for signed 16-bit values
70   /*!
71     \arg CN The constant SelectionDAG node holding the value
72     \arg Imm The returned 16-bit value, if returning true
73 
74     This predicate tests the value in \a CN to see whether it can be
75     represented as a 16-bit, sign-extended quantity. Returns true if
76     this is the case.
77    */
78   bool
isIntS16Immediate(ConstantSDNode * CN,short & Imm)79   isIntS16Immediate(ConstantSDNode *CN, short &Imm)
80   {
81     EVT vt = CN->getValueType(0);
82     Imm = (short) CN->getZExtValue();
83     if (vt.getSimpleVT() >= MVT::i1 && vt.getSimpleVT() <= MVT::i16) {
84       return true;
85     } else if (vt == MVT::i32) {
86       int32_t i_val = (int32_t) CN->getZExtValue();
87       short s_val = (short) i_val;
88       return i_val == s_val;
89     } else {
90       int64_t i_val = (int64_t) CN->getZExtValue();
91       short s_val = (short) i_val;
92       return i_val == s_val;
93     }
94 
95     return false;
96   }
97 
98   //! ConstantFPSDNode predicate for representing floats as 16-bit sign ext.
99   static bool
isFPS16Immediate(ConstantFPSDNode * FPN,short & Imm)100   isFPS16Immediate(ConstantFPSDNode *FPN, short &Imm)
101   {
102     EVT vt = FPN->getValueType(0);
103     if (vt == MVT::f32) {
104       int val = FloatToBits(FPN->getValueAPF().convertToFloat());
105       int sval = (int) ((val << 16) >> 16);
106       Imm = (short) val;
107       return val == sval;
108     }
109 
110     return false;
111   }
112 
113   //! Generate the carry-generate shuffle mask.
getCarryGenerateShufMask(SelectionDAG & DAG,DebugLoc dl)114   SDValue getCarryGenerateShufMask(SelectionDAG &DAG, DebugLoc dl) {
115     SmallVector<SDValue, 16 > ShufBytes;
116 
117     // Create the shuffle mask for "rotating" the borrow up one register slot
118     // once the borrow is generated.
119     ShufBytes.push_back(DAG.getConstant(0x04050607, MVT::i32));
120     ShufBytes.push_back(DAG.getConstant(0x80808080, MVT::i32));
121     ShufBytes.push_back(DAG.getConstant(0x0c0d0e0f, MVT::i32));
122     ShufBytes.push_back(DAG.getConstant(0x80808080, MVT::i32));
123 
124     return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
125                        &ShufBytes[0], ShufBytes.size());
126   }
127 
128   //! Generate the borrow-generate shuffle mask
getBorrowGenerateShufMask(SelectionDAG & DAG,DebugLoc dl)129   SDValue getBorrowGenerateShufMask(SelectionDAG &DAG, DebugLoc dl) {
130     SmallVector<SDValue, 16 > ShufBytes;
131 
132     // Create the shuffle mask for "rotating" the borrow up one register slot
133     // once the borrow is generated.
134     ShufBytes.push_back(DAG.getConstant(0x04050607, MVT::i32));
135     ShufBytes.push_back(DAG.getConstant(0xc0c0c0c0, MVT::i32));
136     ShufBytes.push_back(DAG.getConstant(0x0c0d0e0f, MVT::i32));
137     ShufBytes.push_back(DAG.getConstant(0xc0c0c0c0, MVT::i32));
138 
139     return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
140                        &ShufBytes[0], ShufBytes.size());
141   }
142 
143   //===------------------------------------------------------------------===//
144   /// SPUDAGToDAGISel - Cell SPU-specific code to select SPU machine
145   /// instructions for SelectionDAG operations.
146   ///
147   class SPUDAGToDAGISel :
148     public SelectionDAGISel
149   {
150     const SPUTargetMachine &TM;
151     const SPUTargetLowering &SPUtli;
152     unsigned GlobalBaseReg;
153 
154   public:
SPUDAGToDAGISel(SPUTargetMachine & tm)155     explicit SPUDAGToDAGISel(SPUTargetMachine &tm) :
156       SelectionDAGISel(tm),
157       TM(tm),
158       SPUtli(*tm.getTargetLowering())
159     { }
160 
runOnMachineFunction(MachineFunction & MF)161     virtual bool runOnMachineFunction(MachineFunction &MF) {
162       // Make sure we re-emit a set of the global base reg if necessary
163       GlobalBaseReg = 0;
164       SelectionDAGISel::runOnMachineFunction(MF);
165       return true;
166     }
167 
168     /// getI32Imm - Return a target constant with the specified value, of type
169     /// i32.
getI32Imm(uint32_t Imm)170     inline SDValue getI32Imm(uint32_t Imm) {
171       return CurDAG->getTargetConstant(Imm, MVT::i32);
172     }
173 
174     /// getSmallIPtrImm - Return a target constant of pointer type.
getSmallIPtrImm(unsigned Imm)175     inline SDValue getSmallIPtrImm(unsigned Imm) {
176       return CurDAG->getTargetConstant(Imm, SPUtli.getPointerTy());
177     }
178 
emitBuildVector(SDNode * bvNode)179     SDNode *emitBuildVector(SDNode *bvNode) {
180       EVT vecVT = bvNode->getValueType(0);
181       DebugLoc dl = bvNode->getDebugLoc();
182 
183       // Check to see if this vector can be represented as a CellSPU immediate
184       // constant by invoking all of the instruction selection predicates:
185       if (((vecVT == MVT::v8i16) &&
186            (SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i16).getNode() != 0)) ||
187           ((vecVT == MVT::v4i32) &&
188            ((SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) ||
189             (SPU::get_ILHUvec_imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) ||
190             (SPU::get_vec_u18imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) ||
191             (SPU::get_v4i32_imm(bvNode, *CurDAG).getNode() != 0))) ||
192           ((vecVT == MVT::v2i64) &&
193            ((SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i64).getNode() != 0) ||
194             (SPU::get_ILHUvec_imm(bvNode, *CurDAG, MVT::i64).getNode() != 0) ||
195             (SPU::get_vec_u18imm(bvNode, *CurDAG, MVT::i64).getNode() != 0)))) {
196         HandleSDNode Dummy(SDValue(bvNode, 0));
197         if (SDNode *N = Select(bvNode))
198           return N;
199         return Dummy.getValue().getNode();
200       }
201 
202       // No, need to emit a constant pool spill:
203       std::vector<Constant*> CV;
204 
205       for (size_t i = 0; i < bvNode->getNumOperands(); ++i) {
206         ConstantSDNode *V = cast<ConstantSDNode > (bvNode->getOperand(i));
207         CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
208       }
209 
210       const Constant *CP = ConstantVector::get(CV);
211       SDValue CPIdx = CurDAG->getConstantPool(CP, SPUtli.getPointerTy());
212       unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
213       SDValue CGPoolOffset =
214               SPU::LowerConstantPool(CPIdx, *CurDAG, TM);
215 
216       HandleSDNode Dummy(CurDAG->getLoad(vecVT, dl,
217                                          CurDAG->getEntryNode(), CGPoolOffset,
218                                          MachinePointerInfo::getConstantPool(),
219                                          false, false, Alignment));
220       CurDAG->ReplaceAllUsesWith(SDValue(bvNode, 0), Dummy.getValue());
221       if (SDNode *N = SelectCode(Dummy.getValue().getNode()))
222         return N;
223       return Dummy.getValue().getNode();
224     }
225 
226     /// Select - Convert the specified operand from a target-independent to a
227     /// target-specific node if it hasn't already been changed.
228     SDNode *Select(SDNode *N);
229 
230     //! Emit the instruction sequence for i64 shl
231     SDNode *SelectSHLi64(SDNode *N, EVT OpVT);
232 
233     //! Emit the instruction sequence for i64 srl
234     SDNode *SelectSRLi64(SDNode *N, EVT OpVT);
235 
236     //! Emit the instruction sequence for i64 sra
237     SDNode *SelectSRAi64(SDNode *N, EVT OpVT);
238 
239     //! Emit the necessary sequence for loading i64 constants:
240     SDNode *SelectI64Constant(SDNode *N, EVT OpVT, DebugLoc dl);
241 
242     //! Alternate instruction emit sequence for loading i64 constants
243     SDNode *SelectI64Constant(uint64_t i64const, EVT OpVT, DebugLoc dl);
244 
245     //! Returns true if the address N is an A-form (local store) address
246     bool SelectAFormAddr(SDNode *Op, SDValue N, SDValue &Base,
247                          SDValue &Index);
248 
249     //! D-form address predicate
250     bool SelectDFormAddr(SDNode *Op, SDValue N, SDValue &Base,
251                          SDValue &Index);
252 
253     /// Alternate D-form address using i7 offset predicate
254     bool SelectDForm2Addr(SDNode *Op, SDValue N, SDValue &Disp,
255                           SDValue &Base);
256 
257     /// D-form address selection workhorse
258     bool DFormAddressPredicate(SDNode *Op, SDValue N, SDValue &Disp,
259                                SDValue &Base, int minOffset, int maxOffset);
260 
261     //! Address predicate if N can be expressed as an indexed [r+r] operation.
262     bool SelectXFormAddr(SDNode *Op, SDValue N, SDValue &Base,
263                          SDValue &Index);
264 
265     /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
266     /// inline asm expressions.
SelectInlineAsmMemoryOperand(const SDValue & Op,char ConstraintCode,std::vector<SDValue> & OutOps)267     virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
268                                               char ConstraintCode,
269                                               std::vector<SDValue> &OutOps) {
270       SDValue Op0, Op1;
271       switch (ConstraintCode) {
272       default: return true;
273       case 'm':   // memory
274         if (!SelectDFormAddr(Op.getNode(), Op, Op0, Op1)
275             && !SelectAFormAddr(Op.getNode(), Op, Op0, Op1))
276           SelectXFormAddr(Op.getNode(), Op, Op0, Op1);
277         break;
278       case 'o':   // offsetable
279         if (!SelectDFormAddr(Op.getNode(), Op, Op0, Op1)
280             && !SelectAFormAddr(Op.getNode(), Op, Op0, Op1)) {
281           Op0 = Op;
282           Op1 = getSmallIPtrImm(0);
283         }
284         break;
285       case 'v':   // not offsetable
286 #if 1
287         llvm_unreachable("InlineAsmMemoryOperand 'v' constraint not handled.");
288 #else
289         SelectAddrIdxOnly(Op, Op, Op0, Op1);
290 #endif
291         break;
292       }
293 
294       OutOps.push_back(Op0);
295       OutOps.push_back(Op1);
296       return false;
297     }
298 
getPassName() const299     virtual const char *getPassName() const {
300       return "Cell SPU DAG->DAG Pattern Instruction Selection";
301     }
302 
303   private:
304     SDValue getRC( MVT );
305 
306     // Include the pieces autogenerated from the target description.
307 #include "SPUGenDAGISel.inc"
308   };
309 }
310 
311 /*!
312  \arg Op The ISD instruction operand
313  \arg N The address to be tested
314  \arg Base The base address
315  \arg Index The base address index
316  */
317 bool
SelectAFormAddr(SDNode * Op,SDValue N,SDValue & Base,SDValue & Index)318 SPUDAGToDAGISel::SelectAFormAddr(SDNode *Op, SDValue N, SDValue &Base,
319                     SDValue &Index) {
320   // These match the addr256k operand type:
321   EVT OffsVT = MVT::i16;
322   SDValue Zero = CurDAG->getTargetConstant(0, OffsVT);
323   int64_t val;
324 
325   switch (N.getOpcode()) {
326   case ISD::Constant:
327     val = dyn_cast<ConstantSDNode>(N.getNode())->getSExtValue();
328     Base = CurDAG->getTargetConstant( val , MVT::i32);
329     Index = Zero;
330     return true; break;
331   case ISD::ConstantPool:
332   case ISD::GlobalAddress:
333     report_fatal_error("SPU SelectAFormAddr: Pool/Global not lowered.");
334     /*NOTREACHED*/
335 
336   case ISD::TargetConstant:
337   case ISD::TargetGlobalAddress:
338   case ISD::TargetJumpTable:
339     report_fatal_error("SPUSelectAFormAddr: Target Constant/Pool/Global "
340                       "not wrapped as A-form address.");
341     /*NOTREACHED*/
342 
343   case SPUISD::AFormAddr:
344     // Just load from memory if there's only a single use of the location,
345     // otherwise, this will get handled below with D-form offset addresses
346     if (N.hasOneUse()) {
347       SDValue Op0 = N.getOperand(0);
348       switch (Op0.getOpcode()) {
349       case ISD::TargetConstantPool:
350       case ISD::TargetJumpTable:
351         Base = Op0;
352         Index = Zero;
353         return true;
354 
355       case ISD::TargetGlobalAddress: {
356         GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op0);
357         const GlobalValue *GV = GSDN->getGlobal();
358         if (GV->getAlignment() == 16) {
359           Base = Op0;
360           Index = Zero;
361           return true;
362         }
363         break;
364       }
365       }
366     }
367     break;
368   }
369   return false;
370 }
371 
372 bool
SelectDForm2Addr(SDNode * Op,SDValue N,SDValue & Disp,SDValue & Base)373 SPUDAGToDAGISel::SelectDForm2Addr(SDNode *Op, SDValue N, SDValue &Disp,
374                                   SDValue &Base) {
375   const int minDForm2Offset = -(1 << 7);
376   const int maxDForm2Offset = (1 << 7) - 1;
377   return DFormAddressPredicate(Op, N, Disp, Base, minDForm2Offset,
378                                maxDForm2Offset);
379 }
380 
381 /*!
382   \arg Op The ISD instruction (ignored)
383   \arg N The address to be tested
384   \arg Base Base address register/pointer
385   \arg Index Base address index
386 
387   Examine the input address by a base register plus a signed 10-bit
388   displacement, [r+I10] (D-form address).
389 
390   \return true if \a N is a D-form address with \a Base and \a Index set
391   to non-empty SDValue instances.
392 */
393 bool
SelectDFormAddr(SDNode * Op,SDValue N,SDValue & Base,SDValue & Index)394 SPUDAGToDAGISel::SelectDFormAddr(SDNode *Op, SDValue N, SDValue &Base,
395                                  SDValue &Index) {
396   return DFormAddressPredicate(Op, N, Base, Index,
397                                SPUFrameLowering::minFrameOffset(),
398                                SPUFrameLowering::maxFrameOffset());
399 }
400 
401 bool
DFormAddressPredicate(SDNode * Op,SDValue N,SDValue & Base,SDValue & Index,int minOffset,int maxOffset)402 SPUDAGToDAGISel::DFormAddressPredicate(SDNode *Op, SDValue N, SDValue &Base,
403                                       SDValue &Index, int minOffset,
404                                       int maxOffset) {
405   unsigned Opc = N.getOpcode();
406   EVT PtrTy = SPUtli.getPointerTy();
407 
408   if (Opc == ISD::FrameIndex) {
409     // Stack frame index must be less than 512 (divided by 16):
410     FrameIndexSDNode *FIN = cast<FrameIndexSDNode>(N);
411     int FI = int(FIN->getIndex());
412     DEBUG(errs() << "SelectDFormAddr: ISD::FrameIndex = "
413                << FI << "\n");
414     if (SPUFrameLowering::FItoStackOffset(FI) < maxOffset) {
415       Base = CurDAG->getTargetConstant(0, PtrTy);
416       Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
417       return true;
418     }
419   } else if (Opc == ISD::ADD) {
420     // Generated by getelementptr
421     const SDValue Op0 = N.getOperand(0);
422     const SDValue Op1 = N.getOperand(1);
423 
424     if ((Op0.getOpcode() == SPUISD::Hi && Op1.getOpcode() == SPUISD::Lo)
425         || (Op1.getOpcode() == SPUISD::Hi && Op0.getOpcode() == SPUISD::Lo)) {
426       Base = CurDAG->getTargetConstant(0, PtrTy);
427       Index = N;
428       return true;
429     } else if (Op1.getOpcode() == ISD::Constant
430                || Op1.getOpcode() == ISD::TargetConstant) {
431       ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
432       int32_t offset = int32_t(CN->getSExtValue());
433 
434       if (Op0.getOpcode() == ISD::FrameIndex) {
435         FrameIndexSDNode *FIN = cast<FrameIndexSDNode>(Op0);
436         int FI = int(FIN->getIndex());
437         DEBUG(errs() << "SelectDFormAddr: ISD::ADD offset = " << offset
438                    << " frame index = " << FI << "\n");
439 
440         if (SPUFrameLowering::FItoStackOffset(FI) < maxOffset) {
441           Base = CurDAG->getTargetConstant(offset, PtrTy);
442           Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
443           return true;
444         }
445       } else if (offset > minOffset && offset < maxOffset) {
446         Base = CurDAG->getTargetConstant(offset, PtrTy);
447         Index = Op0;
448         return true;
449       }
450     } else if (Op0.getOpcode() == ISD::Constant
451                || Op0.getOpcode() == ISD::TargetConstant) {
452       ConstantSDNode *CN = cast<ConstantSDNode>(Op0);
453       int32_t offset = int32_t(CN->getSExtValue());
454 
455       if (Op1.getOpcode() == ISD::FrameIndex) {
456         FrameIndexSDNode *FIN = cast<FrameIndexSDNode>(Op1);
457         int FI = int(FIN->getIndex());
458         DEBUG(errs() << "SelectDFormAddr: ISD::ADD offset = " << offset
459                    << " frame index = " << FI << "\n");
460 
461         if (SPUFrameLowering::FItoStackOffset(FI) < maxOffset) {
462           Base = CurDAG->getTargetConstant(offset, PtrTy);
463           Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
464           return true;
465         }
466       } else if (offset > minOffset && offset < maxOffset) {
467         Base = CurDAG->getTargetConstant(offset, PtrTy);
468         Index = Op1;
469         return true;
470       }
471     }
472   } else if (Opc == SPUISD::IndirectAddr) {
473     // Indirect with constant offset -> D-Form address
474     const SDValue Op0 = N.getOperand(0);
475     const SDValue Op1 = N.getOperand(1);
476 
477     if (Op0.getOpcode() == SPUISD::Hi
478         && Op1.getOpcode() == SPUISD::Lo) {
479       // (SPUindirect (SPUhi <arg>, 0), (SPUlo <arg>, 0))
480       Base = CurDAG->getTargetConstant(0, PtrTy);
481       Index = N;
482       return true;
483     } else if (isa<ConstantSDNode>(Op0) || isa<ConstantSDNode>(Op1)) {
484       int32_t offset = 0;
485       SDValue idxOp;
486 
487       if (isa<ConstantSDNode>(Op1)) {
488         ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
489         offset = int32_t(CN->getSExtValue());
490         idxOp = Op0;
491       } else if (isa<ConstantSDNode>(Op0)) {
492         ConstantSDNode *CN = cast<ConstantSDNode>(Op0);
493         offset = int32_t(CN->getSExtValue());
494         idxOp = Op1;
495       }
496 
497       if (offset >= minOffset && offset <= maxOffset) {
498         Base = CurDAG->getTargetConstant(offset, PtrTy);
499         Index = idxOp;
500         return true;
501       }
502     }
503   } else if (Opc == SPUISD::AFormAddr) {
504     Base = CurDAG->getTargetConstant(0, N.getValueType());
505     Index = N;
506     return true;
507   } else if (Opc == SPUISD::LDRESULT) {
508     Base = CurDAG->getTargetConstant(0, N.getValueType());
509     Index = N;
510     return true;
511   } else if (Opc == ISD::Register
512            ||Opc == ISD::CopyFromReg
513            ||Opc == ISD::UNDEF
514            ||Opc == ISD::Constant) {
515     unsigned OpOpc = Op->getOpcode();
516 
517     if (OpOpc == ISD::STORE || OpOpc == ISD::LOAD) {
518       // Direct load/store without getelementptr
519       SDValue Offs;
520 
521       Offs = ((OpOpc == ISD::STORE) ? Op->getOperand(3) : Op->getOperand(2));
522 
523       if (Offs.getOpcode() == ISD::Constant || Offs.getOpcode() == ISD::UNDEF) {
524         if (Offs.getOpcode() == ISD::UNDEF)
525           Offs = CurDAG->getTargetConstant(0, Offs.getValueType());
526 
527         Base = Offs;
528         Index = N;
529         return true;
530       }
531     } else {
532       /* If otherwise unadorned, default to D-form address with 0 offset: */
533       if (Opc == ISD::CopyFromReg) {
534         Index = N.getOperand(1);
535       } else {
536         Index = N;
537       }
538 
539       Base = CurDAG->getTargetConstant(0, Index.getValueType());
540       return true;
541     }
542   }
543 
544   return false;
545 }
546 
547 /*!
548   \arg Op The ISD instruction operand
549   \arg N The address operand
550   \arg Base The base pointer operand
551   \arg Index The offset/index operand
552 
553   If the address \a N can be expressed as an A-form or D-form address, returns
554   false.  Otherwise, creates two operands, Base and Index that will become the
555   (r)(r) X-form address.
556 */
557 bool
SelectXFormAddr(SDNode * Op,SDValue N,SDValue & Base,SDValue & Index)558 SPUDAGToDAGISel::SelectXFormAddr(SDNode *Op, SDValue N, SDValue &Base,
559                                  SDValue &Index) {
560   if (!SelectAFormAddr(Op, N, Base, Index)
561       && !SelectDFormAddr(Op, N, Base, Index)) {
562     // If the address is neither A-form or D-form, punt and use an X-form
563     // address:
564     Base = N.getOperand(1);
565     Index = N.getOperand(0);
566     return true;
567   }
568 
569   return false;
570 }
571 
572 /*!
573  Utility function to use with COPY_TO_REGCLASS instructions. Returns a SDValue
574  to be used as the last parameter of a
575 CurDAG->getMachineNode(COPY_TO_REGCLASS,..., ) function call
576  \arg VT the value type for which we want a register class
577 */
getRC(MVT VT)578 SDValue SPUDAGToDAGISel::getRC( MVT VT ) {
579   switch( VT.SimpleTy ) {
580   case MVT::i8:
581     return CurDAG->getTargetConstant(SPU::R8CRegClass.getID(), MVT::i32);
582     break;
583   case MVT::i16:
584     return CurDAG->getTargetConstant(SPU::R16CRegClass.getID(), MVT::i32);
585     break;
586   case MVT::i32:
587     return CurDAG->getTargetConstant(SPU::R32CRegClass.getID(), MVT::i32);
588     break;
589   case MVT::f32:
590     return CurDAG->getTargetConstant(SPU::R32FPRegClass.getID(), MVT::i32);
591     break;
592   case MVT::i64:
593     return CurDAG->getTargetConstant(SPU::R64CRegClass.getID(), MVT::i32);
594     break;
595   case MVT::i128:
596     return CurDAG->getTargetConstant(SPU::GPRCRegClass.getID(), MVT::i32);
597     break;
598   case MVT::v16i8:
599   case MVT::v8i16:
600   case MVT::v4i32:
601   case MVT::v4f32:
602   case MVT::v2i64:
603   case MVT::v2f64:
604     return CurDAG->getTargetConstant(SPU::VECREGRegClass.getID(), MVT::i32);
605     break;
606   default:
607     assert( false && "add a new case here" );
608   }
609   return SDValue();
610 }
611 
612 //! Convert the operand from a target-independent to a target-specific node
613 /*!
614  */
615 SDNode *
Select(SDNode * N)616 SPUDAGToDAGISel::Select(SDNode *N) {
617   unsigned Opc = N->getOpcode();
618   int n_ops = -1;
619   unsigned NewOpc = 0;
620   EVT OpVT = N->getValueType(0);
621   SDValue Ops[8];
622   DebugLoc dl = N->getDebugLoc();
623 
624   if (N->isMachineOpcode())
625     return NULL;   // Already selected.
626 
627   if (Opc == ISD::FrameIndex) {
628     int FI = cast<FrameIndexSDNode>(N)->getIndex();
629     SDValue TFI = CurDAG->getTargetFrameIndex(FI, N->getValueType(0));
630     SDValue Imm0 = CurDAG->getTargetConstant(0, N->getValueType(0));
631 
632     if (FI < 128) {
633       NewOpc = SPU::AIr32;
634       Ops[0] = TFI;
635       Ops[1] = Imm0;
636       n_ops = 2;
637     } else {
638       NewOpc = SPU::Ar32;
639       Ops[0] = CurDAG->getRegister(SPU::R1, N->getValueType(0));
640       Ops[1] = SDValue(CurDAG->getMachineNode(SPU::ILAr32, dl,
641                                               N->getValueType(0), TFI),
642                        0);
643       n_ops = 2;
644     }
645   } else if (Opc == ISD::Constant && OpVT == MVT::i64) {
646     // Catch the i64 constants that end up here. Note: The backend doesn't
647     // attempt to legalize the constant (it's useless because DAGCombiner
648     // will insert 64-bit constants and we can't stop it).
649     return SelectI64Constant(N, OpVT, N->getDebugLoc());
650   } else if ((Opc == ISD::ZERO_EXTEND || Opc == ISD::ANY_EXTEND)
651              && OpVT == MVT::i64) {
652     SDValue Op0 = N->getOperand(0);
653     EVT Op0VT = Op0.getValueType();
654     EVT Op0VecVT = EVT::getVectorVT(*CurDAG->getContext(),
655                                     Op0VT, (128 / Op0VT.getSizeInBits()));
656     EVT OpVecVT = EVT::getVectorVT(*CurDAG->getContext(),
657                                    OpVT, (128 / OpVT.getSizeInBits()));
658     SDValue shufMask;
659 
660     switch (Op0VT.getSimpleVT().SimpleTy) {
661     default:
662       report_fatal_error("CellSPU Select: Unhandled zero/any extend EVT");
663       /*NOTREACHED*/
664     case MVT::i32:
665       shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
666                                  CurDAG->getConstant(0x80808080, MVT::i32),
667                                  CurDAG->getConstant(0x00010203, MVT::i32),
668                                  CurDAG->getConstant(0x80808080, MVT::i32),
669                                  CurDAG->getConstant(0x08090a0b, MVT::i32));
670       break;
671 
672     case MVT::i16:
673       shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
674                                  CurDAG->getConstant(0x80808080, MVT::i32),
675                                  CurDAG->getConstant(0x80800203, MVT::i32),
676                                  CurDAG->getConstant(0x80808080, MVT::i32),
677                                  CurDAG->getConstant(0x80800a0b, MVT::i32));
678       break;
679 
680     case MVT::i8:
681       shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
682                                  CurDAG->getConstant(0x80808080, MVT::i32),
683                                  CurDAG->getConstant(0x80808003, MVT::i32),
684                                  CurDAG->getConstant(0x80808080, MVT::i32),
685                                  CurDAG->getConstant(0x8080800b, MVT::i32));
686       break;
687     }
688 
689     SDNode *shufMaskLoad = emitBuildVector(shufMask.getNode());
690 
691     HandleSDNode PromoteScalar(CurDAG->getNode(SPUISD::PREFSLOT2VEC, dl,
692                                                Op0VecVT, Op0));
693 
694     SDValue PromScalar;
695     if (SDNode *N = SelectCode(PromoteScalar.getValue().getNode()))
696       PromScalar = SDValue(N, 0);
697     else
698       PromScalar = PromoteScalar.getValue();
699 
700     SDValue zextShuffle =
701             CurDAG->getNode(SPUISD::SHUFB, dl, OpVecVT,
702                             PromScalar, PromScalar,
703                             SDValue(shufMaskLoad, 0));
704 
705     HandleSDNode Dummy2(zextShuffle);
706     if (SDNode *N = SelectCode(Dummy2.getValue().getNode()))
707       zextShuffle = SDValue(N, 0);
708     else
709       zextShuffle = Dummy2.getValue();
710     HandleSDNode Dummy(CurDAG->getNode(SPUISD::VEC2PREFSLOT, dl, OpVT,
711                                        zextShuffle));
712 
713     CurDAG->ReplaceAllUsesWith(N, Dummy.getValue().getNode());
714     SelectCode(Dummy.getValue().getNode());
715     return Dummy.getValue().getNode();
716   } else if (Opc == ISD::ADD && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
717     SDNode *CGLoad =
718             emitBuildVector(getCarryGenerateShufMask(*CurDAG, dl).getNode());
719 
720     HandleSDNode Dummy(CurDAG->getNode(SPUISD::ADD64_MARKER, dl, OpVT,
721                                        N->getOperand(0), N->getOperand(1),
722                                        SDValue(CGLoad, 0)));
723 
724     CurDAG->ReplaceAllUsesWith(N, Dummy.getValue().getNode());
725     if (SDNode *N = SelectCode(Dummy.getValue().getNode()))
726       return N;
727     return Dummy.getValue().getNode();
728   } else if (Opc == ISD::SUB && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
729     SDNode *CGLoad =
730             emitBuildVector(getBorrowGenerateShufMask(*CurDAG, dl).getNode());
731 
732     HandleSDNode Dummy(CurDAG->getNode(SPUISD::SUB64_MARKER, dl, OpVT,
733                                        N->getOperand(0), N->getOperand(1),
734                                        SDValue(CGLoad, 0)));
735 
736     CurDAG->ReplaceAllUsesWith(N, Dummy.getValue().getNode());
737     if (SDNode *N = SelectCode(Dummy.getValue().getNode()))
738       return N;
739     return Dummy.getValue().getNode();
740   } else if (Opc == ISD::MUL && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
741     SDNode *CGLoad =
742             emitBuildVector(getCarryGenerateShufMask(*CurDAG, dl).getNode());
743 
744     HandleSDNode Dummy(CurDAG->getNode(SPUISD::MUL64_MARKER, dl, OpVT,
745                                        N->getOperand(0), N->getOperand(1),
746                                        SDValue(CGLoad, 0)));
747     CurDAG->ReplaceAllUsesWith(N, Dummy.getValue().getNode());
748     if (SDNode *N = SelectCode(Dummy.getValue().getNode()))
749       return N;
750     return Dummy.getValue().getNode();
751   } else if (Opc == ISD::TRUNCATE) {
752     SDValue Op0 = N->getOperand(0);
753     if ((Op0.getOpcode() == ISD::SRA || Op0.getOpcode() == ISD::SRL)
754         && OpVT == MVT::i32
755         && Op0.getValueType() == MVT::i64) {
756       // Catch (truncate:i32 ([sra|srl]:i64 arg, c), where c >= 32
757       //
758       // Take advantage of the fact that the upper 32 bits are in the
759       // i32 preferred slot and avoid shuffle gymnastics:
760       ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op0.getOperand(1));
761       if (CN != 0) {
762         unsigned shift_amt = unsigned(CN->getZExtValue());
763 
764         if (shift_amt >= 32) {
765           SDNode *hi32 =
766                   CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, OpVT,
767                                          Op0.getOperand(0), getRC(MVT::i32));
768 
769           shift_amt -= 32;
770           if (shift_amt > 0) {
771             // Take care of the additional shift, if present:
772             SDValue shift = CurDAG->getTargetConstant(shift_amt, MVT::i32);
773             unsigned Opc = SPU::ROTMAIr32_i32;
774 
775             if (Op0.getOpcode() == ISD::SRL)
776               Opc = SPU::ROTMr32;
777 
778             hi32 = CurDAG->getMachineNode(Opc, dl, OpVT, SDValue(hi32, 0),
779                                           shift);
780           }
781 
782           return hi32;
783         }
784       }
785     }
786   } else if (Opc == ISD::SHL) {
787     if (OpVT == MVT::i64)
788       return SelectSHLi64(N, OpVT);
789   } else if (Opc == ISD::SRL) {
790     if (OpVT == MVT::i64)
791       return SelectSRLi64(N, OpVT);
792   } else if (Opc == ISD::SRA) {
793     if (OpVT == MVT::i64)
794       return SelectSRAi64(N, OpVT);
795   } else if (Opc == ISD::FNEG
796              && (OpVT == MVT::f64 || OpVT == MVT::v2f64)) {
797     DebugLoc dl = N->getDebugLoc();
798     // Check if the pattern is a special form of DFNMS:
799     // (fneg (fsub (fmul R64FP:$rA, R64FP:$rB), R64FP:$rC))
800     SDValue Op0 = N->getOperand(0);
801     if (Op0.getOpcode() == ISD::FSUB) {
802       SDValue Op00 = Op0.getOperand(0);
803       if (Op00.getOpcode() == ISD::FMUL) {
804         unsigned Opc = SPU::DFNMSf64;
805         if (OpVT == MVT::v2f64)
806           Opc = SPU::DFNMSv2f64;
807 
808         return CurDAG->getMachineNode(Opc, dl, OpVT,
809                                       Op00.getOperand(0),
810                                       Op00.getOperand(1),
811                                       Op0.getOperand(1));
812       }
813     }
814 
815     SDValue negConst = CurDAG->getConstant(0x8000000000000000ULL, MVT::i64);
816     SDNode *signMask = 0;
817     unsigned Opc = SPU::XORfneg64;
818 
819     if (OpVT == MVT::f64) {
820       signMask = SelectI64Constant(negConst.getNode(), MVT::i64, dl);
821     } else if (OpVT == MVT::v2f64) {
822       Opc = SPU::XORfnegvec;
823       signMask = emitBuildVector(CurDAG->getNode(ISD::BUILD_VECTOR, dl,
824                                                  MVT::v2i64,
825                                                  negConst, negConst).getNode());
826     }
827 
828     return CurDAG->getMachineNode(Opc, dl, OpVT,
829                                   N->getOperand(0), SDValue(signMask, 0));
830   } else if (Opc == ISD::FABS) {
831     if (OpVT == MVT::f64) {
832       SDNode *signMask = SelectI64Constant(0x7fffffffffffffffULL, MVT::i64, dl);
833       return CurDAG->getMachineNode(SPU::ANDfabs64, dl, OpVT,
834                                     N->getOperand(0), SDValue(signMask, 0));
835     } else if (OpVT == MVT::v2f64) {
836       SDValue absConst = CurDAG->getConstant(0x7fffffffffffffffULL, MVT::i64);
837       SDValue absVec = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64,
838                                        absConst, absConst);
839       SDNode *signMask = emitBuildVector(absVec.getNode());
840       return CurDAG->getMachineNode(SPU::ANDfabsvec, dl, OpVT,
841                                     N->getOperand(0), SDValue(signMask, 0));
842     }
843   } else if (Opc == SPUISD::LDRESULT) {
844     // Custom select instructions for LDRESULT
845     EVT VT = N->getValueType(0);
846     SDValue Arg = N->getOperand(0);
847     SDValue Chain = N->getOperand(1);
848     SDNode *Result;
849 
850     Result = CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, VT,
851                                     MVT::Other, Arg,
852                                     getRC( VT.getSimpleVT()), Chain);
853     return Result;
854 
855   } else if (Opc == SPUISD::IndirectAddr) {
856     // Look at the operands: SelectCode() will catch the cases that aren't
857     // specifically handled here.
858     //
859     // SPUInstrInfo catches the following patterns:
860     // (SPUindirect (SPUhi ...), (SPUlo ...))
861     // (SPUindirect $sp, imm)
862     EVT VT = N->getValueType(0);
863     SDValue Op0 = N->getOperand(0);
864     SDValue Op1 = N->getOperand(1);
865     RegisterSDNode *RN;
866 
867     if ((Op0.getOpcode() != SPUISD::Hi && Op1.getOpcode() != SPUISD::Lo)
868         || (Op0.getOpcode() == ISD::Register
869             && ((RN = dyn_cast<RegisterSDNode>(Op0.getNode())) != 0
870                 && RN->getReg() != SPU::R1))) {
871       NewOpc = SPU::Ar32;
872       Ops[1] = Op1;
873       if (Op1.getOpcode() == ISD::Constant) {
874         ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
875         Op1 = CurDAG->getTargetConstant(CN->getSExtValue(), VT);
876         if (isInt<10>(CN->getSExtValue())) {
877           NewOpc = SPU::AIr32;
878           Ops[1] = Op1;
879         } else {
880           Ops[1] = SDValue(CurDAG->getMachineNode(SPU::ILr32, dl,
881                                                   N->getValueType(0),
882                                                   Op1),
883                            0);
884         }
885       }
886       Ops[0] = Op0;
887       n_ops = 2;
888     }
889   }
890 
891   if (n_ops > 0) {
892     if (N->hasOneUse())
893       return CurDAG->SelectNodeTo(N, NewOpc, OpVT, Ops, n_ops);
894     else
895       return CurDAG->getMachineNode(NewOpc, dl, OpVT, Ops, n_ops);
896   } else
897     return SelectCode(N);
898 }
899 
900 /*!
901  * Emit the instruction sequence for i64 left shifts. The basic algorithm
902  * is to fill the bottom two word slots with zeros so that zeros are shifted
903  * in as the entire quadword is shifted left.
904  *
905  * \note This code could also be used to implement v2i64 shl.
906  *
907  * @param Op The shl operand
908  * @param OpVT Op's machine value value type (doesn't need to be passed, but
909  * makes life easier.)
910  * @return The SDNode with the entire instruction sequence
911  */
912 SDNode *
SelectSHLi64(SDNode * N,EVT OpVT)913 SPUDAGToDAGISel::SelectSHLi64(SDNode *N, EVT OpVT) {
914   SDValue Op0 = N->getOperand(0);
915   EVT VecVT = EVT::getVectorVT(*CurDAG->getContext(),
916                                OpVT, (128 / OpVT.getSizeInBits()));
917   SDValue ShiftAmt = N->getOperand(1);
918   EVT ShiftAmtVT = ShiftAmt.getValueType();
919   SDNode *VecOp0, *SelMask, *ZeroFill, *Shift = 0;
920   SDValue SelMaskVal;
921   DebugLoc dl = N->getDebugLoc();
922 
923   VecOp0 = CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, VecVT,
924                                   Op0, getRC(MVT::v2i64) );
925   SelMaskVal = CurDAG->getTargetConstant(0xff00ULL, MVT::i16);
926   SelMask = CurDAG->getMachineNode(SPU::FSMBIv2i64, dl, VecVT, SelMaskVal);
927   ZeroFill = CurDAG->getMachineNode(SPU::ILv2i64, dl, VecVT,
928                                     CurDAG->getTargetConstant(0, OpVT));
929   VecOp0 = CurDAG->getMachineNode(SPU::SELBv2i64, dl, VecVT,
930                                   SDValue(ZeroFill, 0),
931                                   SDValue(VecOp0, 0),
932                                   SDValue(SelMask, 0));
933 
934   if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(ShiftAmt)) {
935     unsigned bytes = unsigned(CN->getZExtValue()) >> 3;
936     unsigned bits = unsigned(CN->getZExtValue()) & 7;
937 
938     if (bytes > 0) {
939       Shift =
940         CurDAG->getMachineNode(SPU::SHLQBYIv2i64, dl, VecVT,
941                                SDValue(VecOp0, 0),
942                                CurDAG->getTargetConstant(bytes, ShiftAmtVT));
943     }
944 
945     if (bits > 0) {
946       Shift =
947         CurDAG->getMachineNode(SPU::SHLQBIIv2i64, dl, VecVT,
948                                SDValue((Shift != 0 ? Shift : VecOp0), 0),
949                                CurDAG->getTargetConstant(bits, ShiftAmtVT));
950     }
951   } else {
952     SDNode *Bytes =
953       CurDAG->getMachineNode(SPU::ROTMIr32, dl, ShiftAmtVT,
954                              ShiftAmt,
955                              CurDAG->getTargetConstant(3, ShiftAmtVT));
956     SDNode *Bits =
957       CurDAG->getMachineNode(SPU::ANDIr32, dl, ShiftAmtVT,
958                              ShiftAmt,
959                              CurDAG->getTargetConstant(7, ShiftAmtVT));
960     Shift =
961       CurDAG->getMachineNode(SPU::SHLQBYv2i64, dl, VecVT,
962                              SDValue(VecOp0, 0), SDValue(Bytes, 0));
963     Shift =
964       CurDAG->getMachineNode(SPU::SHLQBIv2i64, dl, VecVT,
965                              SDValue(Shift, 0), SDValue(Bits, 0));
966   }
967 
968   return CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl,
969                                 OpVT, SDValue(Shift, 0), getRC(MVT::i64));
970 }
971 
972 /*!
973  * Emit the instruction sequence for i64 logical right shifts.
974  *
975  * @param Op The shl operand
976  * @param OpVT Op's machine value value type (doesn't need to be passed, but
977  * makes life easier.)
978  * @return The SDNode with the entire instruction sequence
979  */
980 SDNode *
SelectSRLi64(SDNode * N,EVT OpVT)981 SPUDAGToDAGISel::SelectSRLi64(SDNode *N, EVT OpVT) {
982   SDValue Op0 = N->getOperand(0);
983   EVT VecVT = EVT::getVectorVT(*CurDAG->getContext(),
984                                OpVT, (128 / OpVT.getSizeInBits()));
985   SDValue ShiftAmt = N->getOperand(1);
986   EVT ShiftAmtVT = ShiftAmt.getValueType();
987   SDNode *VecOp0, *Shift = 0;
988   DebugLoc dl = N->getDebugLoc();
989 
990   VecOp0 = CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, VecVT,
991                                   Op0, getRC(MVT::v2i64) );
992 
993   if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(ShiftAmt)) {
994     unsigned bytes = unsigned(CN->getZExtValue()) >> 3;
995     unsigned bits = unsigned(CN->getZExtValue()) & 7;
996 
997     if (bytes > 0) {
998       Shift =
999         CurDAG->getMachineNode(SPU::ROTQMBYIv2i64, dl, VecVT,
1000                                SDValue(VecOp0, 0),
1001                                CurDAG->getTargetConstant(bytes, ShiftAmtVT));
1002     }
1003 
1004     if (bits > 0) {
1005       Shift =
1006         CurDAG->getMachineNode(SPU::ROTQMBIIv2i64, dl, VecVT,
1007                                SDValue((Shift != 0 ? Shift : VecOp0), 0),
1008                                CurDAG->getTargetConstant(bits, ShiftAmtVT));
1009     }
1010   } else {
1011     SDNode *Bytes =
1012       CurDAG->getMachineNode(SPU::ROTMIr32, dl, ShiftAmtVT,
1013                              ShiftAmt,
1014                              CurDAG->getTargetConstant(3, ShiftAmtVT));
1015     SDNode *Bits =
1016       CurDAG->getMachineNode(SPU::ANDIr32, dl, ShiftAmtVT,
1017                              ShiftAmt,
1018                              CurDAG->getTargetConstant(7, ShiftAmtVT));
1019 
1020     // Ensure that the shift amounts are negated!
1021     Bytes = CurDAG->getMachineNode(SPU::SFIr32, dl, ShiftAmtVT,
1022                                    SDValue(Bytes, 0),
1023                                    CurDAG->getTargetConstant(0, ShiftAmtVT));
1024 
1025     Bits = CurDAG->getMachineNode(SPU::SFIr32, dl, ShiftAmtVT,
1026                                   SDValue(Bits, 0),
1027                                   CurDAG->getTargetConstant(0, ShiftAmtVT));
1028 
1029     Shift =
1030       CurDAG->getMachineNode(SPU::ROTQMBYv2i64, dl, VecVT,
1031                              SDValue(VecOp0, 0), SDValue(Bytes, 0));
1032     Shift =
1033       CurDAG->getMachineNode(SPU::ROTQMBIv2i64, dl, VecVT,
1034                              SDValue(Shift, 0), SDValue(Bits, 0));
1035   }
1036 
1037   return CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl,
1038                                 OpVT, SDValue(Shift, 0), getRC(MVT::i64));
1039 }
1040 
1041 /*!
1042  * Emit the instruction sequence for i64 arithmetic right shifts.
1043  *
1044  * @param Op The shl operand
1045  * @param OpVT Op's machine value value type (doesn't need to be passed, but
1046  * makes life easier.)
1047  * @return The SDNode with the entire instruction sequence
1048  */
1049 SDNode *
SelectSRAi64(SDNode * N,EVT OpVT)1050 SPUDAGToDAGISel::SelectSRAi64(SDNode *N, EVT OpVT) {
1051   // Promote Op0 to vector
1052   EVT VecVT = EVT::getVectorVT(*CurDAG->getContext(),
1053                                OpVT, (128 / OpVT.getSizeInBits()));
1054   SDValue ShiftAmt = N->getOperand(1);
1055   EVT ShiftAmtVT = ShiftAmt.getValueType();
1056   DebugLoc dl = N->getDebugLoc();
1057 
1058   SDNode *VecOp0 =
1059     CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl,
1060                            VecVT, N->getOperand(0), getRC(MVT::v2i64));
1061 
1062   SDValue SignRotAmt = CurDAG->getTargetConstant(31, ShiftAmtVT);
1063   SDNode *SignRot =
1064     CurDAG->getMachineNode(SPU::ROTMAIv2i64_i32, dl, MVT::v2i64,
1065                            SDValue(VecOp0, 0), SignRotAmt);
1066   SDNode *UpperHalfSign =
1067     CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl,
1068                            MVT::i32, SDValue(SignRot, 0), getRC(MVT::i32));
1069 
1070   SDNode *UpperHalfSignMask =
1071     CurDAG->getMachineNode(SPU::FSM64r32, dl, VecVT, SDValue(UpperHalfSign, 0));
1072   SDNode *UpperLowerMask =
1073     CurDAG->getMachineNode(SPU::FSMBIv2i64, dl, VecVT,
1074                            CurDAG->getTargetConstant(0xff00ULL, MVT::i16));
1075   SDNode *UpperLowerSelect =
1076     CurDAG->getMachineNode(SPU::SELBv2i64, dl, VecVT,
1077                            SDValue(UpperHalfSignMask, 0),
1078                            SDValue(VecOp0, 0),
1079                            SDValue(UpperLowerMask, 0));
1080 
1081   SDNode *Shift = 0;
1082 
1083   if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(ShiftAmt)) {
1084     unsigned bytes = unsigned(CN->getZExtValue()) >> 3;
1085     unsigned bits = unsigned(CN->getZExtValue()) & 7;
1086 
1087     if (bytes > 0) {
1088       bytes = 31 - bytes;
1089       Shift =
1090         CurDAG->getMachineNode(SPU::ROTQBYIv2i64, dl, VecVT,
1091                                SDValue(UpperLowerSelect, 0),
1092                                CurDAG->getTargetConstant(bytes, ShiftAmtVT));
1093     }
1094 
1095     if (bits > 0) {
1096       bits = 8 - bits;
1097       Shift =
1098         CurDAG->getMachineNode(SPU::ROTQBIIv2i64, dl, VecVT,
1099                                SDValue((Shift != 0 ? Shift : UpperLowerSelect), 0),
1100                                CurDAG->getTargetConstant(bits, ShiftAmtVT));
1101     }
1102   } else {
1103     SDNode *NegShift =
1104       CurDAG->getMachineNode(SPU::SFIr32, dl, ShiftAmtVT,
1105                              ShiftAmt, CurDAG->getTargetConstant(0, ShiftAmtVT));
1106 
1107     Shift =
1108       CurDAG->getMachineNode(SPU::ROTQBYBIv2i64_r32, dl, VecVT,
1109                              SDValue(UpperLowerSelect, 0), SDValue(NegShift, 0));
1110     Shift =
1111       CurDAG->getMachineNode(SPU::ROTQBIv2i64, dl, VecVT,
1112                              SDValue(Shift, 0), SDValue(NegShift, 0));
1113   }
1114 
1115   return CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl,
1116                                 OpVT, SDValue(Shift, 0), getRC(MVT::i64));
1117 }
1118 
1119 /*!
1120  Do the necessary magic necessary to load a i64 constant
1121  */
SelectI64Constant(SDNode * N,EVT OpVT,DebugLoc dl)1122 SDNode *SPUDAGToDAGISel::SelectI64Constant(SDNode *N, EVT OpVT,
1123                                            DebugLoc dl) {
1124   ConstantSDNode *CN = cast<ConstantSDNode>(N);
1125   return SelectI64Constant(CN->getZExtValue(), OpVT, dl);
1126 }
1127 
SelectI64Constant(uint64_t Value64,EVT OpVT,DebugLoc dl)1128 SDNode *SPUDAGToDAGISel::SelectI64Constant(uint64_t Value64, EVT OpVT,
1129                                            DebugLoc dl) {
1130   EVT OpVecVT = EVT::getVectorVT(*CurDAG->getContext(), OpVT, 2);
1131   SDValue i64vec =
1132           SPU::LowerV2I64Splat(OpVecVT, *CurDAG, Value64, dl);
1133 
1134   // Here's where it gets interesting, because we have to parse out the
1135   // subtree handed back in i64vec:
1136 
1137   if (i64vec.getOpcode() == ISD::BITCAST) {
1138     // The degenerate case where the upper and lower bits in the splat are
1139     // identical:
1140     SDValue Op0 = i64vec.getOperand(0);
1141 
1142     ReplaceUses(i64vec, Op0);
1143     return CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, OpVT,
1144                                   SDValue(emitBuildVector(Op0.getNode()), 0),
1145                                   getRC(MVT::i64));
1146   } else if (i64vec.getOpcode() == SPUISD::SHUFB) {
1147     SDValue lhs = i64vec.getOperand(0);
1148     SDValue rhs = i64vec.getOperand(1);
1149     SDValue shufmask = i64vec.getOperand(2);
1150 
1151     if (lhs.getOpcode() == ISD::BITCAST) {
1152       ReplaceUses(lhs, lhs.getOperand(0));
1153       lhs = lhs.getOperand(0);
1154     }
1155 
1156     SDNode *lhsNode = (lhs.getNode()->isMachineOpcode()
1157                        ? lhs.getNode()
1158                        : emitBuildVector(lhs.getNode()));
1159 
1160     if (rhs.getOpcode() == ISD::BITCAST) {
1161       ReplaceUses(rhs, rhs.getOperand(0));
1162       rhs = rhs.getOperand(0);
1163     }
1164 
1165     SDNode *rhsNode = (rhs.getNode()->isMachineOpcode()
1166                        ? rhs.getNode()
1167                        : emitBuildVector(rhs.getNode()));
1168 
1169     if (shufmask.getOpcode() == ISD::BITCAST) {
1170       ReplaceUses(shufmask, shufmask.getOperand(0));
1171       shufmask = shufmask.getOperand(0);
1172     }
1173 
1174     SDNode *shufMaskNode = (shufmask.getNode()->isMachineOpcode()
1175                             ? shufmask.getNode()
1176                             : emitBuildVector(shufmask.getNode()));
1177 
1178    SDValue shufNode =
1179             CurDAG->getNode(SPUISD::SHUFB, dl, OpVecVT,
1180                                    SDValue(lhsNode, 0), SDValue(rhsNode, 0),
1181                                    SDValue(shufMaskNode, 0));
1182     HandleSDNode Dummy(shufNode);
1183     SDNode *SN = SelectCode(Dummy.getValue().getNode());
1184     if (SN == 0) SN = Dummy.getValue().getNode();
1185 
1186     return CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl,
1187                                   OpVT, SDValue(SN, 0), getRC(MVT::i64));
1188   } else if (i64vec.getOpcode() == ISD::BUILD_VECTOR) {
1189     return CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS, dl, OpVT,
1190                                   SDValue(emitBuildVector(i64vec.getNode()), 0),
1191                                   getRC(MVT::i64));
1192   } else {
1193     report_fatal_error("SPUDAGToDAGISel::SelectI64Constant: Unhandled i64vec"
1194                       "condition");
1195   }
1196 }
1197 
1198 /// createSPUISelDag - This pass converts a legalized DAG into a
1199 /// SPU-specific DAG, ready for instruction scheduling.
1200 ///
createSPUISelDag(SPUTargetMachine & TM)1201 FunctionPass *llvm::createSPUISelDag(SPUTargetMachine &TM) {
1202   return new SPUDAGToDAGISel(TM);
1203 }
1204