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Searched refs:CondCode2 (Results 1 – 6 of 6) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64InstructionSelector.cpp533 AArch64CC::CondCode &CondCode2) { in changeFCMPPredToAArch64CC() argument
534 CondCode2 = AArch64CC::AL; in changeFCMPPredToAArch64CC()
555 CondCode2 = AArch64CC::GT; in changeFCMPPredToAArch64CC()
565 CondCode2 = AArch64CC::VS; in changeFCMPPredToAArch64CC()
DAArch64ISelLowering.cpp1333 AArch64CC::CondCode &CondCode2) { in changeFPCCToAArch64CC() argument
1334 CondCode2 = AArch64CC::AL; in changeFPCCToAArch64CC()
1358 CondCode2 = AArch64CC::GT; in changeFPCCToAArch64CC()
1368 CondCode2 = AArch64CC::VS; in changeFPCCToAArch64CC()
1396 AArch64CC::CondCode &CondCode2) { in changeFPCCToANDAArch64CC() argument
1397 CondCode2 = AArch64CC::AL; in changeFPCCToANDAArch64CC()
1400 changeFPCCToAArch64CC(CC, CondCode, CondCode2); in changeFPCCToANDAArch64CC()
1401 assert(CondCode2 == AArch64CC::AL); in changeFPCCToANDAArch64CC()
1408 CondCode2 = AArch64CC::NE; in changeFPCCToANDAArch64CC()
1415 CondCode2 = AArch64CC::LE; in changeFPCCToANDAArch64CC()
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMISelLowering.cpp1030 ARMCC::CondCodes &CondCode2) { in FPCCToARMCC() argument
1031 CondCode2 = ARMCC::AL; in FPCCToARMCC()
1042 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break; in FPCCToARMCC()
1045 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break; in FPCCToARMCC()
2801 ARMCC::CondCodes CondCode, CondCode2; in LowerSELECT_CC() local
2802 FPCCToARMCC(CC, CondCode, CondCode2); in LowerSELECT_CC()
2809 if (CondCode2 != ARMCC::AL) { in LowerSELECT_CC()
2810 SDValue ARMcc2 = DAG.getConstant(CondCode2, MVT::i32); in LowerSELECT_CC()
2961 ARMCC::CondCodes CondCode, CondCode2; in LowerBR_CC() local
2962 FPCCToARMCC(CC, CondCode, CondCode2); in LowerBR_CC()
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/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp1080 AArch64CC::CondCode &CondCode2) { in changeFPCCToAArch64CC() argument
1081 CondCode2 = AArch64CC::AL; in changeFPCCToAArch64CC()
1105 CondCode2 = AArch64CC::GT; in changeFPCCToAArch64CC()
1115 CondCode2 = AArch64CC::VS; in changeFPCCToAArch64CC()
1143 AArch64CC::CondCode &CondCode2) { in changeFPCCToANDAArch64CC() argument
1144 CondCode2 = AArch64CC::AL; in changeFPCCToANDAArch64CC()
1147 changeFPCCToAArch64CC(CC, CondCode, CondCode2); in changeFPCCToANDAArch64CC()
1148 assert(CondCode2 == AArch64CC::AL); in changeFPCCToANDAArch64CC()
1155 CondCode2 = AArch64CC::NE; in changeFPCCToANDAArch64CC()
1162 CondCode2 = AArch64CC::LE; in changeFPCCToANDAArch64CC()
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/external/llvm/lib/Target/ARM/
DARMISelLowering.cpp1347 ARMCC::CondCodes &CondCode2) { in FPCCToARMCC() argument
1348 CondCode2 = ARMCC::AL; in FPCCToARMCC()
1359 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break; in FPCCToARMCC()
1362 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break; in FPCCToARMCC()
3906 ARMCC::CondCodes CondCode, CondCode2; in LowerSELECT_CC() local
3907 FPCCToARMCC(CC, CondCode, CondCode2); in LowerSELECT_CC()
3929 if (CondCode2 != ARMCC::AL) { in LowerSELECT_CC()
3930 SDValue ARMcc2 = DAG.getConstant(CondCode2, dl, MVT::i32); in LowerSELECT_CC()
4097 ARMCC::CondCodes CondCode, CondCode2; in LowerBR_CC() local
4098 FPCCToARMCC(CC, CondCode, CondCode2); in LowerBR_CC()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMISelLowering.cpp1524 ARMCC::CondCodes &CondCode2, bool &InvalidOnQNaN) { in FPCCToARMCC() argument
1525 CondCode2 = ARMCC::AL; in FPCCToARMCC()
1542 CondCode2 = ARMCC::GT; in FPCCToARMCC()
1549 CondCode2 = ARMCC::VS; in FPCCToARMCC()
4515 ARMCC::CondCodes CondCode, CondCode2; in LowerSELECT_CC() local
4517 FPCCToARMCC(CC, CondCode, CondCode2, InvalidOnQNaN); in LowerSELECT_CC()
4542 if (CondCode2 != ARMCC::AL) { in LowerSELECT_CC()
4543 SDValue ARMcc2 = DAG.getConstant(CondCode2, dl, MVT::i32); in LowerSELECT_CC()
4771 ARMCC::CondCodes CondCode, CondCode2; in LowerBR_CC() local
4773 FPCCToARMCC(CC, CondCode, CondCode2, InvalidOnQNaN); in LowerBR_CC()
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