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Searched refs:Cyclone (Results 1 – 23 of 23) sorted by relevance

/external/u-boot/arch/arm/mach-socfpga/
DKconfig36 bool "Altera SOCFPGA SoCDK (Cyclone V)"
40 bool "Devboards DBM-SoC1 (Cyclone V)"
44 bool "EBV SoCrates (Cyclone V)"
48 bool "IS1 (Cyclone V)"
52 bool "samtec VIN|ING FPGA (Cyclone V)"
57 bool "SR1500 (Cyclone V)"
61 bool "Terasic DE0-Nano-Atlas (Cyclone V)"
65 bool "Terasic DE10-Nano (Cyclone V)"
69 bool "Terasic DE1-SoC (Cyclone V)"
73 bool "Terasic SoCkit (Cyclone V)"
/external/u-boot/drivers/fpga/
DKconfig25 bool "Enable Altera FPGA driver for Cyclone II"
28 Say Y here to enable the Altera Cyclone II FPGA specific driver
30 This provides common functionality for Altera Cyclone II devices.
32 on Altera Cyclone II device.
/external/llvm/lib/Target/AArch64/
DAArch64.td47 /// Cyclone has register move instructions which are "free".
51 /// Cyclone has instructions which zero registers for "free".
204 def ProcCyclone : SubtargetFeature<"cyclone", "ARMProcFamily", "Cyclone",
205 "Cyclone", [
DAArch64SchedCyclone.td1 //=- AArch64SchedCyclone.td - Cyclone Scheduling Definitions -*- tablegen -*-=//
10 // This file defines the machine model for AArch64 Cyclone to support
24 // Define each kind of processor resource and number available on Cyclone.
95 // Define scheduler read/write resources and latency on Cyclone.
243 def : SchedAlias<WriteLDIdx, CyWriteLDIdx>; // Map AArch64->Cyclone type.
249 def : SchedAlias<WriteSTIdx, CyWriteSTIdx>; // Map AArch64->Cyclone type.
257 def : SchedAlias<ReadAdrBase, CyReadAdrBase>; // Map AArch64->Cyclone type.
305 // Define some longer latency vector op types for Cyclone.
318 // TODO: Add Cyclone-specific zero-cycle zeros. LLVM currently
DAArch64Subtarget.cpp56 case Cyclone: in initializeProperties()
DAArch64Subtarget.h44 Cyclone, enumerator
DAArch64SystemOperands.td1015 // Cyclone specific system registers
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64SchedCyclone.td1 //=- AArch64SchedCyclone.td - Cyclone Scheduling Definitions -*- tablegen -*-=//
10 // This file defines the machine model for AArch64 Cyclone to support
26 // Define each kind of processor resource and number available on Cyclone.
97 // Define scheduler read/write resources and latency on Cyclone.
245 def : SchedAlias<WriteLDIdx, CyWriteLDIdx>; // Map AArch64->Cyclone type.
251 def : SchedAlias<WriteSTIdx, CyWriteSTIdx>; // Map AArch64->Cyclone type.
259 def : SchedAlias<ReadAdrBase, CyReadAdrBase>; // Map AArch64->Cyclone type.
307 // Define some longer latency vector op types for Cyclone.
320 // TODO: Add Cyclone-specific zero-cycle zeros. LLVM currently
DAArch64.td80 /// Cyclone has register move instructions which are "free".
84 /// Cyclone has instructions which zero registers for "free".
337 def ProcCyclone : SubtargetFeature<"cyclone", "ARMProcFamily", "Cyclone",
338 "Cyclone", [
DAArch64Subtarget.cpp70 case Cyclone: in initializeProperties()
DAArch64Subtarget.h49 Cyclone, enumerator
DAArch64SystemOperands.td1329 // Cyclone specific system registers
/external/u-boot/arch/arm/dts/
Dsocfpga_cyclone5_sr1500.dts9 model = "SoCFPGA Cyclone V SR1500";
Dsocfpga_cyclone5_is1.dts9 model = "SoCFPGA Cyclone V IS1";
Dsocfpga_cyclone5_socdk.dts9 model = "Altera SOCFPGA Cyclone V SoC Development Kit";
/external/llvm/test/CodeGen/ARM/
Dzero-cycle-zero.ll51 ; crafted behaviour that we might break in Cyclone.
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dzero-cycle-zero.ll51 ; crafted behaviour that we might break in Cyclone.
/external/llvm/test/CodeGen/AArch64/
Dmerge-store.ll26 ; On Cyclone, the stores should not get merged into a 16-byte store because
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Dmerge-store.ll25 ; On Cyclone, the stores should not get merged into a 16-byte store because
/external/llvm/lib/Target/ARM/
DARM.td104 // Cyclone has preferred instructions for zeroing VFP registers, which can
797 // Cyclone is very similar to swift
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARM.td152 // Cyclone can zero VFP registers in 0 cycles.
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/
DAArch64GenSubtargetInfo.inc112 …{ "cyclone", "Cyclone", { AArch64::ProcCyclone }, { AArch64::FeatureAlternateSExtLoadCVTF32Pattern…
10947 if (Bits[AArch64::ProcCyclone] && ARMProcFamily < Cyclone) ARMProcFamily = Cyclone;
/external/cldr/tools/java/org/unicode/cldr/util/data/external/
D2013-1_UNLOCODE_CodeListPart3.csv13416 ,"US","YDL","Cyclone","Cyclone","WV","--3-----","RL","0901",,"3743N 08141W",