1 //===-- AArch64Subtarget.cpp - AArch64 Subtarget Information ----*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the AArch64 specific subclass of TargetSubtarget.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "AArch64Subtarget.h"
15 #include "AArch64InstrInfo.h"
16 #include "AArch64PBQPRegAlloc.h"
17 #include "llvm/CodeGen/MachineScheduler.h"
18 #include "llvm/IR/GlobalValue.h"
19 #include "llvm/Support/TargetRegistry.h"
20
21 using namespace llvm;
22
23 #define DEBUG_TYPE "aarch64-subtarget"
24
25 #define GET_SUBTARGETINFO_CTOR
26 #define GET_SUBTARGETINFO_TARGET_DESC
27 #include "AArch64GenSubtargetInfo.inc"
28
29 static cl::opt<bool>
30 EnableEarlyIfConvert("aarch64-early-ifcvt", cl::desc("Enable the early if "
31 "converter pass"), cl::init(true), cl::Hidden);
32
33 // If OS supports TBI, use this flag to enable it.
34 static cl::opt<bool>
35 UseAddressTopByteIgnored("aarch64-use-tbi", cl::desc("Assume that top byte of "
36 "an address is ignored"), cl::init(false), cl::Hidden);
37
38 AArch64Subtarget &
initializeSubtargetDependencies(StringRef FS)39 AArch64Subtarget::initializeSubtargetDependencies(StringRef FS) {
40 // Determine default and user-specified characteristics
41
42 if (CPUString.empty())
43 CPUString = "generic";
44
45 ParseSubtargetFeatures(CPUString, FS);
46 initializeProperties();
47
48 return *this;
49 }
50
initializeProperties()51 void AArch64Subtarget::initializeProperties() {
52 // Initialize CPU specific properties. We should add a tablegen feature for
53 // this in the future so we can specify it together with the subtarget
54 // features.
55 switch (ARMProcFamily) {
56 case Cyclone:
57 CacheLineSize = 64;
58 PrefetchDistance = 280;
59 MinPrefetchStride = 2048;
60 MaxPrefetchIterationsAhead = 3;
61 break;
62 case CortexA57:
63 MaxInterleaveFactor = 4;
64 break;
65 case ExynosM1:
66 PrefFunctionAlignment = 4;
67 PrefLoopAlignment = 3;
68 break;
69 case Kryo:
70 MaxInterleaveFactor = 4;
71 VectorInsertExtractBaseCost = 2;
72 CacheLineSize = 128;
73 PrefetchDistance = 740;
74 MinPrefetchStride = 1024;
75 MaxPrefetchIterationsAhead = 11;
76 break;
77 case Vulcan:
78 MaxInterleaveFactor = 4;
79 break;
80 case CortexA35: break;
81 case CortexA53: break;
82 case CortexA72: break;
83 case CortexA73: break;
84 case Others: break;
85 }
86 }
87
AArch64Subtarget(const Triple & TT,const std::string & CPU,const std::string & FS,const TargetMachine & TM,bool LittleEndian)88 AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU,
89 const std::string &FS,
90 const TargetMachine &TM, bool LittleEndian)
91 : AArch64GenSubtargetInfo(TT, CPU, FS),
92 ReserveX18(TT.isOSDarwin() || TT.isAndroid()), IsLittle(LittleEndian),
93 CPUString(CPU), TargetTriple(TT), FrameLowering(),
94 InstrInfo(initializeSubtargetDependencies(FS)), TSInfo(),
95 TLInfo(TM, *this), GISel() {}
96
getCallLowering() const97 const CallLowering *AArch64Subtarget::getCallLowering() const {
98 assert(GISel && "Access to GlobalISel APIs not set");
99 return GISel->getCallLowering();
100 }
101
getRegBankInfo() const102 const RegisterBankInfo *AArch64Subtarget::getRegBankInfo() const {
103 assert(GISel && "Access to GlobalISel APIs not set");
104 return GISel->getRegBankInfo();
105 }
106
107 /// Find the target operand flags that describe how a global value should be
108 /// referenced for the current subtarget.
109 unsigned char
ClassifyGlobalReference(const GlobalValue * GV,const TargetMachine & TM) const110 AArch64Subtarget::ClassifyGlobalReference(const GlobalValue *GV,
111 const TargetMachine &TM) const {
112 // MachO large model always goes via a GOT, simply to get a single 8-byte
113 // absolute relocation on all global addresses.
114 if (TM.getCodeModel() == CodeModel::Large && isTargetMachO())
115 return AArch64II::MO_GOT;
116
117 if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
118 return AArch64II::MO_GOT;
119
120 // The small code mode's direct accesses use ADRP, which cannot necessarily
121 // produce the value 0 (if the code is above 4GB).
122 if (TM.getCodeModel() == CodeModel::Small && GV->hasExternalWeakLinkage())
123 return AArch64II::MO_GOT;
124
125 return AArch64II::MO_NO_FLAG;
126 }
127
128 /// This function returns the name of a function which has an interface
129 /// like the non-standard bzero function, if such a function exists on
130 /// the current subtarget and it is considered prefereable over
131 /// memset with zero passed as the second argument. Otherwise it
132 /// returns null.
getBZeroEntry() const133 const char *AArch64Subtarget::getBZeroEntry() const {
134 // Prefer bzero on Darwin only.
135 if(isTargetDarwin())
136 return "bzero";
137
138 return nullptr;
139 }
140
overrideSchedPolicy(MachineSchedPolicy & Policy,unsigned NumRegionInstrs) const141 void AArch64Subtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
142 unsigned NumRegionInstrs) const {
143 // LNT run (at least on Cyclone) showed reasonably significant gains for
144 // bi-directional scheduling. 253.perlbmk.
145 Policy.OnlyTopDown = false;
146 Policy.OnlyBottomUp = false;
147 // Enabling or Disabling the latency heuristic is a close call: It seems to
148 // help nearly no benchmark on out-of-order architectures, on the other hand
149 // it regresses register pressure on a few benchmarking.
150 Policy.DisableLatencyHeuristic = DisableLatencySchedHeuristic;
151 }
152
enableEarlyIfConversion() const153 bool AArch64Subtarget::enableEarlyIfConversion() const {
154 return EnableEarlyIfConvert;
155 }
156
supportsAddressTopByteIgnored() const157 bool AArch64Subtarget::supportsAddressTopByteIgnored() const {
158 if (!UseAddressTopByteIgnored)
159 return false;
160
161 if (TargetTriple.isiOS()) {
162 unsigned Major, Minor, Micro;
163 TargetTriple.getiOSVersion(Major, Minor, Micro);
164 return Major >= 8;
165 }
166
167 return false;
168 }
169
170 std::unique_ptr<PBQPRAConstraint>
getCustomPBQPConstraints() const171 AArch64Subtarget::getCustomPBQPConstraints() const {
172 return balanceFPOps() ? llvm::make_unique<A57ChainingConstraint>() : nullptr;
173 }
174