Searched refs:DDR3L (Results 1 – 18 of 18) sorted by relevance
| /external/u-boot/board/freescale/ls1012ardb/ |
| D | README | 6 optimized to support the high-bandwidth DDR3L memory and
21 - 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s
62 - 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s
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| /external/u-boot/board/freescale/ls1012aqds/ |
| D | README | 6 optimized to support the high-bandwidth DDR3L memory and
21 - 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s
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| /external/u-boot/board/freescale/ls1012afrdm/ |
| D | README | 6 high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports.
18 - 4 Gb DDR3L SDRAM memory, running at data rates up to 1 GT/s
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| /external/u-boot/board/freescale/t102xqds/ |
| D | README | 24 - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support
88 - Supports one DDR4 or DDR3L module using DDR4 to DDR3L adapter card.
90 - DDR power supplies 1.35V (DDR3L)/1.20V (DDR4) to all devices with automatic tracking of VTT.
124 - DDR3L/DDR4 power supply for GVDD: 1.35 or 1.20V at up to 22A.
214 $ make T1024QDS_defconfig (For DDR3L, by default)
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| /external/u-boot/board/tbs/tbs2910/ |
| D | tbs2910.cfg | 34 * DDR3/DDR3L settings
36 * 4x256Mx16 DDR3L-1066 7-7-7
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| /external/u-boot/arch/x86/include/asm/arch-quark/ |
| D | mrc.h | 45 DDR3L enumerator
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| /external/u-boot/board/freescale/ls1021aqds/ |
| D | README | 21 CAN controller for implementing industrial protocols, DDR3L/4 running
36 - One DDR3L/DDR4 SDRAM memory controller with x8/x16/x32-bit configuration
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| /external/u-boot/board/freescale/ls1021atwr/ |
| D | README | 21 CAN controller for implementing industrial protocols, DDR3L/4 running
36 - One DDR3L/DDR4 SDRAM memory controller with x8/x16/x32-bit configuration
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| /external/u-boot/board/freescale/ls1021aiot/ |
| D | README | 9 - Supports 1GB un-buffered DDR3L SDRAM discrete
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| /external/u-boot/board/toradex/colibri_imx7/ |
| D | imximage.cfg | 47 /* DDR3L */
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| /external/u-boot/arch/arm/dts/ |
| D | stm32mp15-ddr3-2x4Gb-1066-binG.dtsi | 7 * 2x DDR3L 4Gb each, 16-bit, 533MHz, Single Die Package in flyby topology.
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| /external/u-boot/board/intel/ |
| D | Kconfig | 15 Intel quad-core Atom Processor E3800 with dual-channel DDR3L SODIMM
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| /external/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/ |
| D | README.soc | 21 - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
135 - One 16-bit DDR3L SDRAM memory controller, Up to 1.0 GT/s, Supports
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| /external/u-boot/board/freescale/t102xrdb/ |
| D | README | 24 - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support
82 - Supports 64-bit 4GB DDR3L DIMM
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| /external/u-boot/board/freescale/t1040qds/ |
| D | README | 17 - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
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| /external/u-boot/board/freescale/t104xrdb/ |
| D | README | 48 - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
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| /external/u-boot/drivers/power/ |
| D | Kconfig | 150 should be 1.5V, 1.35V if DDR3L is used.
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| /external/u-boot/ |
| D | README | 458 Freescale DDR3 or DDR3L controllers.
461 Board config to use DDR3L. It can be enabled for SoCs with
462 DDR3L controllers.
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