1Overview 2-------- 3The LS1021ATWR is a Freescale reference board that hosts the LS1021A SoC. 4 5LS1021A SoC Overview 6------------------ 7The QorIQ LS1 family, which includes the LS1021A communications processor, 8is built on Layerscape architecture, the industry's first software-aware, 9core-agnostic networking architecture to offer unprecedented efficiency 10and scale. 11 12A member of the value-performance tier, the QorIQ LS1021A processor provides 13extensive integration and power efficiency for fanless, small form factor 14enterprise networking applications. Incorporating dual ARM Cortex-A7 cores 15running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark 16performance of over 6,000, as well as virtualization support, advanced 17security features and the broadest array of high-speed interconnects and 18optimized peripheral features ever offered in a sub-3 W processor. 19 20The QorIQ LS1021A processor features an integrated LCD controller, 21CAN controller for implementing industrial protocols, DDR3L/4 running 22up to 1600 MHz, integrated security engine and QUICC Engine, and ECC 23protection on both L1 and L2 caches. The LS1021A processor is pin- and 24software-compatible with the QorIQ LS1020A and LS1022A processors. 25 26The LS1021A SoC includes the following function and features: 27 28 - ARM Cortex-A7 MPCore compliant with ARMv7-A architecture 29 - Dual high-preformance ARM Cortex-A7 cores, each core includes: 30 - 32 Kbyte L1 Instruction Cache and Data Cache for each core (ECC protection) 31 - 512 Kbyte shared coherent L2 Cache (with ECC protection) 32 - NEON Co-processor (per core) 33 - 40-bit physical addressing 34 - Vector floating-point support 35 - ARM Core-Link CCI-400 Cache Coherent Interconnect 36 - One DDR3L/DDR4 SDRAM memory controller with x8/x16/x32-bit configuration 37 supporting speeds up to 1600Mtps 38 - ECC and interleaving support 39 - VeTSEC Ethernet complex 40 - Up to 3x virtualized 10/100/1000 Ethernet controllers 41 - MII, RMII, RGMII, and SGMII support 42 - QoS, lossless flow control, and IEEE 1588 support 43 - 4-lane 6GHz SerDes 44 - High speed interconnect (4 SerDes lanes with are muxed for these protocol) 45 - Two PCI Express Gen2 controllers running at up to 5 GHz 46 - One Serial ATA 3.0 supporting 6 GT/s operation 47 - Two SGMII interfaces supporting 1000 Mbps 48 - Additional peripheral interfaces 49 - One high-speed USB 3.0 controller with integrated PHY and one high-speed 50 USB 2.00 controller with ULPI 51 - Integrated flash controller (IFC) with 16-bit interface 52 - Quad SPI NOR Flash 53 - One enhanced Secure digital host controller 54 - Display controller unit (DCU) 24-bit RGB (12-bit DDR pin interface) 55 - Ten UARTs comprised of two 16550 compliant DUARTs, and six low power 56 UARTs 57 - Three I2C controllers 58 - Eight FlexTimers four supporting PWM and four FlexCAN ports 59 - Four GPIO controllers supporting up to 109 general purpose I/O signals 60 - Integrated advanced audio block: 61 - Four synchronous audio interfaces (SAI) 62 - Sony/Philips Digital Interconnect Format (SPDIF) 63 - Asynchronous Sample Rate Converter (ASRC) 64 - Hardware based crypto offload engine 65 - IPSec forwarding at up to 1Gbps 66 - QorIQ Trust Architecture, Secure Boot, and ARM TrustZone supported 67 - Public key hardware accelerator 68 - True Random Number Generator (NIST Certified) 69 - Advanced Encryption Standard Accelerators (AESA) 70 - Data Encryption Standard Accelerators 71 - QUICC Engine ULite block 72 - Two universal communication controllers (TDM and HDLC) supporting 64 73 multichannels, each running at 64 Kbps 74 - Support for 256 channels of HDLC 75 - QorIQ TrustArchitecture with Secure Boot, as well as ARM TrustZone supported 76 77LS1021ATWR board Overview 78------------------------- 79 - DDR Controller 80 - Supports rates of up to 1600 MHz data-rate 81 - Supports one DDR3LP SDRAM. 82 - IFC/Local Bus 83 - NOR: 128MB 16-bit NOR Flash 84 - Ethernet 85 - Three on-board RGMII 10/100/1G ethernet ports. 86 - CPLD 87 - Clocks 88 - System and DDR clock (SYSCLK, DDRCLK) 89 - SERDES clocks 90 - Power Supplies 91 - SDHC 92 - SDHC/SDXC connector 93 - Other IO 94 - One Serial port 95 - Three I2C ports 96 97Memory map 98----------- 99The addresses in brackets are physical addresses. 100 101Start Address End Address Description Size 1020x00_0000_0000 0x00_000F_FFFF Secure Boot ROM 1MB 1030x00_0100_0000 0x00_0FFF_FFFF CCSRBAR 240MB 1040x00_1000_0000 0x00_1000_FFFF OCRAM0 64KB 1050x00_1001_0000 0x00_1001_FFFF OCRAM1 64KB 1060x00_2000_0000 0x00_20FF_FFFF DCSR 16MB 1070x00_4000_0000 0x00_5FFF_FFFF QSPI 512MB 1080x00_6000_0000 0x00_67FF_FFFF IFC - NOR Flash 128MB 1090x00_8000_0000 0x00_FFFF_FFFF DRAM1 2GB 110 111LS1021a rev1.0 Soc specific Options/Settings 112-------------------------------------------- 113If the LS1021a Soc is rev1.0, you need modify the configure file. 114Add the following define in include/configs/ls1021atwr.h: 115#define CONFIG_SKIP_LOWLEVEL_INIT 116