| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/instverify/ |
| D | dext-pos.mir | 45 %1 = DEXT %0, 55, 10
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| D | dext-size.mir | 45 %1 = DEXT %0, 5, 50
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| /external/clang/test/Parser/ |
| D | opencl-atomics-cl20.cl | 3 // RUN: %clang_cc1 %s -triple spir-unknown-unknown -verify -fsyntax-only -cl-std=CL2.0 -DCL20 -DEXT…
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| /external/v8/src/mips64/ |
| D | constants-mips64.h | 579 DEXT = ((0U << 3) + 3), enumerator
1779 case DEXT: in InstructionType()
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| D | disasm-mips64.cc | 1742 case DEXT: { in DecodeTypeRegisterSPECIAL3()
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| D | assembler-mips64.cc | 2888 GenInstrRegister(SPECIAL3, rs, rt, size - 1, pos, DEXT); in dext_()
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| D | simulator-mips64.cc | 4168 case DEXT: { // Mips64r2 instruction. in DecodeTypeRegisterSPECIAL3()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsInstrInfo.cpp | 770 case Mips::DEXT: in verifyInstruction()
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| D | Mips64InstrInfo.td | 368 def DEXT : ExtBase<"dext", GPR64Opnd, uimm5_report_uimm6,
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| /external/llvm/lib/Target/Mips/ |
| D | MicroMips64r6InstrInfo.td | 108 // DEXT: 0 < pos + size <= 63
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| D | Mips64InstrInfo.td | 314 def DEXT : ExtBase<"dext", GPR64Opnd, uimm5_report_uimm6, uimm5_plus1,
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| /external/capstone/arch/Mips/ |
| D | MipsGenAsmWriter.inc | 557 1107321667U, // DEXT
2271 5U, // DEXT
4822 // ANDi, ANDi64, ANDi_MM, APPEND, BALIGN, CINS, CINS32, DEXT, DEXTM, DEXT...
4845 // ALIGN, CINS, CINS32, DALIGN, DEXT, DEXTM, DEXTU, DINS, DINSM, DINSU, D...
4859 // DEXT, DEXTM, DEXTU, DINS, DINSM, DINSU, EXT, EXT_MM, INS, INS_MM, MADD...
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| D | MipsGenDisassemblerTables.inc | 4535 /* 2054 */ MCD_OPC_Decode, 156, 4, 247, 1, // Opcode: DEXT
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/Disassembler/ |
| D | MipsDisassembler.cpp | 1072 case Mips::DEXT: in DecodeDEXT()
1088 MI.setOpcode(Mips::DEXT); in DecodeDEXT()
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenAsmWriter.inc | 2406 268459502U, // DEXT
5037 1612U, // DEXT
6980 // BCLRI_D, BNEGI_D, BSETI_D, DEXT, DEXT64_32, DINS, DROTR, DSLL, DSRA, D...
7056 // ALIGN, ALIGN_MMR6, CINS, CINS32, CINS64_32, CINS_i32, DALIGN, DEXT, DE...
7095 // DEXT
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| D | MipsGenMCCodeEmitter.inc | 1191 UINT64_C(2080374787), // DEXT
5840 case Mips::DEXT:
8917 Feature_HasStdEnc | Feature_HasMips64r2 | Feature_NotInMicroMips | 0, // DEXT = 1178
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| D | MipsGenInstrInfo.inc | 1193 DEXT = 1178,
5238 …178, 4, 1, 4, 92, 0, 0x1ULL, nullptr, nullptr, OperandInfo191, -1 ,nullptr }, // Inst #1178 = DEXT
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| D | MipsGenDisassemblerTables.inc | 7009 /* 1052 */ MCD::OPC_Decode, 154, 9, 244, 2, // Opcode: DEXT
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| D | MipsGenAsmMatcher.inc | 5936 …{ 3165 /* dext */, Mips::DEXT, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_0_Report_UIm…
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| D | MipsGenDAGISel.inc | 12835 /* 23635*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DEXT), 0,
12838 …// Dst: (DEXT:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i32] }):$pos, (imm:{ *:[i32] }):$si…
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 5271 case Mips::DEXT: { in checkTargetMatchPredicate()
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