| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/instverify/ |
| D | dextm-pos-size.mir | 45 %1 = DEXTM %0, 3, 62
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| D | dextm-size.mir | 45 %1 = DEXTM %0, 31, 67
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| D | dextm-pos.mir | 45 %1 = DEXTM %0, 65, 5
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| /external/v8/src/mips64/ |
| D | constants-mips64.h | 577 DEXTM = ((0U << 3) + 1), enumerator
1780 case DEXTM: in InstructionType()
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| D | disasm-mips64.cc | 1746 case DEXTM: { in DecodeTypeRegisterSPECIAL3()
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| D | assembler-mips64.cc | 2895 GenInstrRegister(SPECIAL3, rs, rt, size - 1 - 32, pos, DEXTM); in dextm_()
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| D | simulator-mips64.cc | 4179 case DEXTM: { in DecodeTypeRegisterSPECIAL3()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsInstrInfo.cpp | 772 case Mips::DEXTM: in verifyInstruction()
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| D | Mips64InstrInfo.td | 371 def DEXTM : ExtBase<"dextm", GPR64Opnd, uimm5, uimm5_plus33, immZExt5,
960 (DEXTM GPR64Opnd:$rt, GPR64Opnd:$rs, uimm5:$pos,
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| /external/llvm/lib/Target/Mips/ |
| D | MicroMips64r6InstrInfo.td | 109 // DEXTM, DEXTU: 32 < pos + size <= 64
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| D | Mips64InstrInfo.td | 317 def DEXTM : ExtBase<"dextm", GPR64Opnd, uimm5, uimm5_plus33, immZExt5,
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| /external/capstone/arch/Mips/ |
| D | MipsGenAsmWriter.inc | 558 1107321642U, // DEXTM
2272 5U, // DEXTM
4822 // ANDi, ANDi64, ANDi_MM, APPEND, BALIGN, CINS, CINS32, DEXT, DEXTM, DEXT...
4845 // ALIGN, CINS, CINS32, DALIGN, DEXT, DEXTM, DEXTU, DINS, DINSM, DINSU, D...
4859 // DEXT, DEXTM, DEXTU, DINS, DINSM, DINSU, EXT, EXT_MM, INS, INS_MM, MADD...
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| D | MipsGenDisassemblerTables.inc | 4529 /* 2028 */ MCD_OPC_Decode, 157, 4, 247, 1, // Opcode: DEXTM
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/Disassembler/ |
| D | MipsDisassembler.cpp | 1076 case Mips::DEXTM: in DecodeDEXT()
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenAsmWriter.inc | 2408 268458290U, // DEXTM
5039 2628U, // DEXTM
7105 // DEXTM
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| D | MipsGenMCCodeEmitter.inc | 1193 UINT64_C(2080374785), // DEXTM
5842 case Mips::DEXTM:
8919 Feature_HasStdEnc | Feature_HasMips64r2 | Feature_NotInMicroMips | 0, // DEXTM = 1180
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| D | MipsGenAsmMatcher.inc | 5934 …{ 3165 /* dext */, Mips::DEXTM, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__Const…
5937 …{ 3170 /* dextm */, Mips::DEXTM, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__Cons…
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| D | MipsGenInstrInfo.inc | 1195 DEXTM = 1180,
5240 …80, 4, 1, 4, 92, 0, 0x1ULL, nullptr, nullptr, OperandInfo191, -1 ,nullptr }, // Inst #1180 = DEXTM
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| D | MipsGenDisassemblerTables.inc | 7003 /* 1022 */ MCD::OPC_Decode, 156, 9, 244, 2, // Opcode: DEXTM
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| D | MipsGenDAGISel.inc | 12847 /* 23657*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DEXTM), 0,
12850 …// Dst: (DEXTM:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i32] }):$pos, (imm:{ *:[i32] }):$s…
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 5280 case Mips::DEXTM: in checkTargetMatchPredicate()
|