Searched refs:DEXTU (Results 1 – 22 of 22) sorted by relevance
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/instverify/ |
| D | dextu-pos.mir | 45 %1 = DEXTU %0, 64, 5
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| D | dextu-size.mir | 45 %1 = DEXTU %0, 33, 67
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| D | dextu-size-valid.mir | 45 %1 = DEXTU %0, 63, 1
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| D | dextu-pos-size.mir | 45 %1 = DEXTU %0, 43, 30
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| /external/v8/src/mips64/ |
| D | constants-mips64.h | 578 DEXTU = ((0U << 3) + 2), enumerator
1781 case DEXTU: in InstructionType()
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| D | disasm-mips64.cc | 1750 case DEXTU: { in DecodeTypeRegisterSPECIAL3()
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| D | assembler-mips64.cc | 2902 GenInstrRegister(SPECIAL3, rs, rt, size - 1, pos - 32, DEXTU); in dextu_()
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| D | simulator-mips64.cc | 4190 case DEXTU: { in DecodeTypeRegisterSPECIAL3()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsInstrInfo.cpp | 774 case Mips::DEXTU: in verifyInstruction()
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| D | Mips64InstrInfo.td | 373 def DEXTU : ExtBase<"dextu", GPR64Opnd, uimm5_plus32, uimm5_plus1,
963 (DEXTU GPR64Opnd:$rt, GPR64Opnd:$rs, uimm5_plus32:$pos,
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| /external/llvm/lib/Target/Mips/ |
| D | MicroMips64r6InstrInfo.td | 109 // DEXTM, DEXTU: 32 < pos + size <= 64
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| D | Mips64InstrInfo.td | 319 def DEXTU : ExtBase<"dextu", GPR64Opnd, uimm5_plus32, uimm5_plus1,
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| /external/capstone/arch/Mips/ |
| D | MipsGenAsmWriter.inc | 559 1107321680U, // DEXTU
2273 5U, // DEXTU
4845 // ALIGN, CINS, CINS32, DALIGN, DEXT, DEXTM, DEXTU, DINS, DINSM, DINSU, D...
4859 // DEXT, DEXTM, DEXTU, DINS, DINSM, DINSU, EXT, EXT_MM, INS, INS_MM, MADD...
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| D | MipsGenDisassemblerTables.inc | 4532 /* 2041 */ MCD_OPC_Decode, 158, 4, 247, 1, // Opcode: DEXTU
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/Disassembler/ |
| D | MipsDisassembler.cpp | 1080 case Mips::DEXTU: in DecodeDEXT()
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenAsmWriter.inc | 2409 268459691U, // DEXTU
5040 222U, // DEXTU
7019 // DEXTU, DINSU
7065 // DEXTU
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| D | MipsGenMCCodeEmitter.inc | 1194 UINT64_C(2080374786), // DEXTU
5843 case Mips::DEXTU:
8920 Feature_HasStdEnc | Feature_HasMips64r2 | Feature_NotInMicroMips | 0, // DEXTU = 1181
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| D | MipsGenAsmMatcher.inc | 5935 …{ 3165 /* dext */, Mips::DEXTU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__Cons…
5938 …{ 3176 /* dextu */, Mips::DEXTU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__Con…
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| D | MipsGenInstrInfo.inc | 1196 DEXTU = 1181,
5241 …81, 4, 1, 4, 92, 0, 0x1ULL, nullptr, nullptr, OperandInfo191, -1 ,nullptr }, // Inst #1181 = DEXTU
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| D | MipsGenDisassemblerTables.inc | 7006 /* 1037 */ MCD::OPC_Decode, 157, 9, 244, 2, // Opcode: DEXTU
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| D | MipsGenDAGISel.inc | 12864 /* 23687*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::DEXTU), 0,
12867 …// Dst: (DEXTU:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i32] }):$pos, (imm:{ *:[i32] }):$s…
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 5281 case Mips::DEXTU: { in checkTargetMatchPredicate()
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