| /external/u-boot/arch/arm/include/asm/ |
| D | barriers.h | 35 #define DMB asm volatile ("dmb sy" : : : "memory") macro
39 #define DMB CP15DMB macro
43 #define DMB asm volatile ("" : : : "memory") macro
48 #define dmb() DMB
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| /external/libavc/common/arm/ |
| D | ih264_arm_memory_barrier.s | 62 @* Description : Adds DMB
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| D | invalid-barrier.s | 5 @ DMB
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| D | basic-arm-instructions-v8.s | 20 @ DMB (v8 barriers)
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| D | basic-thumb2-instructions-v8.s | 60 @ DMB (ARMv8-only barriers)
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| /external/llvm/test/MC/ARM/ |
| D | invalid-barrier.s | 5 @ DMB
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| D | basic-arm-instructions-v8.s | 20 @ DMB (v8 barriers)
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| D | basic-thumb2-instructions-v8.s | 50 @ DMB (ARMv8-only barriers)
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| /external/llvm/lib/Target/ARM/ |
| D | ARMOptimizeBarriersPass.cpp | 70 if (MI.getOpcode() == ARM::DMB) { in runOnMachineFunction()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMOptimizeBarriersPass.cpp | 68 if (MI.getOpcode() == ARM::DMB) { in runOnMachineFunction()
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| /external/llvm/test/CodeGen/AArch64/ |
| D | atomic-ops-not-barriers.ll | 20 ; simple_ver basic block, which LLVM attempted to do when DMB had been marked
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| D | intrinsics-memory-barrier.ll | 18 ; instructions around DMB.
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/ |
| D | atomic-ops-not-barriers.ll | 20 ; simple_ver basic block, which LLVM attempted to do when DMB had been marked
|
| D | intrinsics-memory-barrier.ll | 18 ; instructions around DMB.
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | intrinsics-memory-barrier.ll | 13 ; instructions around DMB.
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| /external/llvm/test/CodeGen/ARM/ |
| D | intrinsics-memory-barrier.ll | 13 ; instructions around DMB.
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| /external/u-boot/arch/arm/mach-omap2/omap3/ |
| D | lowlevel_init.S | 33 mcr p15, 0, r0, c7, c10, 5 @ DMB
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrAtomics.td | 17 def : Pat<(atomic_fence (i64 4), (imm)), (DMB (i32 0x9))>;
18 def : Pat<(atomic_fence (imm), (imm)), (DMB (i32 0xb))>;
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| D | AArch64SchedCyclone.td | 292 // SLREX,DMB,DSB
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstrAtomics.td | 20 def : Pat<(atomic_fence (i64 4), (imm)), (DMB (i32 0x9))>;
21 def : Pat<(atomic_fence (imm), (imm)), (DMB (i32 0xb))>;
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| D | AArch64SchedCyclone.td | 294 // SLREX,DMB,DSB
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| D | AArch64SchedFalkorDetails.td | 1245 def : InstRW<[FalkorWr_1LD_0cyc], (instrs CLREX, DMB, DSB)>;
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| /external/v8/src/arm64/ |
| D | constants-arm64.h | 775 DMB = MemBarrierFixed | 0x00000020, enumerator
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| D | disasm-arm64.cc | 1257 case DMB: { in VisitSystem()
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| /external/vixl/src/aarch64/ |
| D | constants-aarch64.h | 756 DMB = MemBarrierFixed | 0x00000020, enumerator
|