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1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Board specific setup info
4 *
5 * (C) Copyright 2008
6 * Texas Instruments, <www.ti.com>
7 *
8 * Initial Code by:
9 * Richard Woodruff <r-woodruff2@ti.com>
10 * Syed Mohammed Khasim <khasim@ti.com>
11 */
12
13#include <config.h>
14#include <asm/arch/mem.h>
15#include <asm/arch/clocks_omap3.h>
16#include <linux/linkage.h>
17
18/*
19 * Funtion for making PPA HAL API calls in secure devices
20 * Input:
21 *	R0 - Service ID
22 *	R1 - paramer list
23 */
24ENTRY(do_omap3_emu_romcode_call)
25	PUSH {r4-r12, lr} @ Save all registers from ROM code!
26	MOV r12, r0	@ Copy the Secure Service ID in R12
27	MOV r3, r1	@ Copy the pointer to va_list in R3
28	MOV r1, #0	@ Process ID - 0
29	MOV r2, #OMAP3_EMU_HAL_START_HAL_CRITICAL	@ Copy the pointer
30							@ to va_list in R3
31	MOV r6, #0xFF	@ Indicate new Task call
32	mcr     p15, 0, r0, c7, c10, 4	@ DSB
33	mcr     p15, 0, r0, c7, c10, 5	@ DMB
34	.word	0xe1600071	@ SMC #1 to call PPA service - hand assembled
35				@ because we use -march=armv5
36	POP {r4-r12, pc}
37ENDPROC(do_omap3_emu_romcode_call)
38
39#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_NAND_BOOT)
40/**************************************************************************
41 * cpy_clk_code: relocates clock code into SRAM where its safer to execute
42 * R1 = SRAM destination address.
43 *************************************************************************/
44ENTRY(cpy_clk_code)
45	/* Copy DPLL code into SRAM */
46	adr	r0, go_to_speed		/* copy from start of go_to_speed... */
47	adr	r2, lowlevel_init	/* ... up to start of low_level_init */
48next2:
49	ldmia	r0!, {r3 - r10}		/* copy from source address [r0] */
50	stmia	r1!, {r3 - r10}		/* copy to   target address [r1] */
51	cmp	r0, r2			/* until source end address [r2] */
52	blo	next2
53	mov	pc, lr			/* back to caller */
54ENDPROC(cpy_clk_code)
55
56/* ***************************************************************************
57 *  go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
58 *               -executed from SRAM.
59 *  R0 = CM_CLKEN_PLL-bypass value
60 *  R1 = CM_CLKSEL1_PLL-m, n, and divider values
61 *  R2 = CM_CLKSEL_CORE-divider values
62 *  R3 = CM_IDLEST_CKGEN - addr dpll lock wait
63 *
64 *  Note: If core unlocks/relocks and SDRAM is running fast already it gets
65 *        confused.  A reset of the controller gets it back.  Taking away its
66 *        L3 when its not in self refresh seems bad for it.  Normally, this
67 *	  code runs from flash before SDR is init so that should be ok.
68 ****************************************************************************/
69ENTRY(go_to_speed)
70	stmfd sp!, {r4 - r6}
71
72	/* move into fast relock bypass */
73	ldr	r4, pll_ctl_add
74	str	r0, [r4]
75wait1:
76	ldr	r5, [r3]		/* get status */
77	and	r5, r5, #0x1		/* isolate core status */
78	cmp	r5, #0x1		/* still locked? */
79	beq	wait1			/* if lock, loop */
80
81	/* set new dpll dividers _after_ in bypass */
82	ldr	r5, pll_div_add1
83	str	r1, [r5]		/* set m, n, m2 */
84	ldr	r5, pll_div_add2
85	str	r2, [r5]		/* set l3/l4/.. dividers*/
86	ldr	r5, pll_div_add3	/* wkup */
87	ldr	r2, pll_div_val3	/* rsm val */
88	str	r2, [r5]
89	ldr	r5, pll_div_add4	/* gfx */
90	ldr	r2, pll_div_val4
91	str	r2, [r5]
92	ldr	r5, pll_div_add5	/* emu */
93	ldr	r2, pll_div_val5
94	str	r2, [r5]
95
96	/* now prepare GPMC (flash) for new dpll speed */
97	/* flash needs to be stable when we jump back to it */
98	ldr	r5, flash_cfg3_addr
99	ldr	r2, flash_cfg3_val
100	str	r2, [r5]
101	ldr	r5, flash_cfg4_addr
102	ldr	r2, flash_cfg4_val
103	str	r2, [r5]
104	ldr	r5, flash_cfg5_addr
105	ldr	r2, flash_cfg5_val
106	str	r2, [r5]
107	ldr	r5, flash_cfg1_addr
108	ldr	r2, [r5]
109	orr	r2, r2, #0x3		/* up gpmc divider */
110	str	r2, [r5]
111
112	/* lock DPLL3 and wait a bit */
113	orr	r0, r0, #0x7	/* set up for lock mode */
114	str	r0, [r4]	/* lock */
115	nop			/* ARM slow at this point working at sys_clk */
116	nop
117	nop
118	nop
119wait2:
120	ldr	r5, [r3]	/* get status */
121	and	r5, r5, #0x1	/* isolate core status */
122	cmp	r5, #0x1	/* still locked? */
123	bne	wait2		/* if lock, loop */
124	nop
125	nop
126	nop
127	nop
128	ldmfd	sp!, {r4 - r6}
129	mov	pc, lr		/* back to caller, locked */
130ENDPROC(go_to_speed)
131
132_go_to_speed: .word go_to_speed
133
134/* these constants need to be close for PIC code */
135/* The Nor has to be in the Flash Base CS0 for this condition to happen */
136flash_cfg1_addr:
137	.word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG1)
138flash_cfg3_addr:
139	.word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG3)
140flash_cfg3_val:
141	.word STNOR_GPMC_CONFIG3
142flash_cfg4_addr:
143	.word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG4)
144flash_cfg4_val:
145	.word STNOR_GPMC_CONFIG4
146flash_cfg5_val:
147	.word STNOR_GPMC_CONFIG5
148flash_cfg5_addr:
149	.word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG5)
150pll_ctl_add:
151	.word CM_CLKEN_PLL
152pll_div_add1:
153	.word CM_CLKSEL1_PLL
154pll_div_add2:
155	.word CM_CLKSEL_CORE
156pll_div_add3:
157	.word CM_CLKSEL_WKUP
158pll_div_val3:
159	.word (WKUP_RSM << 1)
160pll_div_add4:
161	.word CM_CLKSEL_GFX
162pll_div_val4:
163	.word (GFX_DIV << 0)
164pll_div_add5:
165	.word CM_CLKSEL1_EMU
166pll_div_val5:
167	.word CLSEL1_EMU_VAL
168
169#endif
170
171ENTRY(lowlevel_init)
172	ldr	sp, SRAM_STACK
173	str	ip, [sp]	/* stash ip register */
174	mov	ip, lr		/* save link reg across call */
175#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT)
176/*
177 * No need to copy/exec the clock code - DPLL adjust already done
178 * in NAND/oneNAND Boot.
179 */
180	ldr	r1, =SRAM_CLK_CODE
181	bl	cpy_clk_code
182#endif /* NAND Boot */
183	mov	lr, ip		/* restore link reg */
184	ldr	ip, [sp]	/* restore save ip */
185	/* tail-call s_init to setup pll, mux, memory */
186	b	s_init
187
188ENDPROC(lowlevel_init)
189
190	/* the literal pools origin */
191	.ltorg
192
193REG_CONTROL_STATUS:
194	.word CONTROL_STATUS
195SRAM_STACK:
196	.word LOW_LEVEL_SRAM_STACK
197
198/* DPLL(1-4) PARAM TABLES */
199
200/*
201 * Each of the tables has M, N, FREQSEL, M2 values defined for nominal
202 * OPP (1.2V). The fields are defined according to dpll_param struct (clock.c).
203 * The values are defined for all possible sysclk and for ES1 and ES2.
204 */
205
206mpu_dpll_param:
207/* 12MHz */
208/* ES1 */
209.word MPU_M_12_ES1, MPU_N_12_ES1, MPU_FSEL_12_ES1, MPU_M2_12_ES1
210/* ES2 */
211.word MPU_M_12_ES2, MPU_N_12_ES2, MPU_FSEL_12_ES2, MPU_M2_ES2
212/* 3410 */
213.word MPU_M_12, MPU_N_12, MPU_FSEL_12, MPU_M2_12
214
215/* 13MHz */
216/* ES1 */
217.word MPU_M_13_ES1, MPU_N_13_ES1, MPU_FSEL_13_ES1, MPU_M2_13_ES1
218/* ES2 */
219.word MPU_M_13_ES2, MPU_N_13_ES2, MPU_FSEL_13_ES2, MPU_M2_13_ES2
220/* 3410 */
221.word MPU_M_13, MPU_N_13, MPU_FSEL_13, MPU_M2_13
222
223/* 19.2MHz */
224/* ES1 */
225.word MPU_M_19P2_ES1, MPU_N_19P2_ES1, MPU_FSEL_19P2_ES1, MPU_M2_19P2_ES1
226/* ES2 */
227.word MPU_M_19P2_ES2, MPU_N_19P2_ES2, MPU_FSEL_19P2_ES2, MPU_M2_19P2_ES2
228/* 3410 */
229.word MPU_M_19P2, MPU_N_19P2, MPU_FSEL_19P2, MPU_M2_19P2
230
231/* 26MHz */
232/* ES1 */
233.word MPU_M_26_ES1, MPU_N_26_ES1, MPU_FSEL_26_ES1, MPU_M2_26_ES1
234/* ES2 */
235.word MPU_M_26_ES2, MPU_N_26_ES2, MPU_FSEL_26_ES2, MPU_M2_26_ES2
236/* 3410 */
237.word MPU_M_26, MPU_N_26, MPU_FSEL_26, MPU_M2_26
238
239/* 38.4MHz */
240/* ES1 */
241.word MPU_M_38P4_ES1, MPU_N_38P4_ES1, MPU_FSEL_38P4_ES1, MPU_M2_38P4_ES1
242/* ES2 */
243.word MPU_M_38P4_ES2, MPU_N_38P4_ES2, MPU_FSEL_38P4_ES2, MPU_M2_38P4_ES2
244/* 3410 */
245.word MPU_M_38P4, MPU_N_38P4, MPU_FSEL_38P4, MPU_M2_38P4
246
247
248.globl get_mpu_dpll_param
249get_mpu_dpll_param:
250	adr	r0, mpu_dpll_param
251	mov	pc, lr
252
253iva_dpll_param:
254/* 12MHz */
255/* ES1 */
256.word IVA_M_12_ES1, IVA_N_12_ES1, IVA_FSEL_12_ES1, IVA_M2_12_ES1
257/* ES2 */
258.word IVA_M_12_ES2, IVA_N_12_ES2, IVA_FSEL_12_ES2, IVA_M2_12_ES2
259/* 3410 */
260.word IVA_M_12, IVA_N_12, IVA_FSEL_12, IVA_M2_12
261
262/* 13MHz */
263/* ES1 */
264.word IVA_M_13_ES1, IVA_N_13_ES1, IVA_FSEL_13_ES1, IVA_M2_13_ES1
265/* ES2 */
266.word IVA_M_13_ES2, IVA_N_13_ES2,  IVA_FSEL_13_ES2, IVA_M2_13_ES2
267/* 3410 */
268.word IVA_M_13, IVA_N_13, IVA_FSEL_13, IVA_M2_13
269
270/* 19.2MHz */
271/* ES1 */
272.word IVA_M_19P2_ES1, IVA_N_19P2_ES1, IVA_FSEL_19P2_ES1, IVA_M2_19P2_ES1
273/* ES2 */
274.word IVA_M_19P2_ES2, IVA_N_19P2_ES2, IVA_FSEL_19P2_ES2, IVA_M2_19P2_ES2
275/* 3410 */
276.word IVA_M_19P2, IVA_N_19P2, IVA_FSEL_19P2, IVA_M2_19P2
277
278/* 26MHz */
279/* ES1 */
280.word IVA_M_26_ES1, IVA_N_26_ES1, IVA_FSEL_26_ES1, IVA_M2_26_ES1
281/* ES2 */
282.word IVA_M_26_ES2, IVA_N_26_ES2, IVA_FSEL_26_ES2, IVA_M2_26_ES2
283/* 3410 */
284.word IVA_M_26, IVA_N_26, IVA_FSEL_26, IVA_M2_26
285
286/* 38.4MHz */
287/* ES1 */
288.word IVA_M_38P4_ES1, IVA_N_38P4_ES1, IVA_FSEL_38P4_ES1, IVA_M2_38P4_ES1
289/* ES2 */
290.word IVA_M_38P4_ES2, IVA_N_38P4_ES2, IVA_FSEL_38P4_ES2, IVA_M2_38P4_ES2
291/* 3410 */
292.word IVA_M_38P4, IVA_N_38P4, IVA_FSEL_38P4, IVA_M2_38P4
293
294
295.globl get_iva_dpll_param
296get_iva_dpll_param:
297	adr	r0, iva_dpll_param
298	mov	pc, lr
299
300/* Core DPLL targets for L3 at 166 & L133 */
301core_dpll_param:
302/* 12MHz */
303/* ES1 */
304.word CORE_M_12_ES1, CORE_N_12_ES1, CORE_FSL_12_ES1, CORE_M2_12_ES1
305/* ES2 */
306.word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12
307/* 3410 */
308.word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12
309
310/* 13MHz */
311/* ES1 */
312.word CORE_M_13_ES1, CORE_N_13_ES1, CORE_FSL_13_ES1, CORE_M2_13_ES1
313/* ES2 */
314.word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13
315/* 3410 */
316.word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13
317
318/* 19.2MHz */
319/* ES1 */
320.word CORE_M_19P2_ES1, CORE_N_19P2_ES1, CORE_FSL_19P2_ES1, CORE_M2_19P2_ES1
321/* ES2 */
322.word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2
323/* 3410 */
324.word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2
325
326/* 26MHz */
327/* ES1 */
328.word CORE_M_26_ES1, CORE_N_26_ES1, CORE_FSL_26_ES1, CORE_M2_26_ES1
329/* ES2 */
330.word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26
331/* 3410 */
332.word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26
333
334/* 38.4MHz */
335/* ES1 */
336.word CORE_M_38P4_ES1, CORE_N_38P4_ES1, CORE_FSL_38P4_ES1, CORE_M2_38P4_ES1
337/* ES2 */
338.word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4
339/* 3410 */
340.word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4
341
342.globl get_core_dpll_param
343get_core_dpll_param:
344	adr	r0, core_dpll_param
345	mov	pc, lr
346
347/* PER DPLL values are same for both ES1 and ES2 */
348per_dpll_param:
349/* 12MHz */
350.word PER_M_12, PER_N_12, PER_FSEL_12, PER_M2_12
351
352/* 13MHz */
353.word PER_M_13, PER_N_13, PER_FSEL_13, PER_M2_13
354
355/* 19.2MHz */
356.word PER_M_19P2, PER_N_19P2, PER_FSEL_19P2, PER_M2_19P2
357
358/* 26MHz */
359.word PER_M_26, PER_N_26, PER_FSEL_26, PER_M2_26
360
361/* 38.4MHz */
362.word PER_M_38P4, PER_N_38P4, PER_FSEL_38P4, PER_M2_38P4
363
364.globl get_per_dpll_param
365get_per_dpll_param:
366	adr	r0, per_dpll_param
367	mov	pc, lr
368
369/* PER2 DPLL values */
370per2_dpll_param:
371/* 12MHz */
372.word PER2_M_12, PER2_N_12, PER2_FSEL_12, PER2_M2_12
373
374/* 13MHz */
375.word PER2_M_13, PER2_N_13, PER2_FSEL_13, PER2_M2_13
376
377/* 19.2MHz */
378.word PER2_M_19P2, PER2_N_19P2, PER2_FSEL_19P2, PER2_M2_19P2
379
380/* 26MHz */
381.word PER2_M_26, PER2_N_26, PER2_FSEL_26, PER2_M2_26
382
383/* 38.4MHz */
384.word PER2_M_38P4, PER2_N_38P4, PER2_FSEL_38P4, PER2_M2_38P4
385
386.globl get_per2_dpll_param
387get_per2_dpll_param:
388	adr	r0, per2_dpll_param
389	mov	pc, lr
390
391/*
392 * Tables for 36XX/37XX devices
393 *
394 */
395mpu_36x_dpll_param:
396/* 12MHz */
397.word 50, 0, 0, 1
398/* 13MHz */
399.word 600, 12, 0, 1
400/* 19.2MHz */
401.word 125, 3, 0, 1
402/* 26MHz */
403.word 300, 12, 0, 1
404/* 38.4MHz */
405.word 125, 7, 0, 1
406
407iva_36x_dpll_param:
408/* 12MHz */
409.word 130, 2, 0, 1
410/* 13MHz */
411.word 20, 0, 0, 1
412/* 19.2MHz */
413.word 325, 11, 0, 1
414/* 26MHz */
415.word 10, 0, 0, 1
416/* 38.4MHz */
417.word 325, 23, 0, 1
418
419core_36x_dpll_param:
420/* 12MHz */
421.word 100, 2, 0, 1
422/* 13MHz */
423.word 400, 12, 0, 1
424/* 19.2MHz */
425.word 375, 17, 0, 1
426/* 26MHz */
427.word 200, 12, 0, 1
428/* 38.4MHz */
429.word 375, 35, 0, 1
430
431per_36x_dpll_param:
432/*    SYSCLK    M       N      M2      M3      M4     M5      M6      m2DIV */
433.word 12000,    360,    4,     9,      16,     5,     4,      3,      1
434.word 13000,    864,   12,     9,      16,     9,     4,      3,      1
435.word 19200,    360,    7,     9,      16,     5,     4,      3,      1
436.word 26000,    432,   12,     9,      16,     9,     4,      3,      1
437.word 38400,    360,   15,     9,      16,     5,     4,      3,      1
438
439per2_36x_dpll_param:
440/* 12MHz */
441.word PER2_36XX_M_12, PER2_36XX_N_12, 0, PER2_36XX_M2_12
442/* 13MHz */
443.word PER2_36XX_M_13, PER2_36XX_N_13, 0, PER2_36XX_M2_13
444/* 19.2MHz */
445.word PER2_36XX_M_19P2, PER2_36XX_N_19P2, 0, PER2_36XX_M2_19P2
446/* 26MHz */
447.word PER2_36XX_M_26, PER2_36XX_N_26, 0, PER2_36XX_M2_26
448/* 38.4MHz */
449.word PER2_36XX_M_38P4, PER2_36XX_N_38P4, 0, PER2_36XX_M2_38P4
450
451
452ENTRY(get_36x_mpu_dpll_param)
453	adr	r0, mpu_36x_dpll_param
454	mov	pc, lr
455ENDPROC(get_36x_mpu_dpll_param)
456
457ENTRY(get_36x_iva_dpll_param)
458	adr	r0, iva_36x_dpll_param
459	mov	pc, lr
460ENDPROC(get_36x_iva_dpll_param)
461
462ENTRY(get_36x_core_dpll_param)
463	adr	r0, core_36x_dpll_param
464	mov	pc, lr
465ENDPROC(get_36x_core_dpll_param)
466
467ENTRY(get_36x_per_dpll_param)
468	adr	r0, per_36x_dpll_param
469	mov	pc, lr
470ENDPROC(get_36x_per_dpll_param)
471
472ENTRY(get_36x_per2_dpll_param)
473	adr	r0, per2_36x_dpll_param
474	mov	pc, lr
475ENDPROC(get_36x_per2_dpll_param)
476